JPH10274964A - Liquid crystal display device driving circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the number of input terminals and power consumption in a liquid crystal display device driving circuit and to improve the definition of display image. SOLUTION: A frequency divider 36 is provided in the drive circuit driving a simple matrix type liquid crystal display device by a line sequential scan system, and a clock signal together with an image signal are imparted from an external microcomputer generating the image signal. The timing of outputs of a common output part 37 supplying an applied voltage to a common electrode group and a segment output part 38 supplying the applied voltage to a segment electrode group are controlled by a clock obtained by frequency dividing this clock signal. The input terminal required for clock generation for a scan becomes one, and a scan frequency is set based on the clock with high precision.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving circuit for driving a dot matrix type liquid crystal display device by a line sequential scanning method.

[0002]

2. Description of the Related Art A simple dot matrix type liquid crystal display device has a liquid crystal panel comprising a liquid crystal layer and a common electrode group and a segment electrode group disposed so as to be orthogonal to each other with the liquid crystal layer interposed therebetween. It is driven by a progressive scanning method (also referred to as a “dynamic driving method”). In the line-sequential scanning method, a common electrode group is sequentially scanned at a predetermined voltage when an effective voltage is applied between a common electrode and a segment electrode to select a pixel for forming an image. By scanning all the common electrodes once, an image of one frame is displayed on the liquid crystal panel. Line-sequential scanning is particularly suitable for a small liquid crystal display device that displays a character string of about several lines, and is often used in a liquid crystal display device attached to a mobile phone, a pager, or the like.

[0003] A driving circuit for driving a liquid crystal panel includes:
The signal of the image to be displayed is given from an external computer,
The voltage applied to the segment electrodes is changed accordingly, but the clock for scanning the common electrodes is independently set according to the frame frequency and the total number of pixels regardless of an external computer. That is, the drive circuit includes a CR oscillation circuit for generating a clock used for scanning the common electrode, and the oscillation frequency is determined by the number of common electrodes × the number of segment electrodes × the frame frequency.

For example, one character is represented by 40 pixels (5 segment electrodes × 8 common electrodes), and 12 characters per line are represented by 2 characters.
When the display is performed at a line / frame frequency of 75 Hz, the frequency of the CR oscillation circuit is 5 × 12 × 8 × 2 × 75 Hz (= 7
2 kHz). When the number of lines is doubled to display four lines, an oscillation frequency of 144 kHz is required.

FIG. 4 shows the appearance of a conventional liquid crystal display device 50. The drive circuit 52 is mounted on a glass plate 53 of the liquid crystal panel 51 (COG mounting), and a terminal group 54 for input to the drive circuit 52 is formed on the glass plate 53.
Two terminals 54a and 54b of the input terminal group 54 are CR
The other terminal is provided for an oscillation circuit, and is used for supplying power from a power source, connecting to a ground potential, and inputting a display signal.

FIG. 5 schematically shows the configuration of the CR oscillation circuit 60. The CR oscillation circuit 60 includes inverters 61 to 64, a capacitor 65, and an external resistor 66.
6 is connected via a terminal 54a and a terminal 54b. The inverters 61 to 64, as shown in FIG.
The channel transistor 67 and the N-channel transistor 68 are connected in series and have a simple configuration. This C
The common electrode is scanned at a frequency obtained by dividing the oscillation frequency of the R oscillation circuit 60.

[0007]

As described above, the driving circuit 52 of the liquid crystal display device using the conventional line-sequential scanning method has a C
An R oscillation circuit 60 is provided, and it is necessary to use two input terminals 54a and 54b to connect to an external resistor 66. However, as the number of terminals increases, a larger space is required for the arrangement. From the viewpoint of reducing the size of the device, it is preferable that the number of input terminals is smaller. It is better to reduce the number of input terminals in order to reduce mounting cost.

In the CR oscillation circuit 60, since the oscillation waveform at the input side (point a) of the foremost inverter 61 is as shown in FIG. 7, the discharging period T1 of the capacitor 65 is also the charging period T2. Also, a current flows through the two transistors 67 and 68. That is, the CR oscillation circuit 60
Always uses electric power, and thus the conventional drive circuit 52 consumes much power.

Furthermore, since the oscillation frequency of the CR oscillation circuit 60 is easily affected by a change in temperature, the scanning frequency fluctuates.
Display image flicker and color unevenness due to crosstalk were likely to occur.

An object of the present invention is to reduce the number of input terminals of a driving circuit of a liquid crystal display device, reduce power consumption, and improve the quality of a displayed image.

[0011]

In order to achieve the above object, according to the present invention, in a driving circuit of a liquid crystal display device for driving a dot matrix type liquid crystal panel by a line sequential scanning system, an image to be displayed on the liquid crystal panel is displayed. A clock signal is supplied from an external computer that generates a signal, and a clock signal for setting a scanning frequency of line-sequential scanning is generated from the clock signal.

This drive circuit is provided with a signal generated by an external computer, and displays an image on a liquid crystal panel according to the signal. The external computer uses a clock signal for controlling various operations including generation of a signal of an image to be displayed, and provides one of the signals to the drive circuit. The drive circuit generates a clock signal for setting a scanning frequency for line-sequential scanning from the supplied clock signal. Therefore, the drive circuit does not need to include an oscillation circuit for setting the scanning frequency, and it is sufficient to provide only one terminal for generating a clock signal for input from an external computer.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the driving circuit of the present invention is applied to a liquid crystal display device of a portable telephone will be described below. FIG. 1 shows a schematic configuration of a mobile phone 1 of the present embodiment. The mobile phone 1 includes an operation unit 11 including a key group used for inputting a telephone number, a memory 12 for storing the name and telephone number of the other party, and a voice input from the microphone 13 as a transmission signal. A communication circuit 1 for converting and sending out, and outputting a received signal as sound from a speaker 14
5. It comprises a liquid crystal display (LCD) 2 for displaying information relating to telephone numbers as characters, and a microcomputer 3 for controlling these components.

The microcomputer 3 comprises a crystal oscillation circuit 4
And generates various clock signals from the oscillation frequency of the crystal oscillation circuit 4, thereby controlling the timing of its own operation and the operation of each peripheral unit. The microcomputer 3 generates a signal representing a character string including the telephone number input from the operation unit 11 and the name and telephone number read from the memory 12, and outputs the signal to the LCD 2. The microcomputer 3 also outputs a 32 kHz rectangular wave of the generated clock signal from the clock output terminal to the LCD.
Output two.

FIG. 2 shows the appearance of the LCD 2. LCD2
Comprises a simple dot matrix type liquid crystal panel 21 and a driving circuit 22 thereof. The liquid crystal panel 21 has 60 segment electrodes and 16 common electrodes, and one character is represented by 40 pixels (5 segment electrodes × 8 common electrodes).
A character string of 12 characters per line can be displayed in two lines. The drive circuit 22 drives the liquid crystal panel 21 by a line sequential scanning method. Its frame frequency is 75 Hz.

The drive circuit 22 is mounted on the glass plate 23 of the liquid crystal panel 21 by COG, and the glass plate 23 is provided with a terminal group 24 for input to the drive circuit 22. One terminal 24a of the input terminal group 24 is connected to a clock output terminal of the microcomputer 3, and the other two terminals are connected to a power supply line and a ground potential line, respectively. The remaining terminals of the input terminal group 24 are connected to terminals of the microcomputer 3 that output signals representing display character strings.

FIG. 3 shows a schematic configuration of the drive circuit 22. The drive circuit 22 includes a timing generator 31, an interface 32, a ROM 33, a RAM 34, a RAM 35,
A frequency divider 36, a common output section 37, and a segment output section 38 are provided. The interface 32 receives a signal representing a display character string output from the microcomputer 3 and supplies the signal to the timing generator 31.

The frequency dividing circuit 36 divides the frequency of the 32 kHz clock signal supplied from the microcomputer via the input terminal 24a to a 1.2 kHz clock signal.
This is connected to the timing generator 31 and the common output unit 37.
And output to

The common output section 37 outputs four levels (two levels of display ON and two levels of display O) from the power supplied from the power supply line.
A voltage of FF (2 levels) is generated and output to each common electrode via 16 output terminal groups 37a. The common output unit 37 outputs the ON-level voltage (hereinafter, referred to as a scanning voltage) of the four-level voltages at one point in time of the voltage output.
Output to one common electrode, and O to all other common electrodes.
An FF level voltage is output. The output destination of the scanning voltage is sequentially changed in accordance with the timing of the 1.2 kHz clock signal supplied from the frequency dividing circuit 36. Thus, line-sequential scanning of the common electrode is performed, and the frame frequency becomes 75 Hz (1.2 kHz / 16).

The ROM 33 stores predetermined fonts of characters and numbers as binary data of 5 × 8 dots. The RAM 34 stores the font of characters and numbers defined by the user as binary data of 5 × 8 dots. The RAM 35 has R
The addresses of the character fonts in the OM 33 and the RAM 34 are stored.

The timing generator 31 reads the address of the ROM 33 or the RAM 34 in which the font of each character is stored from the RAM 35 based on a signal representing a character string provided via the interface 32.
Then, the font data is read from the ROM 33 or the RAM 35 in accordance with the read address, and display data used for controlling the segment output unit 38 is generated.

More specifically, the timing generator 31
Reads out font data (5 dots) for one horizontal line for each of the twelve characters forming one line, and reads out binary display data (60 for one common electrode) from these.
Dot). From the reading of the font data to the generation of the display data is extremely short (<0.83
(Milliseconds = 1 / 1.2 kHz).

The timing generator 31 generates 16 display data one after another corresponding to the 16 common electrodes, and outputs the data of 1.2 kHz supplied from the frequency dividing circuit 36.
At the timing of the clock signal of
Are output sequentially. As a result, image data for one frame of 12 characters × 2 lines is generated, and an image of one frame is displayed on the liquid crystal panel 21 for a period of 1/75 second.

The segment output unit 38 generates high-low two-level voltages from the power supplied from the power supply line,
The signal is output to each segment electrode via the zero output terminal group 38a. The two high-level voltages are supplied to the common output unit 37
Are set in the middle of the two-level voltage output. Which of the two levels of voltage the segment output section 38 outputs to each segment electrode depends on the timing generator 3
It is determined by the display data given from 1.

The combination of the low level voltage of the common output unit 37 and the high level voltage of the segment output unit 38 and the combination of the high level voltage of the common output unit 37 and the low level voltage of the segment output unit 38 The pixel is selected according to the voltage applied to the common electrode and the voltage applied to the segment electrode, and an image is displayed.

The common output section 37 and the segment output section 38
Perform an output operation at 1.2 kHz, and their periods coincide with each other.
The upper row position (vertical image display position) is not set appropriately. For this reason, the timing generator 31 gives a reset instruction to the common output unit 37 every frame period. Upon receiving this instruction, the common output unit 37 sets the scan voltage output destination to the first common electrode, and then sequentially changes the scan voltage output destination. As a result, the display position is appropriately set, and two lines of characters are correctly displayed.

When a reset instruction is given, the common output unit 37 resets the output destination of the scanning voltage,
The level of the scanning voltage is also reversed. That is, scanning is performed such that the level not used as the scanning voltage in the previous frame is used as the scanning voltage, and the level used as the scanning voltage is output to many common electrodes. Common output unit 37
Corresponds to the fact that the level of the scanning voltage is reversed, the timing generator 31 reverses the binary level of the display data to be supplied to the segment output unit 38, and converts the two-level voltage output from the segment output unit 38. Reverse. As a result, the polarity of the voltage applied to the liquid crystal panel 21 is inverted every frame.

In general, the liquid crystal panel is deteriorated when a voltage of the same polarity is applied for a long time. By driving while reversing the polarity, the liquid crystal panel 21 is prevented from deteriorating and its life is extended. Can be achieved. Image display is continuously performed regardless of the polarity inversion of the applied voltage.

Although the above description has been made with respect to the case where two rows of images are displayed as an example, the drive circuit of the present invention can use different numbers of rows without changing the frequency of the clock signal supplied from the microcomputer and the display frame frequency. Can be displayed. For example, doubling the number of display lines to 12
When displaying characters × 4 lines, the frequency dividing ratio of the frequency dividing circuit 36 is halved to output a 2.4 kHz clock signal. As a result, the output period of the segment output unit 38 controlled by the common output unit 37 and the timing generator 31 is halved, and the frame frequency becomes 75%.
Hz.

The frequency of the clock signal supplied from the microcomputer to the drive circuit, the frame frequency of display, the number of common electrodes, the number of segment electrodes, the number of display lines, the number of characters per line, the number of pixels per character, and the like are as described above. The values are not limited to those illustrated in the embodiment, and may be set arbitrarily. What is necessary is just to set suitably according to the use of a liquid crystal display device, and the microcomputer used.

[0031]

According to the drive circuit of the liquid crystal display device of the present invention, it is not necessary to provide an oscillation circuit in the drive circuit itself, so that power for oscillation is not required and power consumption can be reduced. In addition, since two terminals conventionally used for oscillation are reduced to only one input terminal for the clock signal, the device can be easily formed in a small size, and the mounting cost can be reduced. Furthermore, since scanning is performed based on a high-precision clock signal from a computer, the scanning is stable,
A high-quality image without flicker or color unevenness can be displayed.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a schematic configuration of a mobile phone including a liquid crystal display device driven by a driving circuit of the present invention.

FIG. 2 is a diagram illustrating an appearance of a liquid crystal display device including a driving circuit of the present invention.

FIG. 3 is a block diagram showing a schematic configuration of a drive circuit of the present invention.

FIG. 4 is a diagram showing the appearance of a conventional liquid crystal display device.

FIG. 5 is a diagram showing a schematic configuration of a CR oscillation circuit provided in a drive circuit of a conventional liquid crystal display device.

FIG. 6 is a diagram illustrating a configuration of an inverter of a CR oscillation circuit.

FIG. 7 is a diagram showing an oscillation waveform of a CR oscillation circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Mobile telephone 2 Liquid crystal display device 3 Microcomputer 21 Liquid crystal panel 22 Drive circuit 24 Input terminal group 24a Clock signal input terminal 31 Timing generator 32 Interface 33 ROM 34 RAM 35 RAM 36 Divider circuit 37 Common output section 38 Segment output section

Claims (1)

[Claims] In a driving circuit of a liquid crystal display device for driving a dot matrix type liquid crystal panel by a line sequential scanning method, a clock signal is supplied from an external computer for generating an image signal to be displayed on the liquid crystal panel. A driving circuit for a liquid crystal display device, which generates a clock signal for setting a scanning frequency of line sequential scanning from a clock signal.