JPH1027466A - Internal power source generation circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an internal power source generation circuit which can reduce power consumption. SOLUTION: Power source voltage V1 is supplied to one end of a rectifier circuit 3 constituted by connecting rectifying elements 1 and 2 in series in the forward direction X, and an output terminal of a capacity element C is connected to a node N connecting the rectifying elements 1, 2. First and second voltage generation circuits 11, 12 in which input terminal voltage of the capacity element C is varied by charging and discharging electric charges for the capacity element C by operation of a switch circuit 4 operating based on a control signal ϕand output voltage V01 , V02 being different from the power source voltage V1 are outputted to the other end of the rectifier circuit 3 are provided. A switching element SW supplies the charges to the capacity element C of the second voltage generation circuit 12 when electric charges accumulated in the capacity element C of the first voltage generation circuit 11 is discharged by switching operation of the switch CW, also when electric charges accumulated in the capacity element C of the second voltage generation circuit 12 are charged, the charges are supplied to the capacity element C of the first voltage generation circuit 11.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an internal power supply generating circuit for generating a new power supply voltage based on an external power supply supplied from outside in a semiconductor device.

2. Description of the Related Art In recent years, semiconductor devices have been increasingly operated at higher speeds and lower power consumption. Therefore, the semiconductor device requires a voltage to increase the operating speed. This voltage is generated by the internal power generation circuit based on the power supply voltage. On the other hand, in order to reduce the power consumption of the semiconductor device, it is necessary to reduce the power consumption of the internal power supply generation circuit.

[0003]

2. Description of the Related Art FIG. 7 shows first and second internal power generation circuits 21, 22 mounted on a conventional semiconductor device.
The first internal power supply generation circuit 21 is a P-channel MOS
Transistor (hereinafter referred to as PMOS transistor) T
r1, N-channel MOS transistor (hereinafter, NMOS
It comprises a transistor Tr2, a capacitance element (hereinafter simply referred to as a capacitance) C1, and two diodes D1 and D2. Both transistors Tr1 and Tr2 constitute an inverter circuit 21a as a switch circuit. The input terminal of the inverter circuit 21a, that is, both transistors Tr1, T
The same control signal φA is input to each gate of r2.
The output terminal of the inverter circuit 21a, that is, the node N1 of the drains of the transistors Tr1 and Tr2 is connected to one end of the capacitor C1. The power supply terminal of the inverter circuit 21a, that is, the source of the transistor Tr1, receives the power supply VCC.
The ground GND is supplied as power to the transistor Tr2.

The other end of the capacitor C1, that is, the node N2
Is connected to the cathode of the diode D1 and the anode of the diode D2. The power supply VCC is supplied to the anode of the diode D1, and the first boosted power supply VPP1 is output from the cathode of the diode D2.

On the other hand, the second internal power supply generation circuit 22
PMOS transistor Tr3, NMOS transistor Tr
4. A capacitive element (hereinafter simply referred to as a capacitance) C2 and two diodes D3 and D4. The second internal power generation circuit 22 has the same configuration as the first internal power generation circuit 21 described above. Note that both transistors Tr3, T
A control signal φB is input to each gate of r4. Then, the second boosted power supply VPP is supplied from the cathode of the diode D4.
2 is output.

When an H-level control signal φA is output,
The output terminal of the inverter circuit 21a in the first internal power supply generation circuit section 21, that is, the node N1 is connected to the ground GND
become. At this time, the potential at the node N2 becomes VCC-Vth, which is lower than the power supply VCC by a forward voltage drop Vth of the diode D1. Next, when the control signal φA changes from the H level to the L level, the potential of the node N1 changes from the ground GND level to the power supply VCC level. Therefore, the potential of the node N2 is
The voltage is boosted by CC, and the first boosted power supply V
It is output as PP1 (= 2VCC-2Vth). And
When the control signal φA changes from the L level to the H level again, the potential of the node N1 changes from the power supply VCC level to the ground GND level. Therefore, the potential at the node N2 becomes the potential VCC-Vth which is reduced by the power supply voltage VCC.

By repeating such an operation, each time the control signal φA goes low, the first boosted power supply VPP
1 (= 2VCC-2Vth) is output. On the other hand, the control signal φB is input to the second internal power supply generation circuit unit 22.
The control signal φB is an inverted signal of the control signal φA, and is at the L level when the control signal φA is at the H level, and at the H level when the control signal φA is at the L level. When the H-level control signal φB is output, the second internal power supply generation circuit 2
2, the output terminal of the inverter circuit 22a, that is, the node N3 becomes the ground GND. At this time, the node N4
Is the forward voltage drop Vth of the diode D3 from the power supply VCC.
It has a low potential VCC-Vth. Next, when the control signal φB changes from the H level to the L level, the potential of the node N3 changes from the ground GND level to the power supply VCC level. Therefore, the potential of the node N4 is boosted by the power supply VCC, and is output as the second boosted power supply VPP2 (= 2VCC-2Vth) via the diode D4. When the control signal φB changes from the L level to the H level again, the potential of the node N3 changes from the power supply VCC level to the ground GND level. Therefore, node N
4 is a potential VCC-Vth which is reduced by the power supply voltage VCC.

By repeating such an operation, each time the control signal φB goes low, the second boosted power supply VPP
2 (= 2VCC-2Vth) is output. Accordingly, the first and second boosted power supplies VPP1 and VPP2 are generated and output from the first and second internal power supply generating circuit sections 21 and 22 alternately by the control signals φA and φB.
The first and second boosted power supplies VPP1, which are alternately output,
VPP2 is supplied to each internal circuit of the semiconductor device as an operation power supply for increasing the operation speed.

[0009]

However, the first and second internal power supply generating circuits 21 and 22 are independent circuits, and the capacitors C1 and C2 perform charge and discharge operations, respectively. I have. Therefore, there is a problem in reducing power consumption due to the charging and discharging operations of the capacitors C1 and C2.

The present invention has been made to solve the above problems, and an object of the present invention is to provide an internal power supply generating circuit capable of reducing power consumption.

[0011]

Means for Solving the Problems The first aspect of the present invention is shown in FIG.
As shown in FIG.
2 is connected in series in the forward direction X.
Is supplied with a power supply voltage V1 to one end of
The output terminal of the capacitive element C is connected to the node N connecting the two, and the charge and discharge of the capacitive element C is performed by the operation of the switch circuit 4 that operates based on the control signal φ, so that the input terminal voltage of the capacitive element C Are changed to output voltages Vo1 and Vo2 different from the power supply voltage V1 at the other end of the rectifier circuit 3.
In the internal power generation circuit including the first and second voltage generation circuits 11 and 12 for outputting the electric charges, when discharging the electric charge accumulated in the capacitance element C of the first voltage generation circuit 11, Is supplied to the capacitive element C of the second voltage generating circuit 12, and when the electric charge stored in the capacitive element C of the second voltage generating circuit 12 is discharged, the discharging of the capacitive element C is performed. A switching element for supplying a charge to the capacitive element of the first voltage generating circuit;

According to a second aspect of the present invention, in the internal power generation circuit according to the first aspect, the first and second voltage generation circuits are higher than the power supply voltage based on charging and discharging of the charge of the capacitance element. A booster circuit for outputting a boosted voltage, wherein the switching element is connected between input terminals of capacitive elements of the first and second voltage generating circuits.

According to a third aspect of the present invention, in the internal power supply generating circuit according to the first aspect, the first and second voltage generating circuits are lower than the power supply voltage based on charging / discharging of charges of the capacitive element. A step-down circuit for outputting a step-down voltage, wherein the switching element is connected between input terminals of capacitive elements of the first and second voltage generating circuits.

According to a fourth aspect of the present invention, in the internal power supply generating circuit according to the first to third aspects, the first and second voltage generating circuits perform complementary operations based on the control signal.

(Operation) According to the first aspect of the present invention, when the electric charge accumulated in the capacitive element of the first voltage generating circuit is discharged by switching of the switching element, the discharged electric charge of the capacitive element becomes the second electric charge. When discharging the charge supplied to the capacitance element of the voltage generation circuit and accumulated in the capacitance element of the second voltage generation circuit, the discharge charge of the capacitance is supplied to the capacitance element of the first voltage generation circuit. Is done.

According to the second aspect of the present invention, in a booster circuit that outputs a boosted voltage higher than a power supply voltage based on charging / discharging of charges in a capacitive element, the switching element switches the capacitive element of the first voltage generating circuit. When discharging the stored charge, the discharge charge of the capacitor is supplied to the capacitance element of the second voltage generation circuit, and when discharging the charge stored in the capacitance element of the second voltage generation circuit. The discharge charge of the capacitance is supplied to the capacitance element of the first voltage generation circuit.

According to the third aspect of the present invention, in a step-down circuit that outputs a step-down voltage lower than the power supply voltage based on charging / discharging of the capacitor, the voltage is accumulated in the capacitor of the first voltage generating circuit by switching of the switching element. When discharging the charged electric charge, the discharged electric charge of the capacitor is supplied to the capacitive element of the second voltage generating circuit, and when discharging the electric charge stored in the capacitive element of the second voltage generating circuit, The discharge charge of the capacitance is supplied to the capacitance element of the first voltage generation circuit.

According to the fourth aspect of the present invention, the first and second voltage generating circuits perform complementary operations based on the control signal.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) A first embodiment of the present invention will be described below with reference to FIGS.

For convenience of explanation, the same components as those in FIG. 7 are denoted by the same reference numerals, and the description thereof is partially omitted. FIG. 2 shows the internal power supply generation circuit 10. The internal power supply generation circuit 10 includes first and second voltage generation circuits as first and second voltage generation circuits.
It comprises second internal power supply generation circuit units 11 and 12. The first and second internal power generation circuits 11 and 12 are respectively provided with the conventional first and second internal power generation circuits 21 and 21 described above.
The configuration is almost the same as that of FIG. And the first and second
The internal power generation circuits 11 and 12 perform complementary operations. The differences between the first and second internal power generation circuits 11 and 12 and the conventional internal power generation circuits 21 and 22 shown in FIG. 7 are as follows (1) to (4).
Is the point.

(1) Diodes D1 to D4 shown in FIG.
Are replaced by NMOS transistors Tr5 to Tr8, respectively, in the present embodiment. The drain of the transistor Tr5 is connected to the power supply VCC, and the source of the transistor Tr5, that is, the node N2, is connected to one terminal (output terminal) of the capacitor C1 and the drain of the transistor Tr6. The transistors Tr5 and Tr6 are diode-connected. That is, the respective gates are connected to the respective drains (high potential side), and in the present embodiment, the voltage corresponding to the forward voltage drop is Vthn. The first boosted power supply VPP1 is output from the source of the transistor Tr6.

On the other hand, the drain of the transistor Tr7 is connected to the power supply Vcc, and the source of the transistor Tr7, that is,
The node N4 is connected to one terminal (output terminal) of the capacitor C2 and the drain of the transistor Tr8. And
The transistors Tr7 and Tr8 are diode-connected. That is, the respective gates are connected to the respective drains (high potential side), and in the present embodiment, the voltage corresponding to the forward voltage drop is Vthn. The second boosted power supply VPP2 is output from the source of the transistor Tr8.

(2) The gates of the transistors Tr1 to Tr4 constituting the switch circuit are connected to first to fourth
Are input respectively. The transistors Tr1 and Tr2 and the transistors Tr3 and Tr4 are first to fourth transistors.
Perform a complementary operation based on the control signals φ1 to φ4. That is, the first and second internal power supply generation circuits 11 and 12 perform complementary operations based on the first to fourth control signals φ1 to φ4. Therefore, the internal power supply generation circuit 10
Is configured to alternately generate first and second boosted power supplies VPP1 and VPP2.

(3) The nodes N1 and N3 are connected via an NMOS transistor Tr9 as a switching element. The gate of the transistor Tr9 has
A later-described fifth control signal φ5 is input. The transistor Tr9 is connected to each of the capacitors C based on the fifth control signal φ5.
1 and C2 are exchanged. That is, the transistor T based on the fifth control signal φ5
r9 supplies the discharge charge of the capacitor C1 to the charge of the capacitor C2 and the discharge charge of the capacitor C2 to the charge of the capacitor C1 by the switching.

(4) The first to fifth control signals φ1 to φ
5 are generated by the signal generation circuit 20 and output at the timing shown in FIG. That is, the first control signal φ
The first and fourth control signals φ4 are complementary signals. When the first control signal φ1 is at H level, the fourth control signal φ4 is at L level, and when the first control signal φ1 is at L level, 4
Is at H level. Further, the second control signal φ2 and the third control signal φ3 are complementary signals. When the second control signal φ2 is at the H level, the third control signal φ3 is at the L level.
Level, and the third control signal φ3 is at the H level when the second control signal φ2 is at the L level.

The relationship between the first control signal φ1 and the second control signal φ2 is as follows. Second control signal φ2
Falls for a predetermined time T1 from the H level to the L level.
After the lapse of time, the first control signal φ1 falls from the H level to the L level, and the first control signal φ1 changes from the L level to the H level.
The second control signal φ2 rises from the L level to the H level after a lapse of a predetermined time T2 after rising to the level.

Therefore, the relationship between the third control signal φ3 and the fourth control signal φ4 is determined as follows. That is, the third
The fourth control signal φ4 rises from the L level to the H level after a lapse of a predetermined time T1 after the control signal φ3 rises from the L level to the H level, and the fourth control signal φ4 falls from the H level to the L level. After a lapse of a predetermined time T2, the third control signal φ3 later falls from the H level to the L level.

On the other hand, as shown in FIG. 3, the fifth control signal φ5 is changed to the fifth control signal φ5 after a lapse of a predetermined time T3 after the second control signal φ2 falls from the H level to the L level.
5 rises from the L level to the H level, and the fifth control signal φ5 falls from the H level to the L level first before the time T4 before the time when the first control signal φ1 falls from the H level to the L level. Further, the fifth control signal φ5 rises from the L level to the H level after a lapse of a predetermined time T3 after the first control signal φ1 rises from the L level to the H level, and the second control signal φ5 Signal φ2 is L
The fifth control signal φ5 falls from the H level to the L level before the time T4 before the time to rise from the level to the H level.

Next, the operation of the internal power supply generation circuit 10 configured as described above will be described with reference to the timing chart of FIG. Now, the first and second control signals φ1, φ2
Is H level and the third to fifth control signals φ3 to φ5 are L level, the transistors Tr2 and Tr3 are turned on and the transistors Tr1, Tr4 and Tr9 are turned off. Therefore, node N1
Is at the ground GND level, and the node N3 is at the power supply VCC.
Level. The node N2 has a voltage obtained by subtracting the voltage drop Vthn of the diode-connected transistor Tr5 from the power supply VCC. The node N4 has a voltage obtained by adding the voltage drop Vthn of the diode-connected transistor Tr8 from the second boosted power supply VPP2.

In this state, when the second control signal φ2 changes from H level to L level and the third control signal φ3 changes from L level to H level, the transistors Tr2 and Tr3 are turned off. That is, the five transistors Tr1 to Tr4, T
r9 is turned off. When the time T3 elapses, the fifth control signal φ5 becomes H level, the transistor Tr9 is turned on, and the charge of the capacitor C2 is charged to the capacitor C1 via the transistor Tr9. As a result, the potential of the node N1 rises, and the potential of the node N3 falls and eventually becomes the same potential as the node N1. This rise in the potential of the node N1
2 and the potential of the node N2 becomes a potential obtained by adding the rise of the node N1. On the other hand, the fall of the potential of the node N3 leads to the fall of the node N4, and the node N4
Becomes a potential obtained by subtracting the drop of the node N3. Then, when the fifth control signal φ5 becomes L level, the transistor Tr9 is turned off, and the transfer of the charge from the capacitor C2 to the capacitor C1 ends.

Subsequently, when the time T4 elapses, the first control signal φ1 changes from H level to L level, the fourth control signal φ4 changes from L level to H level, and the transistor Tr
1, Tr4 is turned on.

Therefore, the node N1 becomes the power supply VCC, and the node N3 becomes the ground GND level. At this time, the potential of the node N2 is boosted to the potential of 2VCC-Vthn because the potential of the node N1 is at the power supply VCC level. That is, the first boosted power supply VPP1 is boosted to 2VCC-2Vthn.

Next, when the first control signal φ1 changes from L level to H level and the fourth control signal φ4 changes from H level to L level, the transistors Tr1 and Tr4 are turned off. That is, the five transistors Tr1 to Tr4 and Tr9 are turned off. When the time T3 has elapsed, the fifth control signal φ5 goes high, turning on the transistor Tr9, and the charge of the capacitor C1 is transferred to the capacitor C2 via the transistor Tr9.
Is charged. As a result, the potential of the node N3 rises,
The potential of the node N1 falls, and the potential of the node N3 becomes the same. This rise in the potential of the node N3 leads to a rise in the potential of the node N4, and the potential of the node N4 becomes a potential obtained by adding the rise of the node N3. On the other hand, a drop in the potential of the node N1 leads to a drop in the node N2, and the potential of the node N2 becomes a potential obtained by subtracting the drop of the node N1. And the fifth
Becomes low, the transistor Tr9
Is turned off, and the transfer of the charge from the capacitor C1 to the capacitor C2 ends.

Subsequently, when the time T4 has elapsed, the second control signal φ2 changes from L level to H level, the third control signal φ3 changes from H level to L level, and the transistor Tr
2, Tr3 is turned on.

Therefore, the node N3 becomes the power supply VCC, and the node N1 becomes the ground GND level. At this time, the potential of the node N4 is boosted to the potential of 2VCC-Vthn because the potential of the node N1 is at the power supply VCC level. That is, the second boosted power supply VPP2 is boosted to 2VCC-2Vthn.

Then, the first to fifth control signals φ1 to φ5
, The internal power supply generation circuit 10 repeats the above operation. That is, the first and second internal power supply generation circuits 11 and 12 apply the alternately boosted voltage (2Vcc-2V
thn) of the first and second boosted power supplies VPP1 and VPP2.

As described above, according to the present embodiment,
It has the following features. (1) The charge for charging the capacitor C1 of the first internal power supply generation circuit unit 11 and raising the potential of the node N1 is:
The discharge charge of the capacitor C2 of the second internal power supply generation circuit unit 12 is used. Conversely, the capacitor C2 is charged and the node N2
Of the capacitor C1 is used as the charge for raising the potential of the capacitor C1. Therefore, it is possible to reduce the charge required for charging the capacitors C1 and C2 again, thereby reducing current consumption.

(2) The internal power supply generation circuit 10 is an NMOS
The transistor Tr9 is connected to the nodes N1 and N2, and is controlled by control signals φ1 to φ5. Therefore, the circuit can be configured relatively easily.

(3) First and second internal power supply generation circuits 1
1 and 12 perform complementary operations based on the control signals φ1 to φ4, so that charge can be reliably exchanged between the capacitors C1 and C2.

(Second Embodiment) Hereinafter, a second embodiment of the present invention will be described with reference to FIG. still,
For convenience of description, the same components as those in FIG. 2 are denoted by the same reference numerals, and description thereof is partially omitted.

FIG. 4 shows the internal power supply generation circuit 10a.
The difference from the internal power supply generation circuit 10 shown in FIG. 2 is the following (1) and (2). (1) The diode-connected NMOS transistors Tr6 and Tr8 shown in FIG. 2 are replaced by PMOS transistors Tr10 and Tr11 in the present embodiment. Further, the control signals φ6 and φ7 generated by the signal generating circuit 20a are input to the gates of the transistors Tr10 and Tr11, respectively, and the transistors Tr10 and Tr11 are controlled to be turned on only when the potentials of the nodes N2 and N4 rise. The control signals φ6, φ
7 oscillates between the ground GND level and the first and second boosted power supply levels VPP1 and VPP2. Therefore, the on-resistance between the source and the drain of both transistors Tr10 and Tr11 is small, and the potential difference can be almost eliminated. As a result, the first and second boosted power supplies VPP1 and VPP2 are generated more efficiently.

(2) The diode-connected NMOS
The gate of the transistor Tr5 is connected to the node N4. The transistor Tr5 is on when the potential of the node N4 is higher than the potential of the node N2 by the threshold voltage Vthn. Therefore, when the potential of the node N4 rises, that is, when the second boosted power supply VPP2 starts to be generated, the NMOS transistor Tr5 turns on and starts charging the capacitor C1. Conversely, the transistor Tr5 is connected to the node N
When the potential of No. 2 rises, that is, when the first boosted power supply VPP1 starts to be generated, it is turned off. That is, the transistor Tr5 prevents backflow to the power supply VCC due to an increase in the potential of the node N2.

The gate of the diode-connected NMOS transistor Tr7 is connected to the node N2. The transistor Tr7 is on when the potential of the node N2 is higher than the potential of the node N4 by the threshold voltage Vthn. Therefore, when the potential of the node N2 rises, that is, when the first boosted power supply VPP1 starts to be generated, the NMOS transistor Tr7 turns on and starts charging the capacitor C2. Conversely, the transistor Tr7 is connected to the node N4
Is turned off, that is, when the second boosted power supply VPP2 starts to be generated. That is, the transistor Tr7 prevents backflow to the power supply VCC due to the rise in the potential of the node N4.

The internal power supply generating circuit 1 configured as described above
0a are the first to fifth control signals φ1 to φ5 which transit at the timing shown in FIG. 3 as in the first embodiment.
Is controlled by Based on the control signals φ1 to φ5, the nodes N1 and N3 are charged / discharged in the voltage range between the power supply VCC level and the ground GND level based on the switching operation of the transistors Tr1 to Tr4 and Tr9 by the control signals φ1 to φ5. The operation is performed.

Therefore, the first and second boosted power supplies VPP obtained by boosting the power supply VCC by the same operation as in the first embodiment based on the alternating voltage changes of the nodes N1 and N3.
1 and VPP2 are generated alternately. The first and second boosted power supplies VPP1 and VPP2 are theoretically boosted to 2 VCC because the potential difference between the source and the drain of each of the turned-on transistors Tr5, Tr7, Tr10 and Tr11 is small.

As described above, according to the present embodiment,
The following features are provided in addition to the features of the second embodiment. (1) The gates of the NMOS transistors Tr5 and Tr7 are connected to the nodes N4 and N2, respectively, and the gates of the PMOS transistors Tr10 and Tr11 have amplitudes between the ground GND level and the first and second boosted power supply levels VPP1 and VPP2. By inputting control signals φ6 and φ7 respectively, the potential difference between the source and drain of each of the transistors Tr5, Tr7, Tr10 and Tr11 can be reduced. As a result, the first and second boosted power supplies VPP1 and VPP2 can be generated more efficiently.

(Third Embodiment) Hereinafter, a third embodiment of the present invention will be described with reference to FIG. still,
For convenience of description, the same components as those in FIG. 4 are denoted by the same reference numerals, and description thereof is partially omitted.

FIG. 5 shows the internal power supply generation circuit 10b.
The difference from the internal power supply generation circuit 10a shown in FIG.
These are points (1) and (2) shown below. (1) The gate of the PMOS transistor Tr10 is connected to the node N4. The transistor Tr10 is on when the potential of the node N4 is lower than the potential of the node N2 by the threshold voltage Vthp. Therefore, when the potential of the node N2 rises, that is, the first boosted power supply VPP1
Starts to be generated, the PMOS transistor Tr10 turns on and the boosted power supply VPP1 is output.

The gate of the PMOS transistor Tr11 is connected to the node N2. The transistor Tr1
1 is on when the potential of the node N2 is lower than the potential of the node N4 by the threshold voltage Vthp. Therefore, when the potential of the node N4 rises, that is, when the second boosted power supply VPP2 starts to be generated, the PMOS transistor Tr11 turns on and the boosted power supply VPP2 is output.

(2) The NMOS transistors Tr5 and T
The control signal φ8, φ9 generated by the signal generation circuit 20b is input to the gate of r7, and the node N2,
It is controlled to turn off only when the potential of N4 rises. The control signals φ8 and φ9 oscillate between a level lower than the power supply VCC level and a level higher than the voltage VCC + Vthn level obtained by adding the threshold voltage Vthn of each of the transistors Tr5 and Tr7 to the power supply VCC level. Therefore, both transistors Tr5 and Tr7
Between the gate and the drain of the transistor Tr5,
The ON resistance between the source and the drain of Tr7 is small, and the potential difference can be almost eliminated. As a result, the first and second boosted power supplies VPP1 and VPP2 are generated more efficiently.

The internal power supply generation circuit 1 configured as described above
0b are the first to fifth control signals φ1 to φ5 which transit at the timing shown in FIG. 3, as in the first embodiment.
Is controlled by Based on the control signals φ1 to φ5, the nodes N1 and N3 are charged / discharged in the voltage range between the power supply VCC level and the ground GND level based on the switching operation of the transistors Tr1 to Tr4 and Tr9 by the control signals φ1 to φ5. The operation is performed.

Therefore, the first and second boosted power supplies VPP1 and VPP1, which are obtained by boosting the power supply VCC by the same operation as in the above-described embodiment based on the alternating voltage changes of the nodes N1 and N3.
VPP2 is generated alternately. The first and second boosted power supplies VPP1 and VPP2 are turned on by the respective transistors Tr5, Tr5,
Since the potential difference between the source and drain of Tr7, Tr10 and Tr11 is small, the voltage is theoretically boosted to 2Vcc.

As described above, according to the present embodiment,
The following features are provided in addition to the features of the second embodiment. (1) The gates of the PMOS transistors Tr10 and Tr11 are connected to the nodes N4 and N2, respectively. The gates of the NMOS transistors Tr5 and Tr7 are connected to the power supply VCC level from the power supply VCC level to the threshold voltage of the transistors Tr5 and Tr7. By inputting control signals .phi.8 and .phi.9, each of which has an amplitude between the voltage Vcc + Vthn and the voltage Vthn added, the potential difference between the source and drain of each of the transistors Tr5, Tr7, Tr10 and Tr11 can be reduced.
As a result, the first and second boosted power supplies VPP1 and VPP2 can be generated more efficiently.

(2) PMOS transistors Tr10, Tr1
1 can reliably output the first and second boosted power supplies VPP1 by connecting the respective gates to the nodes N4 and N2 and operating them based on the potentials of the nodes N4 and N2.

(Fourth Embodiment) Hereinafter, a fourth embodiment of the present invention will be described with reference to FIG. still,
For convenience of description, the same components as those in FIG. 2 are denoted by the same reference numerals, and description thereof is partially omitted.

FIG. 6 shows the internal power supply generation circuit 10c.
The difference from the internal power supply generation circuit 10 shown in FIG. 2 is as follows. Diode-connected NM shown in FIG.
The OS transistors Tr5 to Tr8 are replaced by diodes D5 to D8 in the present embodiment. Of course, the MOS transistors may be diode-connected as in the first to third embodiments. The anode of the diode D5 and the cathode of the diode D6 are connected to the node N2. The ground GND is supplied to the cathode of the diode D5, and the first step-down power supply VBB1 is output from the anode of the diode D6. On the other hand, the node N
4 includes an anode of a diode D7 and a diode D8.
Are connected. The ground GND is supplied to the cathode of the diode D7, and the second step-down power supply VBB2 is output from the anode of the diode D8.

The internal power supply generating circuit 1 configured as described above
0c are the first to fifth control signals φ1 to φ5 which transit at the timing shown in FIG. 3, as in the first embodiment.
Is controlled by Based on the control signals φ1 to φ5, the nodes N1 and N3 are charged / discharged in a voltage range between the power supply VCC level and the ground GND level based on the switching operation of the transistors Tr1 to Tr4 and Tr9 by the control signals φ1 to φ5. The operation is performed.

That is, when the node N1 is at the power supply VCC level, the node N2 is switched from the ground GND to the diode D5.
Is discharged to the potential GND + Vth higher by the forward voltage drop Vth. From this state, the node N1 is connected to the ground GND.
When the level becomes the level, the potential of the node N2 is reduced by the power supply voltage VCC, and the reduced voltage absorbs the electric charge from the anode of the diode D6 to the node N2 through the diode D6, thereby forming the first step-down power supply VBB1 (= -VCC + 2Vth). Is output. When the potential of the node N1 becomes the power supply VCC level again, the potential of the node N2 becomes the potential GND + Vth which is boosted by the power supply voltage VCC. By repeating such an operation, the first step-down power supply VBB1 (= -VCC + 2Vth) is output each time the node N1 goes to the ground GND level, that is, the control signal φ2 goes to the H level.

On the other hand, the potential of the node N3 changes between the power supply VCC level and the ground GND level similarly to the node N1, so that every time the node N3 goes to the ground GND level, that is, the control signal φ4 goes to the H level, the second potential changes. Step-down power supply V
BB2 (= −VCC + 2Vth) is output.

Therefore, the first and second step-down power supplies VBB1 and VBB2, which are stepped down to the ground GND level or lower, are generated alternately based on the alternating voltage changes of the nodes N1 and N3. As described above, according to the present embodiment, the fourth
It has the following features in addition to the features of the embodiment.

(1) First and second step-down power supplies VBB1, VBB
Similarly, the internal power supply generation circuit 10c for generating
The charge for charging the capacitor C1 of the internal power generation circuit unit 11 and raising the potential of the node N1 utilizes the discharge charge of the capacitor C2 of the second internal power generation circuit unit 12. Conversely, the charge for charging the capacitor C2 and raising the potential of the node N2 utilizes the discharge charge of the capacitor C1. Therefore, it is possible to reduce the charge required for charging the capacitors C1 and C2 again, thereby reducing current consumption.

The present invention may be embodied in the following modes in addition to the above embodiment. (1) In each of the above embodiments, the internal power supply generation circuit 10,
10a, 10b and 10c are controlled by the first to fifth control signals φ1 to φ5 which transition as shown in FIG. 3, but when discharging the capacitor C1, the discharge charges of the capacitor C1 are transferred to the capacitor C2. When discharging the capacitor C2 and discharging the capacitor C2, the discharge charge of the capacitor C2 is supplied to the capacitor C1. For example, FIG.
May be set to zero.

(2) In each of the above embodiments, the node N
NMOS transistor Tr9 is connected between 1 and N3,
The invention is not limited to this, and other switching elements may be used. For example, switching elements such as PMOS transistors and bipolar transistors may be used.

(3) In the first to third embodiments,
Each of the transistors Tr5 to Tr8, Tr10, Tr11 is diode-connected to allow a current to flow only from the power supply VCC in the direction of the first and second boosted power supplies VPP1, VPP2. However, the current flows only in the same direction. The configuration is not limited to these configurations.

(4) In the fourth embodiment, the anode of the diode D5 and the cathode of the diode D6 are connected to the node N2, and the anode of the diode D7 and the cathode of the diode D8 are connected to the node N4. Is not limited to a diode, and a diode-connected transistor or the like may be used.

[0066]

As described in detail above, according to the present invention,
An internal power generation circuit capable of reducing power consumption can be provided.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a circuit diagram of an internal power supply generation circuit according to the first embodiment.

FIG. 3 is a timing chart illustrating an operation example of an internal power supply generation circuit.

FIG. 4 is a circuit diagram of an internal power supply generation circuit according to a second embodiment.

FIG. 5 is a circuit diagram of an internal power supply generation circuit according to a third embodiment.

FIG. 6 is a circuit diagram of an internal power supply generation circuit according to a fourth embodiment.

FIG. 7 is a circuit diagram of a conventional internal power supply generation circuit.

[Explanation of symbols]

 1, 2 rectifying element 3 rectifying circuit 4 switching circuit 11 first voltage generating circuit 12 second voltage generating circuit C capacitive element SW switching element V1, V2 power supply voltage Vo1, Vo2 output voltage X forward direction φ control signal

Claims (4)

[Claims] 1. A power supply voltage is supplied to one end of a rectifier circuit having two rectifiers connected in series in a forward direction, and an output terminal of a capacitor is connected to a node connecting the two rectifiers. And an output voltage different from the power supply voltage at the other end of the rectifier circuit by changing the input terminal voltage of the capacitor by charging and discharging the capacitor by the operation of the switch circuit that operates based on the control signal. Output the first
And an internal power generation circuit including a second voltage generation circuit, wherein when discharging the charge accumulated in the capacitance element of the first voltage generation circuit, the discharge charge of the capacitance element is discharged to the second voltage generation circuit. And discharging the electric charge accumulated in the capacitance element of the second voltage generation circuit,
An internal power supply generation circuit including a switching element for supplying discharge charge of the capacitance element to the capacitance element of the first voltage generation circuit. 2. The internal power generation circuit according to claim 1, wherein the first and second voltage generation circuits output a boosted voltage higher than the power supply voltage based on charging / discharging of the charge of the capacitance element. A booster circuit, wherein the switching element is connected between input terminals of capacitive elements of the first and second voltage generation circuits. 3. The internal power generation circuit according to claim 1, wherein the first and second voltage generation circuits output a step-down voltage lower than the power supply voltage based on charging / discharging of charges of the capacitance element. A step-down circuit, wherein the switching element is connected between input terminals of capacitance elements of the first and second voltage generation circuits. 4. The internal power supply generation circuit according to claim 1, wherein said first and second voltage generation circuits perform complementary operations based on said control signal.