JPH10271151A - Data transmission equipment and contact monitor system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data transfer equipment by which a 1 : multi interactive communication system between a master set and slave sets is easily built up at a low cost based on both the hardware and the software and to provide a contact monitor system. SOLUTION: A serial data transfer equipment is provided with a transmission buffer 1, a register 2, a loop switch A3, a loop switch B4, a reception buffer 5, a control section 6, a transmission output (TXD) pin 7 and a reception input (RXD) pin 8 and the reception input (RXD) pin 8, the register 2 and the transmission output (TXD) pin 7 are placed on a loop. Then the control section 6 controls the loop switches A3, B4, the transmission buffer 1 and the reception buffer 5 to select the reception operation, the transmission operation or the loop operation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer device and a contact monitoring system, and more particularly, to a data transfer device and a contact monitoring system having a function of performing bit-serial data transfer by an asynchronous system.

[0002]

2. Description of the Related Art Among current microcomputer application technologies, serial data transfer as a connection method between computer systems is one of important interface technologies.

[0003] Regarding the serial data transfer method, from the viewpoint of the characteristics of the IC, the UART (universal asynch
ronous receiver transmitter) and USRT (universal
There is an IC for LAN such as an Ethernet recently. This UA
RT and USRT are suitable for one-to-one connection between computer systems, but are not suitable for connection between many systems. In addition, LAN ICs such as an Ethernet and an arcnet are manufactured for intercommunication of a large number of systems, and thus the hardware becomes expensive and the software becomes complicated.

[0004] By the way, considering a system currently required, for example, a large number of contact signals are monitored, and the number of times of contact activation is counted or displayed according to the entrance of the contact signal. There are many computer systems for turning on / off a relay or a solenoid for industrial use or consumer use.

[0005] Many of such systems for monitoring a large number of contact signals include a large number of slave units mainly for monitoring a large number of contacts and contacts at remote locations in order to construct an efficient system. A master device whose main purpose is to centrally process the contact data is connected by a serial or parallel communication line, and exchanges data and commands through the communication line.

[0006] There are many other one-to-many interactive communication systems for connecting the above-mentioned master unit and many slave units.

[0007]

In such a one-to-many interactive communication system of a master unit and a slave unit, the speed of the communication line between the master unit and the slave unit depends on the responsiveness of the system. At the same time, it is important to make a good connection between the master unit and many slave units.

However, as described above, the UART and the USRT are one-on-one interactive types, and when a large number of connections are made, the burden on hardware and software increases. In addition, LAN-
When an IC is used, all the master units and the slave units can communicate with each other, but the communication between the slave units is overspecified, and the hardware and software to be controlled are complicated and expensive.

The present invention provides a data transfer device and a contact monitoring system capable of easily and inexpensively constructing a one-to-many interactive communication system of a master unit and a slave unit using both hardware and software. The purpose is to:

[0010]

According to a first aspect of the present invention, there is provided a data transfer apparatus for transferring serial data, wherein the data transfer apparatus has a loop path for looping reception data as transmission data to a transmission side; A data holding unit that is installed and temporarily stores transmission / reception data, a switch unit connected to the data holding unit, and switches the switch unit to take in data from the data holding unit or send data to the data holding unit. Or control means for controlling the received data to be looped to the transmitting side.

According to a second aspect of the present invention, there is provided a data transfer apparatus including a data transfer means for performing bit-serial data transfer by an asynchronous system, wherein the data transfer means includes an identification code for identifying itself. (ID number), processing means for reading the identification code and processing only the corresponding data, a loop path that can connect a plurality of terminals in a loop to form a loop system, and a loop path on the loop path. A data holding unit that is installed and temporarily stores transmission / reception data, a switch unit connected to the data holding unit, and switches the switch unit to take in data of the data holding unit, or send data to the data holding unit or And control means for controlling reception data to be looped to the transmission side.

According to a third aspect of the present invention, the data holding means may be a transmission / reception shift register capable of taking in serial data as parallel data and outputting parallel data as serial data.

According to a fourth aspect of the present invention, the data transfer apparatus further includes a register capable of outputting the input data at the minimum clock timing, and loops the received data to the transmission side via the register during the loop. Good.

According to a fifth aspect of the present invention, the data transfer apparatus further includes a plurality of transmission buffers for temporarily storing transmission data, and a plurality of reception buffers for temporarily storing reception data. Among the buffers, one transmission buffer enables the transmission data to be written by another transmission buffer while the transmission operation is performed, and among the plurality of reception buffers, one reception buffer reads by another reception buffer while the reception operation is performed. It may be made possible.

According to a sixth aspect of the present invention, in the data transfer device, the switch means may include at least one switch provided on a loop path.

According to a seventh aspect of the present invention, in the data transfer apparatus, the switch means is provided on a loop path and temporarily stores transmission / reception data, and the first transmission means is provided on an input side of the transmission / reception shift register. And a second loop switch provided on the output side of the transmission / reception shift register. The first loop switch and the second loop switch are switched to take in data on the loop path or to place the data on the loop path. It may transmit data.

In the data transfer device according to the present invention, the switch means is further provided on a loop path and switches between a loop dedicated register capable of outputting input data at a minimum clock timing and a loop dedicated register. And a loop switch.
In which the data is output to the transmission side via the loop dedicated register.

According to a ninth aspect of the present invention, there is provided a data transfer device comprising a contact input port for inputting a contact signal, wherein the contact input port calculates an effective number according to a pulse width of a contact longer than a predetermined time width. It may include a calculating means and a contact count buffer for storing the number of valid times calculated by the effective number calculating means.

According to a tenth aspect of the present invention, in the data transfer apparatus, a master unit and one or more slave units are connected by using a loop line, the master unit is connected to a master, and contact data of the master unit is controlled by the master. In a contact monitoring system to be managed, a master unit and a slave unit are configured by the data transfer device according to any one of claims 1 to 9.

The contact monitoring system according to claim 11 is
The loop line may be an optical cable including an optical fiber and an optical connector.

[0021] The contact monitoring system according to claim 12 is
The master unit receives data and a command from the master, and the master unit performs processing according to the command from the master.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A data transfer device and a contact monitoring system according to the present invention can be applied to a serial data transfer device for transferring serial data.

First Embodiment FIG. 1 is a block diagram showing a basic configuration of a serial data transfer device according to a first embodiment of the present invention.

In FIG. 1, the serial data transfer device includes a transmission buffer 1, a register 2 (data holding means), a loop switch A3 (switch means), a loop switch B4 (switch means), a reception buffer 5, and a control unit 6. (Control means), a transmission output (TXD) pin 7 and a reception input (RXD) pin 8.

The path from the reception input (RXD) pin 8 to the transmission output (TXD) pin 7 via the loop switch A3, the register 2, and the loop switch B4 constitutes a loop path for constructing a loop system as a whole. .

The control unit 6 is set by a CPU or the like, and controls the transmission buffer 1, the loop switch A3, the loop switch B4, and the reception buffer 5 in response to a reception operation, a transmission operation, a loop operation, and the like.

As described above, the present serial data transfer device has a configuration in which the reception input (RXD) pin 8, the register 2, and the transmission output (TXD) pin 7 are arranged on a loop.

Hereinafter, the operation of the serial data transfer device configured as described above will be described.

When the serial data transfer apparatus receives a signal, the loop switch A3 is turned on and the loop switch B4 is turned off in advance. In this state, the reception input (RX
D) The serial data input to the pin 8 with the pulse width specified in advance is input to the register 2 through the loop switch A3. The data input to the register 2 is shifted in the register 2 and is temporarily stored in the reception buffer 5 when a predetermined number of bits are satisfied. As a result, the serial data is converted into parallel data. The control unit 6 controls the parallel data to be extracted from the reception buffer 5.

When the serial data transfer apparatus transmits data, the loop switch A3 is turned off and the loop switch B4 is turned on in advance. In this state, the control unit 6
Controls to write data to be transferred through the data bus to the transmission buffer 1 in a parallel format. The data written in the transmission buffer 1 is loaded into the register 2, passes through the loop switch B4 with a pulse width specified in advance as a serial format, and transmits the transmission output (TXD).
Output from pin 7.

On the other hand, this serial data transfer device is connected on a loop line, and neither the transmission operation nor the reception operation is performed, and the serial data input from the reception input (RXD) pin 8 is directly transmitted to the transmission output (TXD) pin 7. , The loop switch A3 and the loop switch B4 are turned on in advance. During this loop operation, the register 2 operates as a shift register for passing serial data, and also corrects the waveform of the pulse distortion of the data transmitted to the reception input (RXD) pin 8.

Further, for example, when a plurality of the present apparatuses are connected on a loop line to form a loop, and when data is transmitted from one apparatus to another apparatus, none of the apparatuses receives the data due to an erroneous operation or the like. In this case, data will be permanently looped on the loop line. In such a case, the permanent loop can be prevented by turning off the loop switches A3 and B4.

As described above, the serial data transfer device according to the first embodiment includes the transmission buffer 1, the register 2, the loop switch A3, the loop switch B4, the reception buffer 5, the control unit 6, the transmission output ( TXD) Pin 7
And a reception input (RXD) pin 8.
D) The pin 8, the register 2, and the transmission output (TXD) pin 7 are arranged on a loop. The control unit 6 controls the loop switch A3, the loop switch B4, the transmission buffer 1, and the reception buffer 5. Receive operation by control,
A transmission operation or a loop operation can be selectively used. That is, the present serial data transfer device is a device that transmits and receives serial data, and also has a function as a data transfer device that performs a loop operation of shaping the waveform of input serial data and outputting the waveform as it is.

Therefore, if a plurality of the present serial data transfer devices are connected on a loop line, a highly flexible loop system can be constructed with a very simple configuration.

The effect will be described in comparison with the conventional example.

FIG. 16 shows a conventional UART (universal asyn).
FIG. 2 is a block diagram illustrating a configuration of a (chronous receiver transmitter). As shown in FIG. 16, a UART, which is a conventional serial transfer device, has a transmission UART and a reception UART.
It has an ART and performs one-to-one transmission and reception. Therefore, in order to construct a system in which a plurality of slave units are connected to the master unit, devices having transmission and reception UARTs must be connected to each other. In addition, a hub (HUB) is required for this connection.

On the other hand, in the present serial data transfer device, since the receiving input (RXD) pin 8, the register 2, and the transmitting output (TXD) pin 7 have a loop configuration arranged on a loop, , A receiving operation, a transmitting operation, or a loop operation can be selected. Even when a plurality of connections are made on a loop line, the input / output terminals need only be connected. Therefore, a loop system having a high degree of freedom can be constructed with a simple configuration.

By the way, in the serial data transfer apparatus, in order to control operation such as reception, transmission or a loop, and to further improve the efficiency of a loop line, additional functions are provided in the following points (1) to (4). It may be provided.

(1) To automate the determination of reception, the ID
Add a transmission mode detector to automate the function and the number of received bytes.

(2) To facilitate CPU control when the transfer rate is increased, a transmission buffer and a reception buffer are provided with appropriate capacities.

(3) An interrupt signal is generated when transmission is completed or reception is completed, so that the CPU can quickly detect each state.

(4) DMAC (direct memory) used to shorten the transfer time to the transmission buffer and the reception buffer
y access controller).

The second embodiment described below is an example in which the above functions are added to increase the line efficiency, and each control is automated to enhance the control effect by the CPU. In the second embodiment, the serial data transfer device and an LSI having various functions are integrated into one chip, and are used as a device for connecting a data line between a master unit and a slave unit.

Second Embodiment A data transfer device and a contact monitoring system according to the present invention
The present invention can be applied to a contact monitoring device including a plurality of slave units that monitor a large number of contact points that are distant from each other and a master unit that centrally processes contact data from the plurality of slave units.

FIG. 2 is a diagram showing a configuration of a data transfer device and a contact monitoring system according to a second embodiment of the present invention. This embodiment is a configuration example in which the data transfer device is incorporated in a one-chip microcomputer. .

In FIG. 2, reference numeral 10 denotes a one-chip microcomputer (hereinafter, referred to as a one-chip microcomputer).
The one-chip microcomputer 10 includes an 8-bit CPU core 11 (processor), a dedicated high-speed UART 12 (data transfer means), a DMAC (direct memory access controller) 1
3, CTC (counter timer circuit) 14, SIO (s
erial I / O) 15, PIO (peripheral I / O) 16, contact input port 17, data bus 18, address bus 19
Consists of 20 is a control signal, 21
Is a ROM control signal, 22 is a RAM control signal, 23 is an eraseable memory control signal, 2
4 is a display control signal.

The ROM 25, the main RAM 26, the erasable memory 27, and the display 28, which are controlled by the control signals, are provided outside the one-chip microcomputer 10.
Is connected. Also, the PI inside the one-chip microcomputer 10
O16 is connected to the driver circuit 29, and drives the relay and the solenoid 30 by the driver circuit 29.

The 8-bit CPU core 11 uses, for example, a Z80 CPU as an 8-bit microprocessor. The Z80 CPU core 11 is a general 8-bit microprocessor.
AC13, CTC14, SIO15, and PIO16 are provided, and a dedicated high-speed UART 12 and a contact input port 17 are provided as peripheral LSIs unique to the present embodiment.

The Z80 CPU core 11 collects data of several tens of contacts, sends the count data to the master unit using the dedicated high-speed UART 12, or receives a command from the master unit and outputs it. It is most suitable for the CPU of the machine, and the software can be easily created. When the parent device is relatively small, it can be used as a main CPU, and when the parent device is large, it can be used as a sub CPU.

The dedicated high-speed UART 12 is a serial interface originally developed by adding a new function described later to the serial data transfer device of the first embodiment. If this dedicated high-speed UART 12 is used by attaching an optical connector such as a toslink and an optical cable, a one-to-many interactive communication line between the master unit and a number of slave units can be realized. The function of the dedicated high-speed UART 12 will be described later in detail with reference to FIG.

The DMAC 13 performs DMA control for directly exchanging data between an I / O device and a memory via a bus without going through a CPU. Here, mainly when the data capacity is large, the main R
It is used for high-speed transfer from the AM 26 to the transmission buffer inside the dedicated high-speed UART 12 or from the reception buffer inside the dedicated high-speed UART 12 to the main RAM 26. Since high-speed and large-capacity data transfer can be performed without the overhead of the CPU, it helps to speed up the system.

The CTC (counter / timer controller) 14 manages the time of the system accurately by the internal hardware logic, and operates the dedicated high-speed UART 12
The operation of the reception completion interrupt and the transmission completion interrupt is controlled to control the time smoothing of the system.

The above SIO (serial in / out) 1
Reference numeral 5 denotes an I / O controller for performing serial in / out, which is used as a general RS232C in an auxiliary manner. This is effective when a small terminal having an RS232C interface near the child device is connected and data of the small terminal is transmitted to the parent device through the dedicated high-speed UART 12.

The PIO (Preferred In / Out) 16 is a general-purpose programmable parallel interface I / O controller, and is an LSI that can be used for input and output bit by bit depending on the contents of a software set. It is useful when used as a simple general-purpose input or when controlling the output of a solenoid or relay through a driver circuit.

The contact input port 17 is a contact input port with a built-in noise cut type counter memory, and has a serial buffer for automatically storing only the effective number of times corresponding to the pulse width of the contact longer than a predetermined time width. This allows a large number of contact signals to be reliably taken in from the viewpoint of the CPU. Since this contact input port 17 is also one of the features of the present embodiment, detailed processing for taking in a contact will be described later with reference to FIG.

The data bus 18, address bus 19 and control signal 20 are important signals belonging to the Z80 CPU core 11 and are basic signals required for adding external external parts and functions. That is, the data bus 18 is a data signal of a logic circuit system from D0 to D7, and the address bus 19 is a signal for specifying an address from A0 to A15. The control signal 20 includes RD (read), WR (write), IORQ (Io request), MERQ (memory request), M1 (M1) connected to the control bus, and INT (int) of the interrupt control signal. And the like.

By outputting such signals from the pins of the one-chip microcomputer, it is easy to add a memory and peripheral I / Os.

The ROM control signal 21 is RO
This control signal is necessary when M5 is externally connected.
Software for basic operation of the system is machine-coded in M25 and is incorporated therein. In the case of the ROM 25, in order to change the internal machine code, it is necessary to physically replace it. The ROM control signal 21 is valid from the memory address 0, but the end address is variable by software.

The RAM control signal 22 is a signal necessary for externally attaching the main RAM 26 for the system. The main RAM 26 can be used as a stack pointer or a calculation buffer for system operations, or can be used as contact data, for example. The effective number of contacts read from a small memory built in the contact input port 17 is stored.

The eraseable memory control signal 23 is supplied to a flash memory or an EEPROM (electric
This is a signal for controlling an electrically erasable and nonvolatile erasable memory 27 such as an all erasable programmable ROM.

In the eraseable memory 27, the software of a frequently-changed portion is machine-coded and written, thereby greatly reducing the time required for program development and correction. That is, the software portion that does not basically change uses the ROM 25, and the portion that frequently changes uses the eraseable memory 27. The machine code to be written in the erasable memory 27 is also sent from the master unit to the slave unit through the dedicated high-speed UART 12, and is stored in the ROM 2.
5 can be described by software. By doing so, it is not necessary to change the system software of many slave units.

As for the eraseable memory control signal 23, the ROM control signal 20 and the eraseable memory control signal 21
The effective area is variable according to the software set contents of the OM area boundary set register. This gives R
The software capacity of the OM 25 and the eraseable memory 27 can be made flexible.

FIG. 4 is a diagram showing a variable state of the effective area by the ROM area boundary set register. As shown in FIG. 4, when the power is turned on, the ROM 25 stores 0000H to 7F.
All data are valid up to FFH, and the eraseable memory 27 is all invalid.
When 0H is set, 0000H to 3FFFFH is valid for the ROM 25 after writing to the ROM area boundary set register, and 4000H to 7FFFH is valid for the eraseable memory 27.
Becomes effective, and the effective area can be changed.

The display control signal 24 is a control signal required when the display 28 is externally connected. In an actual system, a small display such as a seven-segment or a liquid crystal display may be attached depending on the child unit. This is because a display in accordance with the data input status or a command from the parent device is often required around the child device. Therefore,
In the case of seven segments, a control signal for writing to the seven-segment driver IC is output from a pin of the one-chip microcomputer 10. In the case of a liquid crystal, a one-chip microcomputer 10 outputs a control signal for the liquid crystal. This is because many I
Since C is required, if it is created internally and output as the display control signal 24, there is an advantage that the cost is low and the printed circuit board is small.

FIG. 3 is a block diagram of the contact input port 17 having a built-in noise cut type counter memory.

In FIG. 3, a contact input port 17 is a time-division sampling circuit 4 for sampling a contact input.
1. a judgment circuit 42 for judging validity from the distribution of continuity;
Comparison circuit 4 for comparing the set time width with the effective time width
Adder 44 for incrementing 3, +1; small memory 45 for storing the addition result (buffer for counting contacts);
It comprises a clear circuit 46 for clearing the contents of the small memory 45 when a PU is read.

The time-division sampling circuit 41, the judgment circuit 42, the comparison circuit 43, and the adder 44 constitute an effective number calculating means 47 for calculating the effective number corresponding to the pulse width of the contact longer than a predetermined time width as a whole. I do.

The contact input port 17 is newly developed from the following viewpoints. That is, in a system using a dedicated one-chip microcomputer, the operation of the CPU is various, and it is not possible to constantly monitor a large number of contact inputs. If a general-purpose input circuit is used to monitor the contacts under the operation of the CPU, the timing at which the contacts become valid may be missed and data may be missed.

Therefore, in this embodiment, the contact input port 17 having the configuration shown in FIG.

First, the time-division sampling circuit 41 and the judgment circuit 42 are a noise cut portion, take in a contact input signal in units of ms, and judge the validity of the signal from the continuity distribution of the signal. It is.

The signal for which the validity of the signal has been determined is input to the comparing circuit 43, and the time designated in advance by the software and the validity time of the signal from the preceding stage are compared. If the valid time of the signal from the previous stage is long, it is determined to be valid,
The count 1 is added by the adder 44 and the small memory 45 is added.
Add to

The small memory 45 is assigned to one contact input pin for each byte, and the actual effective number of contacts is automatically written.

Further, the CPU can read the contents of the small memory 45, and after reading, the clear circuit 46
Thereby, the read portion of the small memory 45 is cleared to zero.

That is, when the CPU reads the small memory 45 in which the effective number of contacts is automatically written, only the effective number of times from the previous reading to the present reading can be read.

The contact input port 17 having such hardware logic automatically stores only the effective number of times corresponding to the pulse width of the contact longer than the time width set by software, independently of the operation of the CPU. There will be a buffer. As a result, the CPU does not have to spend time monitoring the contacts, and can capture a large number of contact signals.

Further, it is possible to cope with a long-time pulse in which the effective state is continuously measured for a predetermined unit (for example, several times) or more and the effective number is counted by one when the observation is performed in the unit of the time width.

FIG. 5 is a block diagram showing the configuration of the dedicated high-speed UART 12. As shown in FIG. In the figure, the solid arrow indicates a normal signal path, and the broken arrow indicates a signal path for changing control contents.

In FIG. 5, the dedicated high-speed UART 12
Demultiplexer 51, transmission buffer changeover switch (SW1) 52, 100-byte transmission buffer A53,
100-byte transmission buffer B54, transmission buffer switch (SW2) 55, multiplexer 56, transmission register 57, transmission / reception shift register 58, loop register 200, transmission enable control unit 59, break signal generator 60, CRC calculator 61, start bit detection Vessel 6
2. Loop switch A (SW5) 63 (first loop switch), loop switch B (SW6) 64 (second loop switch), loop switch C (SW7) 201
(Third loop switch), ID detector 65, transmission mode detector 66, reception register 67, demultiplexer 68, reception buffer changeover switch A (SW4) 6
9, a 100-byte receive buffer A70, a 100-byte receive buffer B71, and a receive buffer switch B (S
W3) 72, multiplexer 73, break signal detector 74, control register 75, status register 76, self ID set register 77, DMA controller 7
8, interrupt control unit 79, TXEN pin 80, transmission output (TXD) pin 81, reception input (RXD) pin 82, D
RQ pin 83, DACK pin 84 and INTRQ pin 8
5 is comprised.

From the reception input (RXD) pin 82 to the start bit detector 62, the loop switch A (SW5) 6
3, transmission / reception shift register 58, loop switch C (S
W7) The path from the path 201 to the DRQ pin 83 via the loop switch B (SW6) 64 constitutes a loop path (first loop path) for constructing a loop system as a whole.

Further, the start bit detector 62, the loop register 200,
DRQ via loop switch C (SW7) 201 (third loop switch) and loop switch B (SW6) 64
The path reaching the pin 83 also constitutes a loop path (second loop path) for constructing a loop system as a whole.

The loop path (second loop path) passing through the loop register 200 and the loop switch C (SW7) 201 is used only at the time of the loop. That is, when the transmission / reception shift register 58 is used in a loop, a time delay of eight clocks is obtained, but a delay of one clock is sufficient in a loop path passing through the loop register 200 and the loop switch C (SW7) 201. Therefore, the second loop path is used only during the loop.

As described above, in the present embodiment, the transmission / reception shift register 58 for temporarily storing transmission / reception data, the loop switch A (SW5) 63 on the input side of the transmission / reception shift register 58, and the output side A loop switch B (SW6) 64 is installed in the controller, and two loop switches A (SW5) 63 and B (SW6) 64 are switched to take in data on a loop path or perform loopback control for sending out data. In addition, a loop register 200 and a loop switch C (SW7) 201 are provided, and only during a loop, the delay is minimized (for one clock) using this loop path.

The CRC calculator 61 outputs a CRC (cyclic r) for error detection to the output from the 100-byte transmission buffer A53 and the output from the 100-byte transmission buffer A54.
(redundancy check: cyclic redundancy check code). Further, it has a function of detecting an error in the transmitted data by analyzing the CRC and correcting the error.

Hereinafter, the dedicated high-speed U configured as described above
The operation of the one-chip microcomputer 10 including the ART 12 will be described.

The dedicated high-speed UART 12 is a general UA
Unlike RT, one of the important features of the one-chip microcomputer 10
One. In particular, the dedicated high-speed UART 12 has a new function for constructing a loop system. Therefore, the loop system at the time of transmission and reception will be described for each corresponding circuit unit, and then, referring to FIGS. The operation of the function unit will be described.

[Characteristic operation in loop system]
The operation of the circuit unit for realizing the loop system is as follows.
~ 4. It is described in.

1. 100-byte transmission buffer A53, 1
The operations of the 00-byte transmission buffer B54, the transmission buffer changeover switch (SW1) 52, and the transmission buffer changeover switch (SW2) 55 are as follows.

When there are many types of data requests sent, normal data is transferred to the 100-byte transmission buffer A5.
3 and the 100-byte transmission buffer B54 is
Used as a transmission buffer for other data requests. Thus, the two transmission buffers A53, B
By using 54, writing of transmission data from a request becomes smooth in terms of software and time. Further, in the case of data of 100 bytes or more, a method of writing data to the 100-byte transmission buffer B54 while transmitting the contents of the 100-byte transmission buffer A53 can be used.

Transmission buffer changeover switch (SW1) 5
Reference numeral 2 denotes a selection switch for selecting a buffer to be written from the CPU, and can be set by writing to the control register 75. The transmission buffer changeover switch (SW2) 55 is a switch for selecting a buffer to be transmitted, and can be set by writing to the control register 75.

2. On the other hand, the 100-byte receive buffer A7
The operations of the 0, 100-byte reception buffer B71, the reception buffer changeover switch A (SW4) 69 and the reception buffer changeover switch B (SW3) 72 are as follows.

The data in the 100-byte receive buffer is
Since a predetermined time is required when data is read out by the PU, the efficiency of the loop line increases if one of the reception buffers can receive data during the read operation by the other reception buffer. For example, when the reception of the 100-byte reception buffer A70 is completed, the reception buffer changeover switch A (SW4) 69 is automatically connected to the 100-byte reception buffer B71. The reception buffer changeover switch B (SW3) 72 is connected to the 100-byte reception buffer A70 for reading previously received data, and is automatically connected to the 100-byte reception buffer B71 when reading is completed. However, the reception buffer changeover switch A (SW4) 69 and the reception buffer changeover switch B (SW3) 72 can also be controlled by writing to the control register 75. This connection state can be confirmed by the status register 76.

The above 1. And 2. As described above, by switching and using two buffers, the utilization efficiency of the loop line can be increased.

3. When a start bit is input, the start bit detector 62 checks the validity at a half position (center position) of the pulse width specified by the baud rate, as in a general start-stop synchronous UART. If there is, it starts reading each data and stop bit in the time unit specified by the baud rate. That is,
A synchronous operation for sampling the serial data input to the reception input (RXD) pin 82 at the center of each bit with few errors is performed.

4. The transmission register 57, the transmission / reception shift register 58, the loop register 200, the reception register 67,
Loop switch A (SW5) 63, Loop switch B
(SW6) 64 and loop switch C (SW7) 201
The operations at the time of transmission, reception, loop, and loop OFF are as follows.

At the time of transmission, the loop switch A (SW5) 6
3 OFF, Loop switch B (SW6) 64 O
N, the loop switch C (SW7) 201 is connected to the transmission / reception shift register 58 side, and data is output from the transmission / reception shift register 58.

The parallel data in the 100-byte transmission buffer designated to be transmitted by the control register 75 is transmitted to the transmission register 57 through the transmission buffer switch (SW2) 55 by the function of the multiplexer 56. Then, the data is loaded from the transmission register 57 to the transmission / reception shift register 58. In the transmission / reception shift register 58, a start bit and a stop bit are added at a specified baud rate as shown in FIG. At this time, the loop switch A (SW5) 63 is turned off and the loop switch B (SW6) 64 is turned on in order to avoid collision of transmission data.

At the time of reception, the loop switch A (SW5) 6
3 ON, Loop switch B (SW6) 64 ON
(Possible loop), Loop switch C (SW7) 201 Connected to the loop register 200 side, and data is output with a small delay through the loop register 200 (Possible loop).

The data of the data string determined as the self ID by the ID detector 65 among the received data passing through the start bit detector 62 is the loop switch A (SW5) 6
3 and reaches the transmission / reception shift register 58. Here, when the transmission / reception shift register 58 is enabled by the validity signals of the ID detector 65 and the transmission mode detector 66, the serial data of the transmission / reception shift register 58 is the data deleted by deleting the start bit and the stop bit. Is loaded into the reception register 57. The data loaded in the reception register 57 passes through the reception buffer changeover switch A (SW4) 69 as parallel data and is stored in the 100-byte reception buffer.

At the time of transmission and reception, the loop switch A (SW
5) 63 and the loop switch B (SW6) 64 are automatically switched. When not transmitting or receiving, loop switch A
(SW5) 63 and loop switch B (SW6) 64
Is turned ON / OFF by writing to the control register 75.
OFF can be set.

Further, even at the time of the above reception, if the set is a loopable set, the data loops and the master unit is cut.

At the time of loop, loop switch A (SW5)
63 ON, loop switch B (SW6) 64 O
N, Loop switch C (SW7) 201 Connected to the loop register 200 side, data is output through the loop register 200 without delay (loop is possible).

When the loop is OFF, the loop switch A (S
W5) 63 ON, loop switch B (SW6) 64
OFF, loop switch C (SW7) 201 Data is cut by loop switch B (SW6) 64 (loop disabled).

The operation of the transmission unit, the reception unit, and other functional units on the premise of the loop system operation will be described below.
Loopback OF of master unit using dedicated high-speed UART12
F, it is assumed that the loopback of the slave unit is ON.

[Operation of Transmission Section] FIG. 6 is a diagram showing a 100-byte transmission / reception buffer and a table of CRC values (transmission mode 10).

The data to be transmitted is transmitted to the 100-byte transmission buffer A by the CPU through the demultiplexer 51.
53 or 100 bytes are written to the transmission buffer B54. Then, the CRC calculator 61 performs a CRC calculation.

As shown in FIG. 6, the demultiplexer 51 is an address indicator for writing the data in the transmission buffer in the order in which the data was written by the CPU. The order of the data to be written is as follows: the destination ID is at the top, the transmission mode indicating the number of data is the second, and the data is written sequentially from the first. The number of data to be written by the CPU is 10 times that of the transmission mode including the first destination ID, the second transmission mode, and each data. When writing is completed, CRC calculation is performed. In the table of the data, the transmission mode is 10
At the time of, it becomes as shown in FIG. Here, in FIG. 6, CRC1 to CRC10 are the total values in the horizontal direction,
CRC11 to CRC20 are total values in the vertical direction. CRC21 is the sum of CRC1 to CRC10 and should be equal to the sum of CRC11 to CRC20.

After the CRC calculation is completed, this data string is sent to the destination I
The data is temporarily loaded into the transmission register 57 in order from D, and then serially output from the transmission / reception shift register 58. When the transmission mode is 10, the result is as shown in FIG.

The format of each data output from the transmission output pin (TXD) 81 is serial data.
As shown in (1), the start bit is 1 bit, then the data from D0 to D7, and then the stop bit is 1 bit. The 1-bit pulse width of this serial data is 200 ns when the transmission baud rate is 5 Mbit / sec.
And 100 ns at 10 Mbit / sec.
This transmission baud rate is considerably high for a UART. Therefore, the wiring for transmitting the signal of the dedicated high-speed UART 12 is basically based on using an optical connector such as a toslink and an optical cable.

The transmission procedure of the dedicated high-speed UART 12 has been described above. The features of this transmission unit are that the transmission baud rate is as high as 5 Mbit / sec to 10 Mbit / sec, there are two transmission buffers with a maximum of 100 bytes, and the CRC calculation is automatically calculated. In particular, by switching between the two transmission buffers A53 and B54, the utilization efficiency of the loop line can be increased.

[Operation of Receiving Unit] In the receiving operation, the own ID is written in the self ID set register 77 of each dedicated high-speed UART 12 by the CPU in advance.

Here, the operation sequence is such that when the dedicated high-speed UART 12 is used for the master unit, the loopback is turned off, and when the dedicated high-speed UART 12 is used for the slave unit, the loopback is turned on.

At the time of reception, as described above, when the ID detector 65 determines that the received data is the self ID,
The transmission / reception shift register 58 is enabled, and the data of the data string is turned on when receiving the loop switch A (SW).
5) It reaches the transmission / reception shift register 58 through 63. Here, when the transmission / reception shift register 58 is in the enabled state, the serial data of the transmission / reception shift register 58 is loaded into the reception register 57. The data loaded in the reception register 57 passes through the reception buffer changeover switch A (SW4) 69 as parallel data and is stored in the 100-byte reception buffer.

That is, when data is looped, data input from the reception input pin (RXD) 82 passes through the loop register 200, the loop switch C (SW7) 201 and the loop switch B (SW6) 64, and passes through the transmission output pin ( TXD) 81. At this time, only when the first data is determined to be the self ID by the ID detector 65, the data input from the reception input pin (RXD) 82 is
The signal is taken in by the transmission / reception shift register 58 enabled through the loop switch A (SW5) 63. In the case of a specific ID such as a broadcast, the same path is used even when the data is taken into the 100-byte reception buffer through the above-described path.

On the other hand, the loop switch A (SW5) 63 is turned on and the loop switch B
(SW6) 64 is OFF and loop switch B
When the (SW6) 64 is turned off, the loopback is turned off, and when the loop switch A (SW5) 63 is turned on, the transmitted / received loop data is taken into the transmission / reception shift register 58 to confirm whether or not the data can be transmitted.

The data string of the serial data output by the above-described transmission operation passes through the transmission optical connector, the optical cable, and the reception optical connector, and enters the reception input pin (RXD) 82 of the next-stage dedicated high-speed UART. Then, the start bit detector 62, the loop register 200, the loop switch C (SW7) 201, and the loop switch B (SW6) 64
Is transmitted again from the TXD pin 81 through the loopback line consisting of

This operation is repeated to loop until the pin end of the dedicated high-speed UART of the master unit that has output the data.

FIG. 9 is a diagram showing a loop system using the above-mentioned dedicated high-speed UART 12, in which the master unit is in loopback OFF and the slave unit is in loopback ON.

As shown in this figure, a loop centering on the transmission / reception shift register 58 is formed, and a loop system connected in a circular shape is constructed.

FIG. 10 shows a dedicated high-speed UA for a one-chip microcomputer.
It is a figure which shows the loop system which connected RT with the optical cable. In this figure, each one-chip microcomputer 10 has a dedicated high-speed UA through an optical connector 90 and an optical cable 91.
RT transmission output pin (TXD) 81, reception input pin (R
XD) 82 are connected in a loop.

In the signal loop operation shown in FIG. 10, the destination ID which is the first data of the transmitted data string,
When the self-ID set in a certain dedicated high-speed UART becomes the same, the transmission mode detector 66 starts operating,
After detecting the transmission mode, which is the next data, and calculating the number of data to be taken in, the data is taken in while counting is performed. In this case, for example, when ID2 is output, loopback of ID2 is disabled in order to prevent the data transmitted by ID2 from being output again from the transmission output pin (TXD) 81 of ID2 after making one round, and Makes loopback possible. When a line break occurs, the reception input pin (RXD) 82 of the cable
Is followed by a low signal and a break occurs.

Here, since only the destination ID has a 7-bit length as shown in FIG. 8, it is easy to detect the destination ID which is the head of the data. Further, when the transmission mode is detected, the number of data to be taken can be automatically calculated by the equation (1) shown in Expression 1.

[0122]

(Equation 1)

When the number of data to be taken is completed, I
The D detector 65 starts ID detection again. The fetched data string is converted by the demultiplexer 68 into a 100-byte receive buffer A 70 or a 100-byte receive buffer B7.
1 are arranged as shown in FIG. After that, CR
Each CRC is calculated by a C calculator 61, compared and checked by an internal CRC checker, and if there is an error, it is corrected by a CRC corrector.

When the data is completed, the reception completion bit of the status register 76 of the dedicated high-speed UART becomes valid, and C
The reception completion is indicated to the PU.

If the reception interrupt enable bit of the control register 75 is set to be valid by software, the interrupt control unit 79 operates and INT
RQ pin 85 provides a valid output. By connecting the INTRQ pin 85 to the clock trigger input pin of the CTC, the completion of reception can be transmitted to the CPU at high speed.

When the CPU senses the reception, the 100-byte receive buffer A 70 or the 100-byte receive buffer B 7
From 1, data is sequentially taken in from the destination ID which is the first data. However, when reading data, each CRC is ignored. When the CPU reads the second transmission mode and determines that the number of data is large,
Work on DMAC13 and dedicated high-speed UART1
The DMA enable bit of the control register 75 is enabled so as to operate the DMA control unit 78 for enabling the DRQ pin 83 and the DACK pin 84 of D2.
MA transfer is also performed. This is faster than the operation by the CPU and is useful for speeding up the system.

As described above, a characteristic of the receiving unit is that the loopback line can be enabled / disabled by software while shaping the distorted waveform. In addition, self ID
Can be set, a looped system can be configured as shown in FIGS. 9 and 10, and a one-to-many interactive UART interface can be constructed. Incidentally, the existing general-purpose UART is basically one-to-one interactive without an ID, and the transmission / reception buffer is several bytes to several tens of bytes. On the other hand, the one-chip microcomputer 10 including the dedicated high-speed UART 12 according to the present embodiment
A receiving buffer of up to 100 bytes can be realized, and an efficient system can be provided together with the baud rate.

As other functions, a break control system such as a break signal detector 74 and a break signal generator 74 is provided. This is in order to cope with a break in the loop which is a major trouble in a loop system as shown in FIG.

That is, the normal high speed UART1
The level of the transmission output pin (TXD) 81 of No. 2 is High. Even when transmitting data, High and Lo
Although there are both levels of w, there is idling, which is a High level of at least one bit, between the serial data and the data. Therefore, when the optical connector 90 is disconnected or the optical cable 91 is disconnected, the Low level continues for a long time. Therefore, if the Low level continues for 1 ms or more, the break signal detector determines that the circuit is in the break state, and makes the bit indicating that the break is in progress in the status register 65 valid to indicate the intention to the CPU. In addition, it works on the interrupt control unit 79 to make the INTRQ pin 85 valid, thereby transmitting a line break to the CPU at a high speed. After detecting and determining this, the CPU outputs a warning indicating a break in the line to urge the line to be repaired.

The break signal generator 60 activates the break generation bit of the control register 75 by the CPU when communication control becomes impossible due to occurrence of a handshake error or the like of a loop communication line, and the break signal generator 60 generates a break. A Low pulse of the signal is output to the TXD pin 81 for 1 ms. This pulse is output several times in time units to signal the reconfiguration of the line.

As described above, the break signal generator 60 and the break signal detector 74 can be used as a countermeasure against a trouble in a loop line.

Further, as other functions, there are a transmission enable control section 59 and a TXEN pin 80. They are,
When the noise of the dedicated high-speed UART line is small, RS42
This is a preliminary function used for timing control for outputting a differential signal when a line is connected with a differential signal such as 2.

As described above, the one-chip microcomputer 10 according to the second embodiment has an 8-bit CPU core 11, a dedicated high-speed UART 12, a DMAC 13, a CTC 1
4, an SIO 15, a PIO 16, a contact input port 17, a data bus 18, and an address bus 19, and a ROM 25 controlled by each control signal,
The dedicated high-speed UART 12 includes an AM 26, an erasable memory 27, and a display device 28. The demultiplexer 51, a transmission buffer switch (SW1) 52,
100-byte transmission buffer A53, 100-byte transmission buffer B54, transmission buffer switch (SW2)
55, multiplexer 56, transmission register 57, transmission / reception shift register 58, transmission enable control unit 59, break signal generator 60, CRC calculator 61, start bit detector 62, loop switch A (SW5) 63, loop switch B (SW6) 64, loop switch C (SW
7) 201, ID detector 65, transmission mode detector 66,
Receive register 67, loop register 200, demultiplexer 68, receive buffer changeover switch A (SW
4) 69, 100-byte receive buffer A 70, 100-byte receive buffer B 71, receive buffer switch B (SW3) 72, multiplexer 73, break signal detector 74, control register 75, status register 76, self ID set register 77, DMA Control unit 78, interrupt control unit 79, TXEN pin 80, transmission output (TXD) pin 81, reception input (RXD) pin 8
2. DRQ pin 83, DACK pin 84 and INTRQ
The dedicated high-speed UART 12 is composed of pins 85 and is connected to another external dedicated high-speed UART via an optical loop line composed of an optical fiber and an optical connector. Since the loopback line can be enabled / disabled by software while shaping the waveform, and the self ID can be set, a looped system can be configured. Thus, a one-to-many interactive UART interface can be constructed.

Further, a break control system such as the break signal detector 74 and the break signal generator 60 can appropriately cope with a loop break which is a major trouble in a loop system.

The one-chip microcomputer 10 according to the second embodiment has a contact input port 17 with a built-in noise-cut counter memory. This contact input port 1
7 can automatically store only the effective number of times corresponding to the pulse width of the contact longer than a predetermined time width in the small memory (contact count buffer) 45, and assure the large number of contact signals at any timing as viewed from the CPU. Can be captured. As a result, the CPU does not have to spend time monitoring the contacts, and can capture a large number of contact signals.

Note that in the second embodiment, the dedicated high-speed UA
As a loop switch function of the RT, a loop switch A (SW5) 63 is provided on the input side of the transmission / reception shift register 58,
A loop switch C (SW7) 201 and a loop switch B (SW6) 64 are installed on the output side, and three loop switches A (SW5) 63, B (SW6) 64, and C (SW
7) 201 is switched to take in data on the loop path or send data.

By adopting such three loop switch configurations, a highly reliable loop system can be realized. Further, since both the master unit and the slave unit have the same hardware configuration, it is possible to construct a loop system that is easier to use and has higher versatility. However, any configuration is possible as long as it is a dedicated high-speed UART having a loop switch function for switching loops, and the configuration is not limited to the configuration including the three loop switches.

For example, only the master unit is provided with the above three loop switches, and the slave unit is provided with one loop switch (for example, the loop switch A (SW5) in FIG. 5).
63 may be deleted). Furthermore, the parent machine,
Dedicated high-speed UAR with one loop switch for both slave units
Despite using T, only the master unit is a dedicated high-speed UA dedicated to sending
An embodiment in which two dedicated RT UARTs and two dedicated high-speed UARTs dedicated to transmission are respectively used may be used.

In the second embodiment, the CRC calculation is performed as a data error check. However, the present invention is not limited to this, and may be, for example, a SUM check.

Third Embodiment FIG. 11 is a block diagram showing a configuration of a one-chip microcomputer and a contact monitoring system according to a third embodiment of the present invention.
0 is an example applied to a contact monitoring system. FIG. 1 illustrates the contact monitoring system according to the third embodiment.
The same components as those of 0 are denoted by the same reference numerals, and the description of the overlapping portions will be omitted.

Referring to FIG. 11, reference numeral 100 denotes a main unit main CP.
U (master), 101 is a plurality of master sub CPUs composed of a one-chip microcomputer 10, and 10 is the dedicated high-speed UART 1
2 are one-chip microcomputers as a number of slave units, each one-chip microcomputer 10 and a master unit sub CPU 101.
Are connected in a loop to the transmission output pin (TXD) 81 and the reception input pin (RXD) 82 of the dedicated high-speed UART through an optical connector 90 and an optical cable 91, respectively.

The main CPU 100 has a large-capacity storage device 102 such as a hard disk, a CRT,
A display 103 such as a large LCD, an input device 104 such as a keyboard and a mouse, and an input / output device 105 for other terminals such as an Ethernet, an RS232C, and an arcnet are connected. The plurality of parent machine sub CPUs 110 include a shared memory and a handshake I / O (not shown).

Also, the one-chip microcomputer 10 connected in a loop as a number of slave units has a number of contact inputs 110, a seven-segment output 111, and a liquid crystal display output 1 respectively.
12, auxiliary output terminals such as a solenoid output 113 and a relay output 114 are provided.

The main unit sub CPU 101 is a sub CPU.
To use the dedicated high-speed UART,
As with the chip microcomputer 10, the one-chip microcomputer 10
Use

The main CPU 100 is a 16-bit or more CPU for high-speed and large-capacity data processing.
Using the (master), data and commands are exchanged with the parent machine sub CPU 101 using a shared memory and handshake I / O.

For the dedicated UART, the optical fiber cable 91 and the optical connector 90 are used to connect the master sub CPU.
101 and a number of slave units (one-chip microcomputer 10) are connected in a loop.

The operation procedure of the contact monitoring system configured as described above will be described below.

[0148] The ID number is set by setting the parent device sub CPU1 to ID1, and thereafter, from the child device 1 to the child device 126 in order.
2 to ID127. The loopback line is set to OFF only for the parent device sub CPU1 (hereinafter, referred to as sub CPU1).

On the other hand, in the slave unit, as a normal operation, data of a large number of contact valid times is read out from the small memory 45 (see FIG. 3) in which the contact valid number is automatically written, and the main RAM 26 ( (See FIG. 2). This is stored in the transmission buffer of the UART. The operation procedure of the system is described below.

1. The main unit main CPU 100
In order to obtain data on the number of effective contacts of the child device 1 belonging to U1, a data request command for the child device 1 is sent to the sub CPU 1 through a shared memory or the like.

2. When the sub CPU 1 receives the data request from the shared memory or the like and determines that the command is a request command, the sub CPU 1 sends the data request command to the child device 1 as ID2 through the dedicated high-speed UART.

[0152] 3. The data request command sent from the sub CPU 1 through the dedicated high-speed UART is fetched into the reception buffer only by the dedicated high-speed UART of the slave 1 that is ID2.

4. The CPU of the slave unit 1 is a dedicated high-speed UART
, The data reception is sensed, the data is read from the reception buffer, and then the data request command is detected.

[0154] 5. Based on this detection, the CPU of the child device 1 writes the transmission mode corresponding to the data amount in the transmission buffer using the ID of the parent device as the destination ID.

6. Next, the CPU of the child device 1 writes the data of the effective number of contacts stored in the main RAM 26 (see FIG. 2) into the transmission buffer. When the data amount is large, high-speed transfer may be performed using the DMAC.

[0156] 7. When the number of bytes corresponding to the transmission mode is written into the transmission buffer, the data is transmitted from the dedicated high-speed UART of the slave unit 1 after the CRC calculation.

8. The transmitted data is transferred to the parent device through the optical connector 90 after the child device 2 and the loopback line. Among them, only the dedicated high-speed UART belonging to the sub CPU 1 of the master unit having the same destination ID takes in the data.

9. The received data of the number of valid contacts of the slave unit 1 is taken out of the reception buffer by the sub CPU 1, sent to the master unit main CPU 100 by a shared memory or the like, and processed by the master unit main CPU 100.

10. When it is determined that the output of an output device such as a display or a relay is required in the slave unit 1 of the sub CPU 1 after the processing by the master unit main CPU 100, an output command is sent from the master unit main CPU 100 to the sub CPU 1. .

11. This output command corresponds to 2. To above 4. Is transmitted to the slave unit 1 of the sub CPU 1 by the operation described above, and after detecting the output command, the slave unit 1 outputs to the liquid crystal display or the segment, or outputs to the relay or the solenoid.

As described above, this application system is very effective for constructing a one-to-many interactive loop circuit.

The additional functions in the contact monitoring system to which the one-chip microcomputer is applied are as follows.

When this application system is used, if the transmission mode 0 which is the all-unit reception mode is used, very efficient means is generated. Basically, the transmission mode of the dedicated high-speed UART can transmit and receive data ten times as large as the transmission mode. However, in the transmission mode 0 as a special mode, all the dedicated high-speed UARTs connected receive 100-byte data.

Thus, it can be used, for example, for writing a machine language in an erasable memory.

As described above, a program whose software is frequently changed uses an erasable memory such as a flash memory or an EEPROM and rewrites the machine language of the program using a dedicated high-speed UART. At this time, the program is sent to all the slaves using the transmission mode 0. This is very effective in terms of time.

At this time, after receiving the program rewriting command, the slave unit receives a machine language as a changing program from the dedicated high-speed UART in units of 100 bytes and performs a rewriting operation. However, during this operation, the CPU operates according to the program supplied from the ROM containing the basic software.

Further, ID numbers can be automatically assigned at power-on or after reset. Furthermore, a loop-like line check can be automatically performed.

At power-on or after reset, all master units and slave units are set by software so that the loopback line is turned off. Thereafter, the master unit sends an ID set command 2 to the slave unit 1 in the transmission mode 0. Since the high-speed dedicated UART of the slave unit 1 is in the transmission mode 0 which is the all-unit reception mode even if the self ID is not set,
D set command 2 can be received.

Upon receiving ID set command 2, handset 1 sets its own ID to "2" and turns on the loopback line. Then, an ID set command (self ID + 1) is sent to the slave unit 2 in the transmission mode 0. When each of the slaves executes the above processing in turn, the transmission mode 0 is displayed at the master.
Then, an ID set command (the number of slave units + 1) is sent. By determining the ID set command, the master unit can confirm the number of slave units and confirm that there is no error in the loop line. At this time, the ID of the slave unit is automatically assigned.

Next, referring to FIG. 12 to FIG.
A comparison is made with a system using ART or another transmission LSI.

FIG. 12 is a block diagram showing the configuration of a conventional general-purpose UART.

As shown in FIG. 12, the conventional UART has no ID and is of the one-to-one interactive type. For this reason, when trying to connect a large number of slaves, a large number of UARs
T is required, so that a large number of ICs constituting the UART are required, and a large number of cables and the like are also required.

In addition, since the transmission buffer and the reception buffer are as small as several bytes, it is difficult to transfer a large amount of data, and it takes a long time. Further, there is no CRC check or correction function, the reliability of the received data is low, and the break signal is only the detection of the break reception.

On the other hand, the dedicated high-speed UART is a one-to-many interactive type, and uses a cable in a loop.
This reduces the number of chips, shortens the cable, and results in an inexpensive system. Also, if the send / receive buffer is 100
Bytes are large, the baud rate is as high as 5 Mbit / sec to 10 Mbit / sec, and large-capacity data can be transferred per time. There is a CRC check and correction function for the received data, which improves the reliability of the received data. In addition, since the transmission line is a loop, not only break detection but also a break generation circuit is provided.

Here, a comparison is made with a general arcnet IC.

FIG. 13 is a diagram showing connection by an optical cable using an arc net IC, and FIG.
It is a figure which shows the cable connection of the loop by ART.

The arcnet IC shown in FIG. 13 is also a multi-channel interactive LANIC, but employs a token ring system. In this case, the possible output time is determined in the order of the ID numbers, and there is a large time lag from the setting of the transmission data to the transmission. This dedicated high-speed UART is 1
It is a multi-user interactive type, and the responsiveness of the system is good when using the master unit and a large number of slave units.

FIG. 13 shows a connection obtained by an optical connector or an optical cable in the Arcnet system, and requires about twice as many connectors and cables as in the loop-type high-speed UART system shown in FIG. Become. Further, a comparison between the transmission signals of the arc net and the dedicated high-speed UART is shown in FIG.
The arc net is a signal of return zero, and the dedicated high-speed UART is a signal of knot return zero. Therefore, the required frequency characteristics of the optical connector are about half,
Inexpensive connectors are available.

By the way, recently used general-purpose LANs
Let's compare it with an Internet IC, which is an IC. Ethernet ICs are very fast and multi-channel interactive. However, since it is made of 16 bits or more, if it is used for a large number of slaves, the cost becomes high in terms of hardware. In addition, TC @ / IP (Tran
Software such as Smission Control Protocol / Internet Protocol) is difficult, and using a software package for a drive requires a copyright fee. On the other hand, the dedicated high-speed UART system is inexpensive in terms of hardware because it can be formed into one chip with 8 bits, and is also a system that is easy to make in terms of software.

As described above, the contact monitoring system according to the third embodiment includes a master main CPU (master) 1.
00, a plurality of master unit sub-Cs each comprising one-chip microcomputer 10
PU 101 and a number of one-chip microcomputers 10 as a number of slave units provided with a dedicated high-speed UART 12. Each one-chip microcomputer 10 and the master unit sub CPU 101 are provided with an optical connector 90.
And the dedicated high-speed UART 12 of the one-chip microcomputer 10 is connected to the transmission output pin (TXD) 81 and the reception input pin (RXD) 82 of the dedicated high-speed UART in a loop through the optical cable 91. Since it is a type and a cable can be used in a loop, the circuit is simplified and an inexpensive system can be realized.

The transmission / reception buffer is as large as 100 bytes, and the baud rate is from 5 Mbit / sec to 10 Mb.
It is as fast as it / sec, and can transfer a large amount of data per time. Furthermore, there is a CRC check and correction function for the received data, and the reliability of the received data can be improved. Further, since the transmission line has a loop shape, not only break detection but also a break generation circuit is provided, so that maintenance becomes easy.

In addition to the above effects, the one-chip microcomputer 10
Dedicated high speed UART 12 is one-to-many interactive,
When applied to a method of connecting a large number of slave units to a master unit, for example, to a contact monitoring system, the responsiveness of the system is good, and one-to-one
The number of connectors, cables, and the like can be greatly reduced as compared with those of the above. Also, for example, Arcnet and dedicated high-speed U
When the transmission signals of the ART12 are compared, since the arc net is a signal of return zero and the dedicated high-speed UART is a signal of not return zero, the required frequency characteristic of the optical connector is reduced to about half, and an inexpensive connector is used. Available.

Furthermore, the dedicated high-speed UART system has 8
Because it can be made into one chip with bits,
The system is inexpensive in terms of hardware as compared with a high-performance multi-channel interactive system using such a method, and is easy to make in terms of software.

Therefore, a one-chip microcomputer and a contact monitoring system having such excellent features can be realized by combining a large number of slave units for monitoring a large number of contact signals and a master unit for centrally processing the data by a high-speed communication line. If the present invention is applied to a contact monitoring system to be connected, a system excellent in performance, cost and operation can be constructed in this contact monitoring system.

For example, in a game arcade in which a pachinko gaming machine is installed, pachinko balls are counted for various purposes, and the counting result is sent to a data management machine. It accumulates data and provides it for analysis. In addition, in addition to the above, there are some amusement arcades that count out balls of a gaming machine or count pachinko balls obtained by a player at the time of prize exchange. This type of communication between slave units calculating each count value is a type that hardly needs to be performed. It is a very effective use to collect data in the pachinko ball management device using the LAN.

That is, as shown in FIG. 9, slave units 1 to 7 are installed near the underframe of each game machine, and a master unit is installed for each island facility, for example. The equipment is connected in a loop with an optical cable, the master unit and the data management unit (main) are connected by a high-speed communication line, and applied to a contact monitoring system that centrally processes slave unit data by the master unit and the data management unit. It is suitable. The counting in the pachinko game facility requires a small amount of data by counting but a large number of counted data and a large number of connected slave units, and requires high reliability at low cost.

In particular, it is not affected by noise generated from motors, solenoids, portable telephones and the like, and is installed and operated by persons who do not necessarily have sufficient knowledge and skills in terms of system installation and maintenance. Often. In such a case, the present contact monitoring system is not only inherently superior in noise immunity, but also simple in installation, in a system in which many slave units and master units are connected in a loop by an optical cable. Since the slave units are merely connected by an optical cable, installation, maintenance, and extension and change are extremely easy, and no special technique is required. In this regard, costs for installation and maintenance can be reduced.

Further, since there is a one-to-many LAN system, the system can be easily changed.
For example, by using an ID that can be received by all terminals at the same time, a program or data can be sent to all terminals with this common ID. In addition, programs adapted to each pachinko machine can be downloaded simultaneously or individually from the center.

In each of the above embodiments, the present invention is applied to a contact monitoring device provided with a plurality of slave units for monitoring a large number of contacts located far from each other and a master unit for centrally processing contact data from the plurality of slave units. Although an example has been described, the present invention is not limited to this, and can be applied to any application as long as the apparatus has a one-chip microcomputer having a UART function for performing bit-serial data transfer.

Further, the data transfer device and the contact monitoring system according to each of the above embodiments can be applied to the LAN system of the pachinko ball counting device as described above.
Of course, the present invention is not limited to this, and it goes without saying that the present invention can be applied to any device (for example, a hotel room equipment management system) as long as it is a communication system that transmits and receives various count information.

Further, it is needless to say that the types, numbers, connection methods, etc. of the various circuits, registers and the like constituting the one-chip microcomputer and the contact monitoring system are not limited to the above-described embodiment.

Further, in the above-described configuration, the data transfer device can be applied to, for example, a microcontroller, but may be a part of a circuit incorporated in the microcontroller or the like.

In each of the above embodiments, the ROM is used as the external memory. However, the present invention is not limited to this. For example, an EPROM (erasable program
bleROM), EEPROM (electrically erasable prog)
It is also possible to use a rammable ROM), a flash memory or the like. Further, although an external memory is used as a supply unit for supplying a program from the outside, the external memory is not limited as long as it can supply a program.

Further, it goes without saying that the types and number of various circuits and registers constituting the one-chip microcomputer and the contact monitoring system and the connection method are not limited to those of the above-described embodiment.

[0195]

According to the data transfer apparatus of the first aspect,
A loop path for looping the reception data as transmission data to the transmission side, a data holding means provided on the loop path for temporarily storing transmission / reception data, a switch means connected to the data holding means, and a switch means. By switching, take in the data of the data holding means,
Or a control means for sending data to the data holding means or controlling the received data to be looped to the transmission side, so that a plurality of connections can be made on a loop line which hardly requires communication between slave units. In this case, a highly flexible loop system can be constructed with a very simple configuration.

Therefore, the present invention is very effective when applied to a one-to-many interactive communication system which hardly requires communication between slave units.

In the data transfer device according to the second aspect, the data transfer means includes an identification code (ID number) for identifying itself.
Has been added, processing means for reading the identification code, processing only the corresponding data, a loop path that can connect a plurality of terminals in a loop to form a loop system, installed on the loop path, Data holding means for temporarily storing transmission / reception data, switch means connected to the data holding means, and switching of the switch means to take in data from the data holding means, or to send data to the data holding means or to receive received data Since it is configured with control means for controlling to loop on the transmission side,
A looped system can be configured, and a one-to-many interactive interface can be constructed for a large variety of data.

In the data transfer device according to the third aspect, the data holding means is constituted by a transmission / reception shift register capable of taking in serial data as parallel data and outputting the parallel data as serial data. Normal serial data transfer can be easily performed.

According to the data transfer device of the present invention, the data holding means is constituted by a register capable of outputting input data at the minimum clock timing. Very little data transfer can be performed.

The data transfer device according to the fifth aspect further includes a plurality of transmission buffers for temporarily storing transmission data, and a plurality of reception buffers for temporarily storing reception data. Among the buffers, one transmission buffer enables the transmission data to be written by another transmission buffer while the transmission operation is performed, and among the plurality of reception buffers, one reception buffer reads by another reception buffer while the reception operation is performed. Since this is made possible, the use efficiency of the loop line can be increased by switching and using a plurality of transmission / reception buffers.

In the data transfer apparatus according to the sixth aspect, the switch means may include at least one switch provided on the loop path.
Since one or more switches are provided, the loopback line can be enabled / disabled by software. For example, if a self-identification code is set, a looped system can be configured, and the loopback line can be configured. Lines can be enabled / disabled by software.

[0202] In the data transfer device according to the seventh aspect, the switch means is provided on a loop path and temporarily stores a transmission / reception data, and a first transmission / reception shift register provided on an input side of the transmission / reception shift register. Loop switch and a second switch installed on the output side of the transmission / reception shift register.
And switches between the first loop switch and the second loop switch to take in data on the loop path or to send data on the loop path, so that the reliability and the usability are high. A good loop system can be realized.

[0203] In the data transfer device according to the eighth aspect, the switch means is provided on a loop path and switches between a loop-dedicated register capable of outputting input data at the minimum clock timing and a loop-dedicated register. A loop switch, and at least at the time of a loop, the third loop switch is switched so that data is output to the transmission side via the loop dedicated register, so that the effect of minimizing the delay at the time of the loop can be obtained. Can be.

According to a ninth aspect of the present invention, there is provided the data transfer device, further comprising a contact input port for inputting a contact signal, wherein the contact input port calculates an effective number corresponding to a pulse width of the contact longer than a predetermined time width. The calculation means and the contact count buffer for storing the effective number calculated by the effective number calculation means are provided, so that a large number of contact signals can be fetched from the outside at an arbitrary timing without fail. The monitoring of the contacts does not take much time, and a large number of contact signals can be captured. Therefore,
Since it takes no time to monitor the contacts, a general-purpose system can be constructed.

In the data transfer device according to the tenth aspect,
Connect the master unit and one or more slave units using a loop line,
A contact monitoring system that connects a master unit to a master and manages contact data of the master unit by the master.Since the master unit and the slave unit are configured by the above-described data transfer device, the responsiveness of the system is good, The number of connectors and cables can be greatly reduced, and inexpensive connectors can be used. Further, for example, since one chip can be formed with 8 bits, a system that is inexpensive in hardware and easy to make in software can be realized.

In the contact monitoring system according to the eleventh aspect, since the loop line is constituted by an optical cable composed of an optical fiber and an optical connector, adverse effects such as noise can be prevented, and installation and maintenance of the system can be simplified. It can be carried out.

In the contact monitoring system according to the twelfth aspect, the master unit receives data and commands from the master,
Since the master unit is configured to perform processing according to the command from the master, the system can be easily changed.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a data transfer device according to a first embodiment to which the present invention has been applied.

FIG. 2 is a diagram showing a configuration of a one-chip microcomputer and a contact monitoring system according to a second embodiment to which the present invention is applied.

FIG. 3 is a block diagram of a contact input port with a built-in noise-cut counter memory of the one-chip microcomputer.

FIG. 4 is a diagram showing an effective area based on a ROM area boundary set register of the one-chip microcomputer.

FIG. 5 is a block diagram showing a configuration of a dedicated high-speed UART of the one-chip microcomputer.

FIG. 6 is a diagram showing a 100-byte transmission / reception buffer and a CRC value table (transmission mode 10) of the one-chip microcomputer.

FIG. 7 is a diagram showing a data string on a line in a transmission mode 10 of the one-chip microcomputer.

FIG. 8 is a diagram showing a format of serial data output from a transmission output pin (TXD) of the one-chip microcomputer.

FIG. 9 is a diagram showing a loop system using a dedicated high-speed UART of the one-chip microcomputer.

FIG. 10 is a diagram showing a loop system using a dedicated high-speed UART of the one-chip microcomputer.

FIG. 11 is a diagram showing a configuration of a one-chip microcomputer and a contact monitoring system according to a third embodiment to which the present invention is applied.

FIG. 12 is a block diagram showing a configuration of a conventional general-purpose UART for explaining the effect of the contact monitoring system.

FIG. 13 is a diagram showing connection by an optical cable using an arc net IC for explaining the effect of the contact monitoring system.

FIG. 14 is a diagram showing a cable connection of a loop by a dedicated high-speed UART of the contact monitoring system.

FIG. 15 is a diagram showing a comparison between transmission signals of an arc net and a dedicated high-speed UART for explaining the effect of the contact monitoring system.

FIG. 16 is a block diagram of a conventional UART.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 transmission buffer, 2 registers (data holding means), 3 loop switch A (switch means), 4 loop switch B (switch means), 5 reception buffer, 6 control unit (control means), 7 transmission output (TXD) Pins, 8 reception input (RXD) pins, 101 chip microcomputer, 11 8-bit CPU core (processor), 12 dedicated high-speed UART (data transfer means),
17 contact input port, 45 small memory (contact count buffer), 52 transmission buffer changeover switch (SW1), 53 100-byte transmission buffer A, 54
100-byte transmission buffer B, 55 transmission buffer switch (SW2), 57 transmission register, 58
Transmission / reception shift register, 63 Loop switch A (SW
5), 64 Loop switch B (SW6), 65 ID
Detector, 66 Transmission mode detector, 67 Receive register, 69 Receive buffer changeover switch A (SW4),
70 100-byte receive buffer A, 71 100-byte receive buffer B, 72 receive buffer switch B
(SW3), 77 Self ID set register, 80 T
XEN pin, 81 transmission output (TXD) pin, 82 reception input (RXD) pin, loop register 200, loop switch C (SW7) 201 (third loop switch)

Claims (12)

[Claims] 1. A data transfer device for transferring serial data, comprising: a loop path for looping reception data as transmission data to a transmission side; and a data holding means installed on the loop path for temporarily storing transmission / reception data. Switching means connected to the data holding means; and switching the switch means to take in data from the data holding means, or send data to the data holding means, or loop received data to the transmission side. And a control means for controlling the data transfer. 2. A data transfer device comprising a data transfer means for performing bit-serial data transfer by a start-stop synchronization method, wherein said data transfer means has an identification code (ID) for identifying itself.
No.), a processing means for reading the identification code and processing only the corresponding data, a loop path capable of constructing a loop system by connecting a plurality of terminals in a loop, A data holding unit that temporarily stores transmission / reception data, a switch unit connected to the data holding unit, and switches the switch unit to take in the data of the data holding unit, or to the data holding unit. Control means for controlling data transmission or looping of received data to the transmission side. 3. The data transfer device according to claim 1, wherein the data holding unit is a transmission / reception shift register capable of receiving serial data as parallel data and outputting the parallel data as serial data. . 4. The apparatus according to claim 1, further comprising a register capable of outputting input data at a minimum clock timing, wherein the received data is looped to the transmission side via the register during a loop. Data transfer device. 5. A transmission buffer for temporarily storing transmission data, and a plurality of reception buffers for temporarily storing reception data, wherein one transmission buffer among the plurality of transmission buffers is provided. Another transmission buffer enables the transmission data to be written during the transmission operation, and among the plurality of reception buffers, one reception buffer allows the other reception buffer to be readable during the reception operation. The data transfer device according to claim 1 or 2, wherein 6. The data transfer device according to claim 1, wherein said switch means includes at least one switch provided on said loop path. 7. The transmission / reception shift register provided on the loop path and temporarily storing transmission / reception data, a first loop switch provided on an input side of the transmission / reception shift register, And a second loop switch provided on the output side of the transmission / reception shift register, wherein the first loop switch and the second loop switch are switched to take in data on the loop path or data on the loop path. 7. The data transfer device according to claim 1, wherein the data transfer device transmits the data. 8. The switch device further comprises: a loop-dedicated register installed on the loop path and capable of outputting input data at a minimum clock timing; and a third loop switch for switching the loop-dedicated register. 8. The data transfer according to claim 1, wherein at least at the time of a loop, the third loop switch is switched to output data to the transmission side via the loop dedicated register. apparatus. 9. The data transfer device according to claim 1, further comprising a contact input port for inputting a contact signal, wherein the contact input port is effective according to a pulse width of the contact longer than a predetermined time width. A data transfer device comprising: an effective count calculating means for calculating the number of times; and a contact count buffer for storing the number of effective times calculated by the effective number of times calculating means. 10. A contact monitoring system in which a master unit and one or more slave units are connected by using a loop line, the master unit is connected to a master, and contact data of the master unit is managed by the master. A contact monitoring system, wherein the master unit and the slave unit are configured by the data transfer device according to any one of claims 1 to 9. 11. The contact monitoring system according to claim 10, wherein the loop line is an optical cable including an optical fiber and an optical connector. 12. The contact monitoring according to claim 10, wherein the master unit receives data and a command from the master, and the master unit performs a process according to the command from the master. system.