JPH10271103A - Reception controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily synchronize the frames of received data and to easily establish reception. SOLUTION: The frame synchronizing signal of received data is supplied to a shift register 1, and the data pattern of the frame synchronizing signal is compared with the frame synchronizing signal from the shift register by a comparator 2. An adder circuit 3 performs adding processing while defining a compared output in the case of non-coincidence between the both as a bit error and supplies this result to a decoder 4. Allowable range data showing the allowable range of bit error are supplied through terminals F1 and F0 to the decoder 4, it is detected whether the bit error generated at the time of added output from the adder circuit 3 is settled within the allowable range or not and this result is supplied to a microcomputer. When the detected result showing this bit error is settled within the allowable range is supplied, the microcomputer spriously synchronizes frames and establishes the reception.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reception control apparatus suitable for use in a receiver of a low power data communication system such as a spread spectrum radio, and more particularly, to a method for reducing a bit error in a frame synchronization signal on the receiver side. The present invention relates to a reception control device that facilitates reception by accepting and synchronizing frames.

[0002]

2. Description of the Related Art Conventionally, a receiver provided in a low power data communication system, such as a spread spectrum radio, detects a frame synchronization signal from signals transmitted by serial communication based on data input and clock input. It employs a synchronization detection method that achieves frame synchronization.

[0003] Specifically, when receiving data, the receiver supplies the data to a reception control device. The reception control device stores a frame synchronization signal having a data pattern defined by a communication protocol.
Check each time a bit is input. Then, this collation operation is repeated until the frame synchronization signal and the received data all match without error, and when they match, frame synchronization is established and reception is established.

[0004]

However, the reception control device provided in the conventional receiver repeats the collation operation between the frame synchronization signal and the received data until the two completely match. Therefore, if there is at least one error in the frame synchronization signal of the received data, the reception is not established because the frame synchronization signal is not detected, and is transmitted next to the frame synchronization signal. There was a problem that could not be received. This problem is particularly noticeable when the communication path is noisy.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and provides an allowable range of a certain bit error in a collation operation between a frame synchronization signal and received data to achieve pseudo frame synchronization. It is another object of the present invention to provide a reception control device that can easily establish reception.

[0006]

A reception control apparatus according to the present invention comprises: a bit error detection means for detecting the number of bit errors in a frame synchronization signal transmitted from a transmitter to solve the above-mentioned problems; An allowable range setting means for setting an allowable range of the number of bit errors of the frame synchronization signal detected by the bit error detection means, and the number of bit errors of the frame synchronization signal detected by the bit error detection means, A frame synchronizing unit that establishes frame synchronization and establishes reception when the frequency is within the allowable range set by the allowable range setting unit.

When the number of bit errors of the frame synchronization signal detected by the bit error detection means is within the allowable range of the number of bit errors set by the allowable range setting means, the frame synchronization means: The reception is established with frame synchronization.

Thus, even when the communication path is noisy, for example, frame synchronization can be simulated in accordance with the allowable range of the number of variable bit errors, and reception is established. Can be made easier.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of a reception control device according to the present invention will be described below in detail with reference to the drawings.

A reception control device according to an embodiment of the present invention is, as shown in FIG. 1, a shift register 1 for outputting a frame synchronization signal extracted from received data on a bit-by-bit basis, and is defined by a communication protocol. A comparator 2 for comparing (collating) the frame synchronization signal with the frame synchronization signal from the shift register 1 on a bit-by-bit basis, and an addition circuit 3 for adding the comparison result.

Further, the reception control device includes an F0 terminal and an F1 terminal to which allowable range data indicating an allowable range of a bit error of the frame synchronization signal is supplied, an addition output from the adder circuit 3, and an F0 terminal and an F1 terminal. And a decoder 4 for comparing the data with the permissible range data supplied thereto and outputting the comparison result.

Such a reception control device can be provided as the signal detection unit 13 of the receiver shown in FIG.

The receiver includes an antenna 11 for receiving data transmitted from the transmitter, a radio unit 12 for receiving the data received by the antenna 11, and a frame synchronization signal from the data from the radio unit 12. And a data buffer 17 for temporarily storing received data and outputting it at a predetermined bit rate. Have been.

The control unit 15 supplies a signal detection unit 13 having the configuration shown in FIG. 1 and a frame synchronization signal defined by a communication protocol to the comparator 2 of the signal detection unit 13.
It comprises a microcomputer (microcomputer) 14 that supplies allowable range data to the decoder 4 via the F0 terminal and the F1 terminal and establishes communication by establishing frame synchronization based on the detection result from the decoder 4.

Data received by such a receiver (data transmitted from the transmitter side) is, for example, as shown in FIG.
It has a communication data format based on the Radio Law Enforcement Regulations composed of a 1-bit frame synchronization signal, a 63-bit calling signal, and data. The data pattern of the 31-bit frame synchronization signal is, for example, “0001
101110101000010010110011111 ". The microcomputer 14 stores the data pattern of the frame synchronization signal in advance.

Next, the operation of the reception control device and the receiver having such a configuration will be described.

First, when data of each frame including a bit synchronization signal, a frame synchronization signal, a calling signal and data as shown in FIG. 3 is transmitted from the transmitter side, the antenna 11 of the receiver shown in FIG. This data is received and supplied to the radio unit 12.

The radio unit 12 takes in the received data and supplies it to the signal detection unit 13 of the control unit 15.

As described above, the signal detection unit 13 employs the reception control device having the configuration shown in FIG. 1, and among the data fetched by the radio unit 12, a 31-bit frame synchronization signal is Shift register 1 shown in FIG.
Supplied to

When supplied with the frame synchronization signal, the shift register 1 temporarily stores the frame synchronization signal and supplies it to the comparator 2 bit by bit.

The comparator 2 is supplied with a data pattern of the frame synchronization signal from the microcomputer 14 separately from the received frame synchronization signal. The comparator 2 compares the frame synchronization signal supplied from the shift register 1 with the data pattern of the frame synchronization signal supplied from the microcomputer 14 bit by bit, and outputs a "0" comparison output when they match. If they do not match, the comparison output of "1" is supplied to the addition circuit 3. As a result, the 31-bit comparison output is supplied to the addition circuit 3.

The adder circuit 3 is, for example, a 5-bit adder circuit, performs an addition process on the 31-bit comparison output from the comparator 2, and supplies this addition output to the decoder 4.

Specifically, as described above, the comparator 2
Compares the received frame synchronizing signal with the data pattern of the frame synchronizing signal from the microcomputer 14, and outputs a comparison output of "0" when both match, and "1" when they do not match. Is output. For this reason, when this comparison output is added by the addition circuit 3, when both of them match, “0000” is obtained.
An addition output of “0” is obtained, and when there is a 1-bit error, an addition output of “00001” is obtained. Similarly, when there is a 2-bit bit error, an addition output of “00010” is obtained, and when there is a 4-bit bit error, an addition output of “00100” is obtained. (When all are bit errors), an added output of "11111" is obtained.

Here, the receiver can set an allowable range of bit errors (mismatch) between the received frame synchronization signal and the data pattern of the frame synchronization signal from the microcomputer 14.

More specifically, as shown in FIG. 4, the allowable range of the two bit errors can be arbitrarily set from a 1-bit bit error to a 4-bit bit error. Is set as an allowable range, low-level (L) allowable range data is supplied to the F1 terminal and the F0 terminal shown in FIG. When a 2-bit bit error is set as an allowable range, low-level allowable range data is supplied to the F1 terminal, and high-level (H) allowable range data is supplied to the F0 terminal. If the error was set as acceptable,
The high-level allowable range data is supplied to the F1 terminal, and the low-level allowable range data is supplied to the F0 terminal. Further, when a 4-bit bit error is set as an allowable range, high-level allowable range data is supplied to the F1 terminal and the F0 terminal, respectively. This F1
The permissible range data supplied via the terminal and the F0 terminal is supplied to the decoder 4 shown in FIG.

The decoder 4 detects the permissible range of the bit error based on the permissible range data supplied via the F1 terminal and the F0 terminal. It detects whether it is within the allowable range. Then, the detection result is supplied to the microcomputer 14 shown in FIG.

If the detection result indicating that the total number of the bit errors is equal to or larger than the set allowable range of the bit error is supplied from the decoder 4, the microcomputer 14 does not establish the reception, and When a detection result indicating that the total number is within the set allowable range of the bit error is supplied from the decoder 4, the reception is established as that the frame synchronization has been achieved. When frame synchronization is established, the received data is temporarily stored in a data buffer, and supplied to an external device connected to the external connection unit 16 at a predetermined bit rate.

As is apparent from the above description, the receiver (and the reception control device) sets the allowable range of the bit error of the frame synchronization signal in advance, and determines the actually generated bit error according to the set allowable range. If it is within the range, pseudo frame synchronization is established to establish reception. Therefore, even when there is a lot of noise in the communication path, frame synchronization can be easily achieved, and reception can be easily established. Further, based on the detection result from the decoder 4, it is possible to determine whether or not the actually generated bit error exceeds a set allowable range. The state may be detectable.

Finally, in the above description of the embodiment, the frame synchronization signal transmitted from the transmitter side is 31 bits, the addition circuit 3 performs addition processing of 5 bits, and the allowable range of the bit error is Although specific numerical values have been set such that up to 4 bits can be set, this is only an example, and the present invention is applied to a case where the allowable range of a bit error is set to 5 bits or 6 bits. Needless to say, various changes can be made in accordance with the design, the standard, and the like within a range not departing from the technical idea according to the above.

[0030]

The reception control device according to the present invention can easily establish frame synchronization even when there is a lot of noise in a communication path, and can easily establish reception.

[Brief description of the drawings]

FIG. 1 is a block diagram of a reception control device according to an embodiment of the present invention.

FIG. 2 is a block diagram of a receiver to which the reception control device according to the embodiment is applied.

FIG. 3 is a diagram illustrating an example of data for one frame transmitted from a transmitter.

FIG. 4 is a diagram for explaining an allowable range of a bit error of a frame synchronization signal set by a microcomputer provided in the receiver.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Shift register 2 Comparator 3 Addition circuit 4 Decoder 13 Signal detection part 14 Microcomputer (microcomputer) 15 Control part 17 Data buffer

Claims (2)

[Claims] 1. A bit error detecting means for detecting the number of bit errors of a frame synchronization signal transmitted from a transmitter, and an allowable range of the number of bit errors of the frame synchronization signal detected by the bit error detecting means. An allowable range setting unit for setting, and when the number of bit errors of the frame synchronization signal detected by the bit error detecting unit is within an allowable range set by the allowable range setting unit, the frame synchronization is performed and reception is performed. And a frame synchronization means for establishing the following. 2. A comparing means for comparing a frame synchronization signal transmitted from a transmitter with a data pattern of a frame synchronization signal stored in advance for each predetermined bit to detect a bit error. 2. The reception control device according to claim 1, further comprising: addition means for adding a bit error each time a bit error is detected by the comparing means to detect the number of bit errors.