JPH10271080A - Digital signal transmitter and receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a digital signal transmitter and receiver in which a transmitter side can control selection or revision of hardware circuits of the receiver. SOLUTION: A video signal and an audio signal subject to compression encoding by encoders 001, 011 are buffered tentatively with hardware configuration information by FIFO memories 002, 012, 021, packet processing circuits 003, 013, 0022 apply packet processing and the result is stored in memories 004, 014, 023. On the other hand, a PMT(program map table) generating circuit 031 sets PMT describing PID(packet ID) or the like of the video signal, the audio signal and the hardware configuration information into a packet, a packet multiplex controller 030 reads the data stored in the memories 004, 014, 023 as a time multiplex signal in the unit of packets in matching with video/audio encoding speeds, applies time multiplexing to the data with other sets of time multiplex signals and the result is outputted from a terminal 056 as a bit stream signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal transmitting apparatus and a digital signal transmitting apparatus used for broadcasting or communicating digital signals.

[0002]

2. Description of the Related Art In recent years, digital signal processing technology for video and audio has remarkably advanced, and digital broadcasting,
Systems are being actively developed around the world to realize the integration of broadcasting and communications.

[0003] Among these, one of the most important technologies is video / video.
This is audio compression technology. This compression technology is MPEG, J
PEG, H.P. 261 was the main place, but ISO / I
EC13818-1 (Moving Picture Coding Experts
Group (ISO / IEC JTC1 / SC29 / WG1
The method proposed in 1)) is being studied for global standardization of broadcasting, communication, and storage media.

[0004] ISO / IEC13818-1 uses not only a video compression system but also a transmitting apparatus to multiplex and broadcast a bit stream compressed for each video, audio and data of a program, and to transmit a designated program to a receiving apparatus. The system for the control part for receiving is also fixed.

[0005] The multiplex control of the bit stream for broadcasting and communication according to ISO / IEC13818-1 has the following configuration. FIG. 12 shows a model of one video system and one audio system for the packet method. First, both video and audio are divided into units of one frame,
A PES (Packetized Elementar)
y Stream). This PES is of variable length.

Further, in order to time-multiplex video and audio, each PES is basically divided into 184 bytes and packetized, and each video packet (PID
= V) and 4b for audio packets (PID = A)
188 byte TP (Tran
sport Stream Packet). This TP has a fixed length.

[0007] A bundle of several PESs according to the above configuration is attached to a header to make one pack (Pack), and each pack is time-multiplexed to form a program stream (Program Std).
ream).

In FIG. 12, video and audio are multiplexed. However, in practice, data such as additional data of a program and program information are also TP-converted and time-multiplexed. FIG. 13 illustrates a method of configuring a bit stream as a broadcast.

A program A shown in the figure shows one program, and in the case of FIG. 13, two video systems, two audio systems,
One system of data and one system of a program map table (PMT) are multiplexed.
Here, video 1 and 2, audio 1 and 2, data 1
Indicates video data, audio data, and additional information data, respectively, and the PMT includes a packet I for distinguishing between the video data, audio data, and additional information data.
D (PID: Packet ID) and technologies related to programs are described.

The first case will be described. As shown in FIG. 13, various programs are time-multiplexed in a transport stream (TS: Transport Stream) corresponding to transmission channel data. On the receiving device side, the video data, The voice data and the additional information data are identified.

Furthermore, the transport stream shown in FIG. 13 is transmitted after being subjected to scramble processing for each broadcaster or each program. The scramble processing method is determined by the broadcaster or in an extreme case. May vary by program. Therefore, on the receiving device side, a descrambling circuit corresponding to each broadcaster or each program is required to perform the descrambling process on the program. However, this requires a plurality of descrambling circuits.

The second case will be described. At present, the home electronic devices we use are improving day by day, and it is common to upgrade parts by replacing various parts like personal computers. We are in the process of replacing new parts.

[0013]

As described above, in the first case, when the scramble processing methods used on the transmitting side are different, corresponding descrambling circuits are required, and the receiving device requires The configuration becomes complicated. In the second case, when replacing a new part,
The solution depends considerably on whether the component is a socket or not, but it is impossible to support all components with sockets.

Therefore, conventionally, in a digital broadcasting system or a digital communication system, the switching or change of the hardware circuit of the receiving apparatus can be controlled from the transmitting side without the user of the receiving apparatus modifying the apparatus. Is strongly desired.

An object of the present invention is to solve the above-mentioned problems and to provide a digital signal transmitting apparatus and a receiving apparatus which can control switching or change of a hardware circuit of a receiving apparatus from a transmitting side.

[0016]

Means for Solving the Problems In order to achieve the above object, the present invention is configured as follows. (1) In the digital signal transmitting apparatus, the wiring of the hardware is specified in the transmission signal to the digital signal receiving apparatus having the hardware capable of rearranging the wiring of the gate array based on the given configuration information. Multiplexing hardware configuration information to be performed.

(2) In the configuration of (1), hardware switching information for switching from the existing hardware configuration information to the multiplexed hardware configuration information in the digital signal receiving apparatus is further included in the transmission signal. Multiplex.

(3) In the configuration of (1), further, hardware switching information for selectively switching between existing hardware configuration information and the multiplex-transmitted hardware configuration information in the digital signal receiving apparatus is further provided. The transmission signal is multiplexed.

(4) In the configuration of (1), the hardware configuration information is compressed by a reversible compression method and multiplexed. (5) In the digital signal receiving apparatus, the hardware capable of rearranging the wiring of the gate array based on the given configuration information and the wiring multiplexed on the transmission signal from the transmitting side to designate the wiring of the hardware Hardware configuration information storing means for downloading and storing hardware configuration information to be transmitted from a transmission signal, and hardware control means for rearranging the hardware wiring based on the hardware configuration information stored in the means.

(6) In the configuration of (5), the hardware control means is multiplexed with the transmission signal and is hardware switching information for switching from existing hardware configuration information to the downloaded hardware configuration information. From the transmission signal, and switches the wiring of the hardware to the wiring corresponding to the downloaded information based on the received information.

(7) In the configuration of (5), the hardware configuration information storage means stores the existing hardware configuration information and the downloaded hardware configuration information, and the hardware control means stores the existing hardware configuration information. Receiving hardware switching information from the transmission signal to select one of the hardware configuration information and the downloaded hardware configuration information; and, based on the received information, any hardware switching information from the hardware configuration information storage unit. The configuration information is taken out and the hardware wiring is selectively switched.

(8) In the configuration of (5), programmable logic modules are regularly arranged in the hardware, a wiring area is prepared between them, and the logic module and the wiring area are connected according to the program. In this case, a field programmable gate array that realizes a desired logic is used.

(9) In the configuration of (5), the hardware is a descrambler for descrambling the transmission signal, and the hardware control means transmits hardware configuration information corresponding to the scramble method. To switch the wiring of the descrambler.

(10) In the configuration of (5), the hardware is a system clock generation circuit for generating a system clock of the present apparatus, and the hardware control means includes a hardware corresponding to the version upgrade of the system clock. The wiring of the system clock generation circuit is switched based on the hardware configuration information.

(11) In the configuration of (5), when the hardware configuration information to be multiplexed on the transmission signal is compressed by a reversible compression method, the hardware control unit executes the downloaded hardware configuration information. Expand and execute.

That is, the digital signal transmitting apparatus and the receiving apparatus according to the present invention have a function of changing or updating hardware based on information given to the receiving apparatus. By transmitting hardware circuit information and circuit change information for changing or updating the hardware, the hardware is automatically changed or updated based on the information sent on the receiving device side.

In particular, based on the protocol of ISO / IEC13818-1, hardware circuit information, and in some cases, hardware change information is broadcasted or communicated, and the receiving side receives and downloads the hardware circuit information. Then, in some cases, hardware change information is received, and the hardware is updated based on the downloaded hardware information. Alternatively, the downloaded information and the initial circuit information are held, and the circuit information is changed based on separately sent hardware change information to correspond to various services.

[0028]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to FIGS. (First Embodiment) As a first embodiment according to the present invention, a transmitting apparatus and a receiving apparatus in the case of multiplex broadcasting of hardware configuration information in a digital broadcasting system will be described.

FIG. 1 shows the configuration of a transmission apparatus according to the present embodiment. A video signal is input from a terminal 000 and compression-encoded by a video encoder 001. The compression-encoded video data is input to a FIFO memory 002 and temporarily buffered, and then packetized into a packet specified by the system layer of ISO / IEC13818-1 in a packetization circuit 003 and stored in a memory. 004.

Similarly, an audio signal is also input from a terminal 010, compression-encoded by an audio encoder 011 and input to a FIFO memory 012 and temporarily buffered. And input to the memory 014.

Further, the hardware configuration information includes terminal 0
20 and directly to the FIFO memory 21. This information may be subjected to lossless compression in advance. The hardware configuration information output from the FIFO memory 021 is packetized by the packetization circuit 022, and the packetization process performed at this time uses a section format. The packetized data is input to the memory 023.

On the other hand, the PMT generation circuit 031 sets the PMT describing the video signal, the audio signal, the PID of the hardware configuration information, and the like, and the PMT signal is packetized similarly to the video and audio signals.

The packetized signal thus obtained is
The packet multiplexing controller 030 reads out a time multiplexed signal from the memory 004 and the memory 014 in packet units in accordance with the video and audio encoding speeds (depending on the occupation amount of the memories 004 and 014). At this time, the hardware configuration information is also multiplexed as necessary (specifically, version upgrade, etc.), and the PMT generation circuit 0
The PMT packetized signal obtained from 31 is also time-multiplexed as needed.

As described above, a signal obtained by time-multiplexing a set of a video signal, an audio signal, hardware configuration information, and a PMT signal is input to the memory 050. The processing of one set of video, audio, hardware configuration information, and PMT is performed as described above, but the other sets of signals are also processed in the same manner with a time difference, and the memories 051, 052,
053.

In the PAT generation circuit 054, a PAT is generated and packetized. The total packet multiplexing controller 055 detects the occupation amount of each of the memories 050, 051, 052, and 053, and
For 0, 051, 052, and 053, signals are output in packet units to the extent that overflow or underflow does not occur. At this time, the packetized signal obtained from the PAT generation circuit 054 is also time-multiplexed as necessary.

The bit stream signal packetized as described above is output from a terminal 056 and broadcast through an error correction circuit and a modulation circuit (not shown). FIG. 2 shows a configuration of a receiving apparatus for receiving a broadcast signal from the transmitting apparatus having the above configuration in the present embodiment.
0 is received by the demodulation circuit 101 including the tuner.
Demodulation processing is performed in the error correction circuit (FEC) 1
In 02, error correction is performed. The signal obtained from the FEC 102 is a packetized bit stream. This bit stream signal is input to the descrambler 103, and the descrambled signal is subjected to descrambling processing.

At this time, the signal subjected to the descrambler processing is stored in the memory 104. At this time, CPU1
07 obtains the PIDs of the video signal and the audio signal by analyzing the input signal and decoding the PMT indicated in the table.

The video signal whose PID has been acquired is input to the video decoder 105, and the audio signal is input to the audio decoder 106. The decoded video signal is transmitted to the NTSC encoder 10
8 and is converted into an NTSC signal.
Is converted into an analog signal, reaches the monitor 112, and is displayed on the screen. On the other hand, the audio signal for which the PID has been acquired is decoded by the audio decoder 106, converted into an analog signal by the D / A conversion circuit 111, and reproduced by the speaker 113.

Here, it is assumed that the scramble method is updated in the descrambling process.
In this case, the CPU 107 downloads the hardware configuration information sent from the transmission device as needed to the memory or the hard disk 109, and updates the descrambler 103 after the download is completed.

The descrambler 103 is an FPGA (Field Programmable Gate Array).
able gatearray): A device that regularly arranges programmable logic modules, prepares a wiring area between them, and connects the logic module and the wiring area according to the program to achieve the desired logic The condition is that the configuration is possible.

If the transmitted hardware configuration information is compressed in a reciprocal manner, the compression is released by the CPU 107 and then the descrambler 1 is decompressed based on the information.
03 is updated. Also, in the present embodiment, the descrambler has been described as an example of an object to be updated by the hardware configuration information, but it is of course possible to update another hardware configuration.

(Second Embodiment) Next, as a second embodiment according to the present invention, a transmitting apparatus and a receiving apparatus for transmitting and receiving hardware switching information in addition to hardware configuration information in a digital broadcasting system Will be described.

FIG. 3 shows the configuration of the transmitting apparatus according to the present embodiment. However, in FIG. 3, the same parts as those in FIG. 1 are denoted by the same reference numerals, and different parts will be described here.

First, the video signal and the audio signal are the same as in the first embodiment. Hardware configuration information
The data is input from the terminal 020 and input directly to the FIFO memory 021. However, the difference from the first embodiment is that transmission is performed at a constant or almost constant rate as a program-specific one, not when necessary. It is in the point that is.

The hardware configuration information output from the FIFO memory 021 is packetized by the packetization circuit 022, and the packetization process performed at this time uses a section format. The packetized data is input to the memory 223.

The hardware switching information is input from the terminal 200 and is directly input to the FIFO memory 201. This information is different from the hardware configuration information and is information having time information. . Specifically, P
The information becomes ES format information, and is packetized by the packetizing circuit 202 in accordance with the broadcast time similarly to the video signal and the audio signal, and is input to the memory 203.

The subsequent encoding operation is the same as in the first embodiment, and will not be described. FIG. 4 shows a configuration of a receiving apparatus that receives a broadcast signal from the transmitting apparatus having the above configuration in the present embodiment. In FIG. 4, the same parts as those in FIG. 2 are denoted by the same reference numerals, and different parts will be described here.

In the present embodiment, the bit stream is input to the descrambler 103, scrambled and stored in the memory 104, and the CPU 107 analyzes the input signal, and first watches the program specified by the user. The PID required for the video signal and the PID of the video signal and the audio signal are obtained by decoding the PMT necessary for the decoding. Subsequent processing of the video signal and the audio signal for which the PID has been acquired is the same as in the first embodiment.

Here, in the above descrambling process, it is assumed that the scramble method differs for each transmitted program. In this case, the CPU 107 downloads the hardware configuration information for each program sent from the encoder to the memory or the hard disk 109, decodes the hardware configuration information, and simultaneously receives the hardware switching information.
Based on the hardware switching information, the descrambler 103
Switch.

Also in this embodiment, the descrambler 1
03 is a condition that it is a rewritable configuration such as an FPGA. If the transmitted hardware configuration information is reversibly compressed, the compression is released and the descrambler 103 is switched based on the information.
In addition, it is also possible to switch not only the descrambler but also another hardware configuration.

Next, in the descrambling process,
It is assumed that the scrambling method is different for each channel (broadcasting company). In this case, the CPU 107 downloads the hardware configuration information for each program sent from the encoder to the memory 109, decodes the hardware configuration information, stores the hardware configuration information in the memory or the hard disk 109, and simultaneously receives the hardware switching information. The descrambler 103 is switched based on the hardware switching information.

At this time, the reason that the hardware configuration information is stored in the memory or the hard disk 109 is that the user changes the channel using the remote
4 transmits the information to the CPU 107, and when the channel before switching and the channel after switching are different, the information held in the memory or the hard disk 109 is read every time the channel switching occurs, and the descrambler is read. This is because the processing time is shorter when 103 is rewritten. This method is more effective when the hardware configuration information has been subjected to lossless compression.

However, rewriting of the descrambler (or other hardware) uses a method (circuit) different from the descrambling method (circuit) used by the channel that the user has selected for viewing previously. However, the timing is required when the information of the new channel is prepared as described above.

In other words, switching when information has been obtained in advance (determined by whether or not the user has previously viewed this channel) occurs when the user changes the channel with a remote controller or the like, and conversely. If the information has not been acquired in advance, it is necessary to acquire new descrambling information, so that the switching occurs after the receiving device completes acquiring the information.

(Third Embodiment) As a third embodiment according to the present invention, a transmitting apparatus and a receiving apparatus for communicating hardware configuration information in a digital communication system will be described.

FIG. 5 shows a configuration of a transmitting apparatus on the server side according to the present embodiment. A video signal is input from a terminal 300 and compression-encoded by a video encoder 301. The compressed and encoded video data is packetized into a packet defined by the system layer of ISO / IEC13818-1 in the FIFO memory 302 and sent to the memory 304.

Similarly, an audio signal is also input from a terminal 310, compression-encoded by an audio encoder 311, input to a FIFO memory 312, and temporarily buffered, and then transmitted to a packetization circuit 313 in the same manner as a video signal. And input to the memory 314.

Further, the hardware configuration information is stored in the terminal 3
20 and directly to the FIFO memory 321. This information may be subjected to lossless compression in advance. The hardware configuration information output from the FIFO memory 321 is packetized by the packetization circuit 322, and the packetization process performed at this time uses a section format. The packetized data is input to the memory 323.

The packetized signal generated in this manner is converted into an image,
In accordance with the audio encoding speed (memory 304 and 31
4 is read out from the memory 304 and the memory 314 as a time-multiplexed signal in packet units. At this time, the hardware configuration information is also multiplexed as needed (specifically, when upgrading, for example). The set of video signal, audio signal, and time multiplexed signal of the hardware configuration information thus generated are filed in the database 331 as one program.

Although the encoding method for one program has been described here, the database 331 stores a plurality of encoded programs. This database 33
1 is output from a terminal 332 and transmitted through an error correction circuit and a modulation circuit (not shown).

FIG. 6 shows a configuration of a receiving apparatus for receiving a transmission signal from the transmitting apparatus having the above configuration in the present embodiment. The signal input from the terminal 400 is a packetized bit stream. . This bit stream is input to the descrambler 402. At this time, the CPU 403 analyzes the header of each packet, and performs descramble processing only on the scrambled signal of the video signal and audio signal of each packet input to the descrambler 402.

The video signal and the audio signal that have been descrambled by the descrambler 402 in this manner are input to the video signal decoder 404 and the audio decoder 405, respectively. The decoded video signal is input to the NTSC encoder 406, converted to an analog signal by the D / A conversion circuit 407, and reaches the monitor 411. On the other hand, the audio signal is decoded by an audio decoder 405, converted into an analog signal by a D / A conversion circuit 407, and
Sound is reproduced.

Here, in the descrambling process, it is assumed that the scrambling method is changed for each service. In this case, the hardware configuration information multiplexed from the transmitting device serving as a server as necessary
U403 downloads to the memory or the hard disk 409, and after the download is completed, the descrambler 402
Make changes.

The condition is that the descrambler circuit 402 has a rewritable configuration such as an FPGA. If the sent hardware configuration information is reversibly compressed, the CPU 403 decompresses the data and changes the descrambler 402 based on the information.

In the present embodiment, a change in the circuit configuration of the descrambler has been described as an example, but it is of course possible to update another hardware configuration. Changing the server to be accessed is performed through the keyboard 410.

(Fourth Embodiment) Next, as a fourth embodiment according to the present invention, a receiving apparatus for transmitting and receiving hardware switching information in addition to hardware circuit information in a digital broadcasting system. explain.
Note that the transmitting device in this case is the same as that of the second embodiment, and a description thereof will be omitted.

FIG. 7 shows the configuration of a receiving apparatus for receiving a broadcast signal from a transmitting apparatus similar to the transmitting apparatus of the second embodiment in this embodiment. However, in FIG. 7, the same parts as those in FIG. 4 are denoted by the same reference numerals.

In FIG. 7, a received signal input from a terminal 100 is subjected to demodulation processing in a tuner 101 and error correction is performed in an error correction circuit (FEC) 102. The signal obtained from the FEC 102 is a packetized bit stream. This bitstream is
The descrambled signal is input to the descrambler 103 and descrambled.

At this time, the signal descrambled by the descrambler 103 is stored in the memory 104.
At this time, the CPU 107 analyzes the input signal and
First, the PAT necessary for viewing the program specified by the user is decoded, and the PM shown in the table is decoded.
By decoding T, PIDs of the video signal and the audio signal are obtained.

The video signal whose PID has been obtained in this manner is input to the video decoder 105, and the audio signal is input to the audio decoder 106. The video signal decoded by the video decoder 105 is input to the NTSC encoder 108, converted into an analog signal by the D / A conversion circuit 110, and reaches the monitor 112. On the other hand, the audio signal decoded by the audio decoder 106 is converted into an analog signal by the D / A conversion circuit 111 and is reproduced from the speaker 113 as sound.

Here, in the second embodiment, the description has been made focusing on the descrambler process. However, the present embodiment is characterized in that a clock switching circuit 116 is added. The clock switching circuit 116 must have a switchable configuration such as an FPGA.

The CPU 107 downloads the hardware configuration information sent from the encoder to the memory or the hard disk 109 and decodes it. When the hardware switching information is received, the CPU 107 reads the hardware or the hard disk 109 based on the hardware switching information. The version of the clock switching circuit 116 is upgraded based on the hardware configuration information stored in the.

Here, when the hardware configuration information sent is reversibly compressed, the CPU 107 decompresses the data and updates the clock switching circuit 116 based on the information. At this time, the version upgrade means an increase in the frequency of the system clock supplied to improve the processing speed of the video decoder and the audio decoder.

At this time, the reason that the hardware configuration information is stored in the memory or the hard disk 109 is that the user changes the channel using the remote
4 transmits the information to the CPU 107, and when the clock frequency of the channel before the switching is different from the clock frequency of the channel after the switching, the information stored in the memory or the hard disk 109 is read every time the channel switching occurs, and the clock switching is performed. This is because the processing time is shorter when the circuit 116 is rewritten. This method is more effective when the hardware configuration information has been subjected to lossless compression.

However, the above hardware rewriting is necessary when the channel selected by the user uses a clock frequency different from the clock frequency used by the previously watched channel. It will be implemented when new channel information is available.

That is, switching when information has been obtained in advance (determined by whether or not the user has previously viewed this channel) occurs when the user changes the channel with a remote controller or the like, and conversely. If the information has not been acquired in advance, it is necessary to acquire new clock information, so that the switching occurs after the receiving device completes acquiring the information.

(Fifth Embodiment) Next, as a fifth embodiment according to the present invention, a receiving apparatus for transmitting and receiving hardware switching information in addition to hardware circuit information in a digital communication system. explain.
Note that the transmitting device in this case is the same as that of the third embodiment, and the description thereof is omitted.

FIG. 8 shows a configuration of a receiving apparatus for receiving a transmission signal from a transmitting apparatus similar to the transmitting apparatus of the third embodiment in this embodiment. However, in FIG. 8, the same parts as those in FIG. 6 are denoted by the same reference numerals.

In FIG. 8, a signal input from a terminal 400 is a packetized bit stream, and this bit stream is input to a descrambler 402. At this time, the header of each packet of the CPU is analyzed, and among the video signal and the audio signal of each packet input to the descrambler 402, only the scrambled signal is descrambled.

The video signal and the audio signal that have been descrambled by the descrambler 402 in this manner are input to the video signal decoder 404 and the audio decoder 405, respectively. The decoded video signal is input to the NTSC encoder 406, converted to an analog signal by the D / A conversion circuit 407, and reaches the monitor 411. On the other hand, the audio signal is decoded by an audio decoder 405, converted into an analog signal by a D / A conversion circuit 407, and
Sound is reproduced.

Here, in the third embodiment, the description has been made focusing on the descrambler process, but the present embodiment is characterized in that a clock supply circuit 413 is added. The clock supply circuit 413 is required to have a switchable configuration such as an FPGA.

The CPU 403 downloads the hardware configuration information sent from the encoder to the memory or the hard disk 409 and decodes it. When the hardware switching information is received, the CPU 403 uses the hardware or hard disk 409 based on the hardware switching information. The version of the clock supply circuit 413 is upgraded based on the hardware configuration information stored in the.

Here, if the hardware configuration information sent is reversibly compressed, the CPU 403 releases the compression and then updates the clock supply circuit 413 based on the information. At this time, the version upgrade means an increase in the frequency of the system clock supplied to improve the processing speed of the video decoder and the audio decoder.

In this embodiment, a change in the configuration of the clock supply circuit has been described as an example. However, it is of course possible to update another hardware configuration. Changing the server to be accessed is performed through the keyboard 410.

(Embodiment) The hardware of the digital signal receiving apparatus according to the present invention will now be described as 12.2-1.
2.75 GHz satellite digital broadcasting system (Refer to the 1995 Telecommunications Technology Council Report, Advisory No. 74)
In the following, a description will be given of a case where the scrambler is configured using an FPGA, as an example.

First, the scramble algorithm is based on the CBC according to the block cipher system (ISO9979 / 009).
Mode and OFB mode. FIG. 9 shows an outline of this algorithm.

In FIG. 9, reference numeral 501 denotes a CBC mode processing circuit, 502 denotes an OFB mode processing circuit, and 503 denotes TS (transport stream) data before encryption in a CBC / OFB mode processing circuit 50 in units of a block length of 8.
A switch for sorting to 1,502, 504 is CBC, O
A switch for taking out the processing outputs of the processing circuits 501 and 502 in the FB mode and outputting them as encrypted TS data.

The CBC mode processing circuit 501 inputs the input data to a two-block multi-encryption processing unit (MULTI2) A2 via an adder A1, and performs an encryption process by a block encryption method based on 64 bits of a key. This is based on a feedback system in which a register (REG) A3 delays by a fixed time and adds the input data to an adder A1.

The OFB mode processing circuit 502 uses a two-block multi-encryption processing unit (MULTI2) B1
A feed in which an encryption process is performed by a block encryption method on the basis of 4 bits, the output of which is delayed for a predetermined time by a register (REG) B2 and returned to an encryption processing unit B1, and simultaneously added to input data by an adder B3. According to the forward method.

That is, a block cipher system has been adopted worldwide as an algorithm of the cipher system.
This is because, in general, the arrangement of bits is not fixed between a plaintext (information to be broadcast) and a ciphertext unlike the PN encryption in the block encryption method, so that the same key is repeatedly used. When using encryption, it is difficult to obtain a clue to decryption, and it is considered that security is high.
This is due to the fact that problems with the hardware scale and processing speed have disappeared due to advances in SI technology.

The layer to be scrambled is the “transport stream layer”. The range is “PSI, E
Payload section excluding the header and adaptation field of the transport stream packet excluding CM and EMM. " The scramble key length is "32 bits or more", and the scramble speed is 37 Mbps or more. The usage period of the same key shall be at least 1 second.

FIG. 10 shows a general structure of a descrambler used for digital broadcasting. In FIG. 10, reference numeral 601 denotes a 15-bit register, in which the same initial value as that of the transmitting side is set in advance. From this register 601, the same bits (the 14th bit and the 15th bit in the figure) as the set of the transmitting side are extracted. These bit outputs are subjected to an exclusive OR operation in an EX-OR (exclusive OR) gate 602 and then to an AND gate 60
3 and simultaneously returned to the input of the register 601.

The AND gate 603 is activated in response to the enable signal and passes the output of the EX-OR gate 602. This gate output is supplied to an EX-OR gate 604, where it is subjected to an exclusive OR operation with the scrambled bit stream and descrambled.

In the descrambler having the above configuration,
When the bit stream scramble method is switched, it is necessary to switch the internal wiring according to the method. Therefore, as shown in FIG. 11, the descramble processing unit is configured using the FPGA 701, and the downloaded hardware configuration information is stored in an electrically erasable programmable read only memory (Electrically Erasable Programmable Memory).
able Read-only memory (EEPROM) or SR
It is stored in a memory 702 such as an AM (Static Random Access Memory) EPROM.

Then, under the switching control by the CPU 703, the hardware configuration information stored in the memory 702 is loaded, and the internal wiring of the FPGA 701 is rearranged so as to correspond to the information. With the above configuration,
The processing contents of the descrambler can be switched by hardware based on information from the transmission side.

[0096]

As described above, according to the present invention, it is possible to provide a digital signal transmitting apparatus and a receiving apparatus capable of controlling the switching or change of the hardware circuit of the receiving apparatus from the transmitting side.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram illustrating a configuration of a transmission device when multiplexing hardware configuration information regarding a descrambler in a digital broadcasting system as a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a receiving device of the embodiment.

FIG. 3 is a block circuit diagram illustrating, as a second embodiment of the present invention, a configuration of a transmission apparatus when multiplexing hardware configuration information and hardware switching information regarding a descrambler in a digital broadcasting system.

FIG. 4 is a block diagram showing a configuration of a receiving device of the embodiment.

FIG. 5 is a block circuit diagram showing a configuration of a transmission device when multiplexing transmission of hardware configuration information regarding a descrambler in a digital communication system as a third embodiment of the present invention.

FIG. 6 is a block circuit diagram showing a configuration of the receiving device of the embodiment.

FIG. 7 is a block circuit diagram illustrating, as a fourth embodiment of the present invention, a hardware configuration information relating to a clock switching circuit and a configuration of a receiving device when hardware switching information is multiplexed in a digital broadcasting system; .

FIG. 8 is a block circuit diagram illustrating, as a fifth embodiment of the present invention, a configuration of a receiving apparatus when hardware configuration information and hardware switching information regarding a clock supply circuit are multiplexed and transmitted in a digital communication system. .

FIG. 9 is a schematic diagram showing an outline of a scrambling algorithm taken as an embodiment of the present invention.

FIG. 10 is a block circuit diagram showing a general configuration of a descrambler used for digital broadcasting according to an embodiment of the present invention.

FIG. 11 is a block circuit diagram showing a configuration when an FPGA is used for the descrambler of the embodiment.

FIG. 12 is a diagram illustrating a packet configuration of a system layer of ISO / IEC13818-1.

FIG. 13 is a block circuit diagram showing a configuration of a system layer of ISO / IEC13818-1.

[Explanation of symbols]

000: video signal input terminal, 001: video encoder,
002: FIFO memory, 003: packetization circuit, 0
04: memory, 010: audio signal input terminal, 011: audio encoder, 012: FIFO memory, 13: packetization circuit, 014: memory, 020: hardware configuration information input terminal, 21: FIFO memory, 022: packetization circuit , 023 ... memory, 031 ... PMT generation circuit, 050, 051, 052, 053 ... memory, 054
... PAT generation circuit, 055 ... General packet multiplexing controller, 056 ... Bit stream signal output terminal, 100
... Antenna, 101 demodulation circuit, 102 error correction circuit (FEC), 103 descrambler, 104 memory, 105 video decoder, 106 audio decoder, 1
07 ... CPU, 108 ... NTSC decoder, 109 ... memory or hard disk, 110, 111 ... D / A conversion circuit, 112 ... monitor, 113 ... speaker, 114 ...
Microcomputer 115, remote controller 116, clock switching circuit 200, hardware switching information input terminal 20,
1 ... FIFO memory, 202 ... Packetizing circuit, 203
... Memory, 300 video signal input terminal, 301 video encoder, 302 FIFO memory, 303 packetization circuit, 304 memory, 310 voice signal input terminal
311 ... Audio encoder, 312 ... FIFO memory, 3
13: packetization circuit, 314: memory, 320: hardware configuration information input terminal, 321: FIFO memory,
322: packetization circuit, 323: memory, 330: packet multiplexing controller, 331: database, 33
2 ... program signal output terminal, 400 ... program signal input terminal, 4
02 Descrambler, 403 CPU, 404 Video decoder, 405 Audio decoder, 406 NTSC encoder, 407, 408 D / A conversion circuit, 409
Memory or hard disk, 410 ... keyboard, 4
11 monitor, 412 speaker, 413 clock supply circuit. 501 ... CBC mode processing circuit, 502 ... OF
B-mode processing circuit, 503, 504... Switch, A1,
B3: adder, A2, B1: 2-block multi-encryption processing unit, A3, B2: register, 601: register, 60
2,604 EX-OR gate, 603 AND gate, 701 FPGA, 702 memory, 703 CP
U.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code FI H04N 7/08 H04N 7/08 Z 7/081

Claims (11)

[Claims] A transmission signal to a digital signal receiver having hardware capable of rearranging wiring of a gate array based on given configuration information is multiplexed with hardware configuration information designating the wiring of the hardware. A digital signal transmitting device. 2. The digital signal receiving apparatus according to claim 1, wherein hardware switching information for switching from existing hardware configuration information to said multiplexed hardware configuration information is multiplexed with said transmission signal. Item 2. The digital signal transmitting device according to Item 1. 3. The digital signal receiving apparatus according to claim 2, further comprising: multiplexing, on said transmission signal, hardware switching information for selectively switching between existing hardware configuration information and said multiplexed hardware configuration information. The digital signal transmission device according to claim 1, wherein 4. The digital signal transmitting apparatus according to claim 1, wherein said hardware configuration information is compressed by a reversible compression method and multiplexed. 5. A hardware capable of rearranging wiring of a gate array based on given configuration information, and transmitting hardware configuration information multiplexed to a transmission signal from a transmission side and designating the wiring of the hardware. Digital signal reception comprising: hardware configuration information storage means for downloading and storing from a signal; and hardware control means for rearranging the hardware wiring based on the hardware configuration information stored in the means. apparatus. 6. The hardware control unit receives, from the transmission signal, hardware switching information multiplexed on the transmission signal and for switching from existing hardware configuration information to the downloaded hardware configuration information,
6. The digital signal receiving apparatus according to claim 5, wherein wiring of the hardware is switched to wiring corresponding to the downloaded information based on the received information. 7. The hardware configuration information storage means stores existing hardware configuration information and downloaded hardware configuration information, and the hardware control means stores the existing hardware configuration information and the downloaded hardware configuration information. Receiving hardware switching information from the transmission signal to select any of the hardware configuration information, extracting any hardware configuration information from the hardware configuration information storage means based on the received information, and 6. The digital signal receiving apparatus according to claim 5, wherein said wiring is selectively switched. 8. A desired logic is realized by regularly arranging programmable logic modules in the hardware, preparing a wiring area between them, and connecting the logic module and the wiring area according to a program. 6. The digital signal receiving apparatus according to claim 5, wherein a field programmable gate array is used. 9. The descrambler for descrambling the transmission signal, wherein the hardware control means connects the descrambler wiring using hardware configuration information corresponding to the scramble method. 6. The digital signal receiving device according to claim 5, wherein the switching is performed. 10. The system according to claim 1, wherein the hardware is a system clock generating circuit for generating a system clock of the present apparatus, and the hardware control unit is configured to execute the system clock based on hardware configuration information corresponding to the version upgrade of the system clock. 6. The digital signal receiving device according to claim 5, wherein wiring of the clock generation circuit is switched. 11. When the hardware configuration information multiplexed on the transmission signal is compressed by a reversible compression method, the hardware control means expands and executes the downloaded hardware configuration information. The digital signal receiving device according to claim 5, wherein: