JPH10270576A - Manufacture of double layer gate type semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a number of carrier trapping levels in the silicon nitride film in an ONO film and in the interface between the silicon nitride film and a silicon oxide film without thinning the silicon nitride film in the ONO film, and to suppress the charge holding rate in the early stage. SOLUTION: In this manufacturing method of a two-layer gate semiconductor memory storage, a wafer is heat-treated at 450 deg.C for several tens minutes (about 30 minutes, for example) as the second annealing treatment for the purpose of decreasing the interfacial level density on the interface of a P-type silicon substrate 1. The wafer is carried to a constant temperature vessel, a heat treatment is conducted at 175 to 325 deg.C, which is lower than the temperature of the second annealing treatment, for about 50 hours as the first annealing treatment. As a result, the trapping level of a number of carriers in a silicon nitride film 5 and on the interface of a silicon oxide films 4 and 6 can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a nonvolatile semiconductor memory device having a two-layer gate electrode of a floating gate and a control gate, and more particularly to an EPR.
It is suitable for application to OM, EEPROM, flash memory and the like.

[0002]

2. Description of the Related Art An EPROM is known as an electrically writable nonvolatile memory. This EPROM
So-called ONO having a three-layer structure of a silicon oxide film, a silicon nitride film, and a silicon oxide film as an interlayer insulating film between a floating gate and a control gate.
Some use a membrane.

The use of the ONO film has the advantage that the capacitance between the floating gate and the control gate made of polycrystalline silicon can be increased, and at the same time, the leakage and the breakdown voltage can be reduced. However, since many carrier trap levels are present at the interface between the silicon nitride film and the silicon oxide film or in the silicon nitride film, they are trapped by the carrier trap levels after writing to the floating gate. Carriers move in the nitride film due to thermal diffusion or the like. For this reason, there is a problem that a threshold change (Vt shift) occurs and the initial charge retention rate decreases (Pan et al., “A”).
Scaling Methodology for
Oxide-Nitride-Oxide inter
poly Dielectric for EPROM
Applications ”IEEE TRANSA
CTIONS ON ELCTRON DEVICES
VOL. 17, No. 6, June 1990).

To solve this problem, there is a method of reducing the amount of carrier movement by making the silicon nitride film thin.

[0005]

However, in order to ensure a high withstand voltage, it is necessary to make the insulating film a predetermined thickness. However, if the silicon oxide film having a small relative dielectric constant is made thicker, there arises a problem that the overall inter-gate capacitance becomes smaller.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to suppress a decrease in initial charge retention due to movement of carriers trapped at a carrier trap level without reducing the gate-to-gate capacitance. I do.

[0007]

The present invention employs the following means in order to solve the above problems. According to a first aspect of the present invention, in the method for manufacturing a two-layer gate type semiconductor memory device, an interface between the silicon nitride film (5) and the first and second insulating films (4, 6) or the silicon nitride film ( 5) A first heat treatment step for reducing the number of carriers trapped in the carrier trapping level in (5).

As described above, by performing the first heat treatment, the silicon nitride film (5) in the interlayer insulating film (20) is formed.
Since a large number of carrier trapping levels can be reduced in the middle or at the interface between the silicon nitride film (5) and the first and second insulating films (4, 6), it is possible to reduce the number of trapped levels at the time of writing to the floating gate (8). It is possible to reduce the number of carriers trapped in the carrier trapping level and to reduce the number of carriers moving in the silicon nitride film (5) due to thermal diffusion or the like after the writing.

Thus, the floating gate (8)
The decrease in the initial charge retention rate after writing to the memory can be reduced. In the case where the second heat treatment for reducing the interface state density on the surface of the substrate (1) is performed, the heat treatment temperature and the heat treatment time in the step of performing the first heat treatment are set as follows. 1) The temperature is lower and longer than the heat treatment temperature and the heat treatment time in the second heat treatment for reducing the interface state density at the interface.

Further, the temperature in the first annealing process can be set to a value in a temperature range of 175 ° C. to 325 ° C., for example, as set forth in claim 4; At 250 ° C., the processing time can be set within approximately 100 hours.

[0011]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a first embodiment of the present invention. A case where a method for manufacturing a two-layer gate type nonvolatile semiconductor device according to an embodiment of the present invention is applied to an EPROM will be described with reference to a manufacturing process diagram of the EPROM shown in FIG.

[Step shown in FIG. 1A] First, a LOCOS film (not shown) is formed on a P-type silicon substrate 1 to perform element isolation, and a gate oxide film 2 is formed on the surface of an element formation region. After the first polysilicon layer 3 is formed on the gate oxide film 2, phosphorus is deposited on the first polysilicon layer 3, and phosphorus ions are thermally deposited in the first polysilicon layer 3. Spread. Thereafter, although not shown, photolithography etching for forming a floating gate is performed.

Next, a silicon oxide film 4 is formed on the upper surface of the first polysilicon layer 3 by thermal oxidation. And LP
A silicon nitride film 5 is deposited on the silicon oxide film (first insulating film) 4 in a furnace. Thereafter, a silicon oxide film (second insulating film) 6 is formed on the silicon nitride film 5 by thermal oxidation. The ONO film (interlayer insulating film) 20
Is formed.

Subsequently, a second polysilicon film 7 is formed on the ONO film 20, and phosphorus ions are thermally diffused into the second polysilicon layer 7 by the same process as that of the first polysilicon layer 3 described above. . [Step shown in FIG. 1B] After that, the first and second polysilicon layers 3 are formed by photolithography and etching.
7 and the ONO film 20 are patterned to form a floating gate 8 and a control gate 9, and a silicon oxide film 10 is formed around the floating gate 8, the ONO film 20 and the control gate 9 by thermal oxidation.

[Step shown in FIG. 1C] Using the thermal oxide film 10, floating gate 8 and control gate 9 as a mask, ion implantation of N-type impurities
1. The drain 12 is formed. Although not shown, the electric field relaxation layer can be formed by performing relatively low concentration ion implantation before forming the source 11 and the drain 12.

[Step shown in FIG. 1 (d)]
An interlayer insulating film 13 made of PSG or the like is formed, and contact holes for an external lead electrode in the source 11, drain 12, and control gate 9 are opened in the interlayer insulating film. [Step shown in FIG. 1 (e)] By depositing an Al alloy film containing Al as a main component as a metal wiring material, patterning the electric wiring 14, and depositing a nitride film on the entire surface of the wafer by a plasma CVD method. A passivation film 15 is formed.

Thereafter, as a second annealing process, the wafer is subjected to a heating process at 450 ° C. for several tens of minutes (for example, approximately 30 minutes) to reduce the interface state (density) at the interface of the P-type silicon substrate 1. Reduce. Then, the wafer is transferred to a thermostat, in which a first annealing process is performed.
Heat treatment for a long time at a temperature lower than the temperature in the second annealing treatment, specifically, 175 ° C. to 325 ° C. (for example,
(About 250 ° C.) for about 50 hours. By this first annealing, a large number of carrier trap levels can be reduced in the silicon nitride film 5 in the ONO film 20 and at the interfaces between the silicon nitride film 5 and the silicon oxide films 4 and 6.

Next, the standing time between the case where the first annealing process is performed and the case where the first annealing process is not performed is as follows.
FIG. 2 shows a comparison diagram of the charge retention characteristics. The charge holding ratio is represented by Expression 1, and is obtained by measuring the voltage (Vt (t)) of the EPROM at five locations in the wafer and plotting the result obtained by using Expression 1 to determine the charge holding ratio. . However, since the charge retention rates in the above five EPROMs have widths as shown in the figure, their average values are plotted.

[0019]

## EQU00001 ## Charge holding ratio (%) = Vt (t) /Vt0.times.100 As is clear from FIG. 2, the charge holding ratio after writing rapidly decreases at the beginning of the standing time. The decrease is smaller when the annealing treatment is performed. That is, this is because a large number of carrier trap levels in the silicon nitride film 5 in the ONO film 20 and at the interfaces between the silicon nitride film 5 and the silicon oxide films 4 and 6 are reduced.

Further, as shown in FIG. 2, the charge holding ratio shows a charge holding characteristic generally observed after the write to the floating gate 8 rapidly decreases in the initial period of the standing time. If the initial decrease in the charge retention due to carrier movement in the silicon nitride film 5 is defined as a decrease from the charge retention of 100% by extrapolation as shown by the dotted line in the figure, the charge retention in the initial period after the writing is left. When the first annealing treatment was performed, the result was about 97.0%, and when the first annealing treatment was not performed, about 95.8%.

Further, looking at the charge retention life, for example, the time required for the charge retention rate to decrease to 95% is about 55 hours without the first annealing treatment, whereas the time when the first annealing treatment is not performed is about 55 hours. The result is about 110 hours. In other words, it can be said that the charge retention life is extended about twice or more.
As described above, by performing the first annealing process, O
Since a large number of carrier trapping levels in the silicon nitride film 5 in the NO film 20 or at the interface between the silicon nitride film 5 and the silicon oxide films 4 and 6 can be reduced, the above-described carrier can be reduced when writing to the floating gate 8 or the like. Carriers trapped in the trap level can be reduced, and carriers moving in the silicon nitride film 5 due to thermal diffusion or the like after the above-described writing can be reduced.

As a result, the amount of Vt shift can be reduced, that is, a decrease in the initial charge retention rate after writing to the floating gate 8 can be reduced. Although the first annealing is performed after the second annealing, the first annealing may be performed before the second annealing.

[Brief description of the drawings]

FIG. 1 is a process chart showing a method for manufacturing an EPROM according to an embodiment of the present invention.

FIG. 2 shows an EPRO manufactured by the method shown in FIG.
FIG. 9 is a diagram showing the charge retention characteristics of M.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... P type silicon substrate, 2 ... Gate oxide film, 4, 6 ... Silicon oxide film, 5 ... Silicon nitride film, 11 ... Source, 1
2 ... Drain, 13 ... Interlayer insulating film, 14 ... Electrical wiring, 1
5. Passivation film.

Claims (4)

[Claims] 1. A floating gate (8) is formed on a substrate (1) via a gate insulating film (2), and a first insulating film (4) and a silicon nitride film are formed on the floating gate (8). (5) and the second insulating film (6) are sequentially stacked to form an interlayer insulating film (20) sandwiching the silicon nitride film (5).
And forming a control gate (9) on the interlayer insulating film (20). In the method for manufacturing a two-layer gate type semiconductor memory device, the silicon nitride film (5) and the first and second Interface with insulating film (4, 6) or silicon nitride film (5)
A method for manufacturing a two-layer gate type semiconductor memory device, comprising: a first heat treatment step for reducing carriers trapped in a carrier trapping level in the semiconductor device. 2. A second heat treatment step for reducing an interface state density at an interface of the substrate (1), wherein the heat treatment temperature and the heat treatment time in the first heat treatment step are the same as those of the second heat treatment step. 2. The method according to claim 1, wherein the temperature is lower and longer than the heat treatment temperature and heat treatment time. 3. The temperature in the first heat treatment step is 1
3. The method according to claim 1, wherein the temperature is set in a temperature range of 75 [deg.] C. to 325 [deg.] C. 4. The method according to claim 1, wherein in the first heat treatment step, the heat treatment temperature is about 250 ° C., and the heat treatment time is set to a value within about 100 hours. A method for manufacturing a layer gate type semiconductor memory device.