JPH10270207A - Multiple laminated thermistor - Google Patents
Multiple laminated thermistorInfo
- Publication number
- JPH10270207A JPH10270207A JP7541397A JP7541397A JPH10270207A JP H10270207 A JPH10270207 A JP H10270207A JP 7541397 A JP7541397 A JP 7541397A JP 7541397 A JP7541397 A JP 7541397A JP H10270207 A JPH10270207 A JP H10270207A
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- thermistor
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- electrode
- internal electrode
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Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は情報機器、通信機
器、家電機器、住設機器、自動車機器等の温度センサに
用いる多連形積層サーミスタに関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-layer type thermistor used for a temperature sensor of information equipment, communication equipment, home electric equipment, housing equipment, automobile equipment and the like.
【0002】[0002]
【従来の技術】近年、情報機器、通信機器、家電機器、
住設機器、自動車機器等においてサーミスタにより、温
度特性を有する電子部品又は電子部品周辺の温度検知を
行い、その温度特性を補償する要望が大きくなってきて
いる。2. Description of the Related Art In recent years, information equipment, communication equipment, home electric appliances,
2. Description of the Related Art There is an increasing demand for detecting the temperature of an electronic component having a temperature characteristic or the vicinity of an electronic component by using a thermistor in a housing device, an automobile device, or the like, and compensating for the temperature characteristic.
【0003】従来、サーミスタによる温度検知は、図1
8に示すような回路構成で行ってきた。図18におい
て、11はサーミスタ、12はサーミスタに直列接続さ
れた固定抵抗器である。入力端子13、アース端子15
間に直流定電圧を印加すると、出力端子14にサーミス
タの温度に応じた電圧が出現する構成となっていた。な
お、ここに用いたサーミスタは図19,20に示す積層
サーミスタで1a,1bは内部電極、2a,2bは外部
電極、3はサーミスタ焼結体である。Conventionally, temperature detection by a thermistor is shown in FIG.
The circuit configuration shown in FIG. In FIG. 18, 11 is a thermistor, and 12 is a fixed resistor connected in series to the thermistor. Input terminal 13, ground terminal 15
When a constant DC voltage is applied during this period, a voltage corresponding to the temperature of the thermistor appears at the output terminal 14. The thermistor used here is a laminated thermistor shown in FIGS. 19 and 20, wherein 1a and 1b are internal electrodes, 2a and 2b are external electrodes, and 3 is a thermistor sintered body.
【0004】[0004]
【発明が解決しようとする課題】上記構成によると、一
般的な機器の使用温度範囲−20℃〜80℃において、
図17に示すように温度によりΔV/ΔT(感度)が異
なり、正確に温度検知を行うことが難しいという問題点
を有していた。According to the above configuration, in the operating temperature range of general equipment of -20 ° C to 80 ° C,
As shown in FIG. 17, ΔV / ΔT (sensitivity) differs depending on the temperature, and there is a problem that it is difficult to accurately detect the temperature.
【0005】そこで本発明は、広い温度範囲(100℃
以上)にてΔV/ΔT(感度)が一定となる電子回路を
容易に構成することができる多連形積層サーミスタを提
供することを目的とするものである。[0005] Therefore, the present invention provides a wide temperature range (100 ° C).
It is an object of the present invention to provide a multi-layered thermistor that can easily constitute an electronic circuit having a constant ΔV / ΔT (sensitivity).
【0006】[0006]
【課題を解決するための手段】この目的を達成するため
に本発明の多連形積層サーミスタは、複数のサーミスタ
層と複数の内部電極層とを交互に積層した積層体と、こ
の積層体の前記内部電極の露出した端面にかつ前記内部
電極に電気的に接続するように設けた少なくとも三つの
外部電極とを備えたものであり、複数のサーミスタ機能
を有することにより、上記目的を達成することができ
る。In order to achieve this object, a multi-layer laminated thermistor according to the present invention comprises: a laminated body in which a plurality of thermistor layers and a plurality of internal electrode layers are alternately laminated; At least three external electrodes provided on an exposed end face of the internal electrode and electrically connected to the internal electrode, and achieve the above object by having a plurality of thermistor functions. Can be.
【0007】[0007]
【発明の実施の形態】本発明の請求項1に記載の発明
は、複数のサーミスタ層と複数の内部電極層とを交互に
積層した積層体と、この積層体の前記内部電極の露出し
た端面にかつ前記内部電極に電気的に接続するように設
けた少なくとも三つの外部電極とを備えた多連形積層サ
ーミスタであり、複数のサーミスタ機能を有することに
より、広い温度範囲にて良好な感度を一定に維持する電
子回路を容易に構成することができるものである。DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 of the present invention is directed to a laminate in which a plurality of thermistor layers and a plurality of internal electrode layers are alternately laminated, and an exposed end face of the internal electrode of the laminate. And a multilayer laminated thermistor having at least three external electrodes provided so as to be electrically connected to the internal electrodes, and having a plurality of thermistor functions, thereby achieving good sensitivity over a wide temperature range. An electronic circuit that maintains a constant value can be easily configured.
【0008】請求項2に記載の発明は、内部電極間の抵
抗値をそれぞれ異なるようにした請求項1に記載の多連
形積層サーミスタであり、複数のサーミスタ機能を有す
ることにより、広い温度範囲にて良好な感度を一定に維
持する電子回路を容易に構成することができるものであ
る。According to a second aspect of the present invention, there is provided the multiple stacked thermistor according to the first aspect, wherein resistance values between the internal electrodes are different from each other. Thus, it is possible to easily configure an electronic circuit that maintains good sensitivity at a constant level.
【0009】請求項3に記載の発明は、内部電極間の抵
抗値は、一方の抵抗値が他方の抵抗値の1.5倍以上の
抵抗値を有する請求項2に記載の多連形積層サーミスタ
であり、さらに広い温度範囲にて良好な感度を一定に維
持する電子回路を容易に構成することができる。According to a third aspect of the present invention, the resistance value between the internal electrodes is such that one resistance value is 1.5 times or more the other resistance value. An electronic circuit which is a thermistor and maintains good sensitivity constant over a wider temperature range can be easily configured.
【0010】請求項4に記載の発明は、積層体内部に外
部電極に非接続の状態の内部電極を設けた請求項1に記
載の多連形積層サーミスタであり、静電容量を低く保ち
ながら低抵抗が得られるものである。According to a fourth aspect of the present invention, there is provided the multi-layer type thermistor according to the first aspect, wherein the internal electrode is provided inside the laminate and is not connected to the external electrode. A low resistance can be obtained.
【0011】以下、本発明の実施の形態について図面を
用いて説明する。 (実施の形態1)図1は本実施の形態における多連形積
層サーミスタであり、図2は同A−B断面図、図3は同
C−D断面図であり、2個のサーミスタを内蔵できるよ
う内部電極1a,1b,1cを所定の形状に印刷した遷
移金属酸化物からなるサーミスタ層3を積層、焼成して
得た焼結体の端面に外部電極2aは内部電極1aと、外
部電極2bは内部電極1bと、外部電極2cは内部電極
1cとそれぞれ電気的に接続するように外部電極ペース
トを塗布、焼き付けて形成したものである。外部電極2
aは2個のサーミスタの共通の外部電極となっており、
外部電極2a,2b間、外部電極2a,2c間で抵抗値
の異なる2個のサーミスタを構成している。An embodiment of the present invention will be described below with reference to the drawings. (Embodiment 1) FIG. 1 shows a multiple layered thermistor according to the present embodiment, FIG. 2 is a sectional view taken along line AB, and FIG. An external electrode 2a is formed on the end face of the sintered body obtained by laminating and firing a transition metal oxide having the internal electrodes 1a, 1b and 1c printed in a predetermined shape so that the internal electrode 1a and the external electrode can be formed. 2b is formed by applying and baking an external electrode paste so as to be electrically connected to the internal electrode 1b and the external electrode 2c, respectively. External electrode 2
a is a common external electrode of the two thermistors,
Two thermistors having different resistance values are formed between the external electrodes 2a and 2b and between the external electrodes 2a and 2c.
【0012】外部電極2b,2cに接続する内部電極1
b,1c間の影響を極力少なくするために内部電極1a
が間に介在するように配置することが好ましい。Internal electrode 1 connected to external electrodes 2b and 2c
internal electrode 1a to minimize the effect between b and 1c.
Are preferably arranged so as to be interposed therebetween.
【0013】また図16は本発明の多連形積層サーミス
タを用いた温度センサの回路であり、実用化できる広い
温度範囲(100℃以上)にてΔV/ΔT(感度)が一
定となるものである。なお25は入力端子、23,24
は固定抵抗器、21,22はサーミスタ、26はアース
端子、27は出力端子である。FIG. 16 shows a circuit of a temperature sensor using the multi-layered thermistor of the present invention, in which ΔV / ΔT (sensitivity) becomes constant over a wide temperature range (100 ° C. or higher) which can be practically used. is there. 25 is an input terminal, 23 and 24
Is a fixed resistor, 21 and 22 are thermistors, 26 is a ground terminal, and 27 is an output terminal.
【0014】(実施の形態2)図4は本実施の形態にお
ける多連形積層サーミスタであり、図5は同A−B断面
図、図6は同C−D断面図であり、図1に示すように共
通の内部電極1a及び外部電極2aを設けず、内部電極
1a,1b,1c,1d及び外部電極2a,2b,2
c,2dをそれぞれ4個形成して、外部電極2a,2b
間、外部電極2c,2d間で抵抗値の異なる2個のサー
ミスタを構成したものである。(Embodiment 2) FIG. 4 shows a multiple layered thermistor according to the present embodiment. FIG. 5 is a sectional view taken along the line AB, FIG. 6 is a sectional view taken along the line CD, and FIG. As shown, the common internal electrode 1a and the external electrode 2a are not provided, and the internal electrodes 1a, 1b, 1c, 1d and the external electrodes 2a, 2b, 2 are not provided.
c and 2d are formed respectively, and external electrodes 2a and 2b are formed.
And two thermistors having different resistance values between the external electrodes 2c and 2d.
【0015】(実施の形態3)図7は本実施の形態にお
ける多連形積層サーミスタであり、図8は同A−B断面
図、図9は同C−D断面図であり、内部電極1a,1
b,1c及び外部電極2a,2b,2cを図1に示すよ
うに共通の内部電極1a及び外部電極2aを設けず、内
部電極1a,1b,1cをそれぞれ異なる端面に引き出
して外部電極2a,2b,2cを形成し、外部電極2
a,2b間、外部電極2a,2c間で抵抗値の異なる2
個のサーミスタを構成したものである。(Embodiment 3) FIG. 7 shows a multiple layered thermistor according to the present embodiment. FIG. 8 is a sectional view taken along the line AB, FIG. 9 is a sectional view taken along the line CD, and the internal electrode 1a. , 1
As shown in FIG. 1, the internal electrodes 1a, 1b, 1c are not provided with the common electrodes b, 1c and the external electrodes 2a, 2b, 2c. , 2c and the external electrodes 2
a, 2b and the external electrodes 2a, 2c having different resistance values.
Thermistors are configured.
【0016】このように三つの外部電極2a,2b,2
cを異なる端面に設けることにより、内部電極1b,1
c間の影響は殆ど無視できる上に、図1,図4に示す多
連形積層サーミスタよりも小型のものが得られる。As described above, the three external electrodes 2a, 2b, 2
c are provided on different end faces, thereby enabling the internal electrodes 1b, 1
The influence between c is almost negligible, and a smaller one can be obtained than the multiple stacked thermistor shown in FIGS.
【0017】(実施の形態4)図10は本実施の形態に
おける多連形積層サーミスタであり、図11は同A−B
断面図、図12は同C−D断面図であり、低抵抗値のサ
ーミスタを得るため、図1の多連形積層サーミスタにお
いて、積層体内部に外部電極2aに接続する内部電極1
eを形成したものである。低抵抗化するための内部電極
は複数形成しても良い。(Embodiment 4) FIG. 10 shows a multi-layer laminated thermistor according to this embodiment, and FIG.
FIG. 12 is a cross-sectional view taken along the line CD in FIG. 12, and in order to obtain a thermistor having a low resistance value, in the multiple stacked thermistor of FIG.
e. A plurality of internal electrodes for lowering the resistance may be formed.
【0018】(実施の形態5)図13は本実施の形態に
おける多連形積層サーミスタであり、図14は同A−B
断面図、図15は同C−D断面図であり、低い静電容量
のサーミスタを得るため、図1の多連形積層サーミスタ
のそれぞれのサーミスタ機能部分において、積層体内部
に外部電極2a,2b,2cに接続しない内部電極1
f,1gを形成したものである。(Embodiment 5) FIG. 13 shows a multi-layered thermistor according to this embodiment, and FIG.
FIG. 15 is a cross-sectional view taken along the line CD in FIG. 15, and in order to obtain a thermistor having a low capacitance, external electrodes 2a and 2b are provided inside the multilayer body in each thermistor function part of the multiple stacked thermistor of FIG. , 2c not connected to internal electrode 1
f, 1 g.
【0019】なお、(実施の形態1)〜(実施の形態
5)において2つのサーミスタの抵抗値は一方の抵抗値
が他方の抵抗値の1.5倍以上になるようにすることに
より、ΔV/ΔT(感度)を広い温度範囲で一定とする
ことができる。この抵抗値は、サーミスタの材料、内部
電極の重ねあわせ面積、距離を選定することで自由に設
定することが可能である。In the first to fifth embodiments, the resistance value of the two thermistors is set such that one resistance value is 1.5 times or more the other resistance value, so that ΔV / ΔT (sensitivity) can be kept constant over a wide temperature range. This resistance value can be freely set by selecting the material of the thermistor, the overlapping area of the internal electrodes, and the distance.
【0020】本発明の多連形積層サーミスタを用いた温
度センサは、図17に示すように、−20℃〜80℃の
間において、ΔV/ΔT(感度)が一定かつ、半導体温
度センサの2倍の感度を有するものである。As shown in FIG. 17, the temperature sensor using the multiple stacked thermistor of the present invention has a constant ΔV / ΔT (sensitivity) between -20 ° C. and 80 ° C. It has twice the sensitivity.
【0021】さらに一つの積層サーミスタに二つのサー
ミスタを形成する場合についてのみ説明したが、同様に
して三つ以上のサーミスタを形成することもできる。Although only the case where two thermistors are formed in one laminated thermistor has been described, three or more thermistors can be formed in the same manner.
【0022】[0022]
【発明の効果】以上のように本発明の多連形積層サーミ
スタは、−20℃〜80℃の間において、感度が一定か
つ、半導体温度センサの2倍の感度を有する温度センサ
回路を形成することができる。この温度センサ回路は多
連形積層サーミスタ1個、固定抵抗器2個の3個と少な
い部品点数で得ることができ、機器の小型化において有
効であるとともに、実装面積、実装コストを削減するこ
とができる。As described above, the multi-layer type thermistor of the present invention forms a temperature sensor circuit having a constant sensitivity and a sensitivity twice as high as that of a semiconductor temperature sensor between -20 ° C and 80 ° C. be able to. This temperature sensor circuit can be obtained with a small number of components such as one multi-layer laminated thermistor and three fixed resistors, which is effective for miniaturization of equipment and reduces mounting area and mounting cost. Can be.
【図1】本発明の実施の形態1における多連形積層サー
ミスタの上面図FIG. 1 is a top view of a multiple stack thermistor according to Embodiment 1 of the present invention.
【図2】図1のA−B断面図FIG. 2 is a cross-sectional view taken along a line AB in FIG.
【図3】図1のC−D断面図FIG. 3 is a sectional view taken along line CD of FIG. 1;
【図4】本発明の実施の形態2における多連形積層サー
ミスタの上面図FIG. 4 is a top view of a multiple-layer laminated thermistor according to Embodiment 2 of the present invention.
【図5】図4のA−B断面図FIG. 5 is a sectional view taken along a line AB in FIG. 4;
【図6】図4のC−D断面図FIG. 6 is a sectional view taken along line CD of FIG. 4;
【図7】本発明の実施の形態3における多連形積層サー
ミスタの上面図FIG. 7 is a top view of a multiple-layer laminated thermistor according to Embodiment 3 of the present invention.
【図8】図7のA−B断面図8 is a sectional view taken along a line AB in FIG. 7;
【図9】図7のC−D断面図FIG. 9 is a sectional view taken along line CD of FIG. 7;
【図10】本発明の実施の形態4における多連形積層サ
ーミスタの上面図FIG. 10 is a top view of a multiple-layer laminated thermistor according to Embodiment 4 of the present invention.
【図11】図10のA−B断面図11 is a sectional view taken along a line AB in FIG.
【図12】図10のC−D断面図12 is a sectional view taken along line CD of FIG.
【図13】本発明の実施の形態5における多連形積層サ
ーミスタの上面図FIG. 13 is a top view of the multiple-layer laminated thermistor according to the fifth embodiment of the present invention.
【図14】図13のA−B断面図14 is a cross-sectional view taken along a line AB in FIG.
【図15】図13のC−D断面図FIG. 15 is a sectional view taken along line CD of FIG. 13;
【図16】本発明の多連形積層サーミスタを用いた温度
センサの回路図FIG. 16 is a circuit diagram of a temperature sensor using the multiple stacked thermistor of the present invention.
【図17】図16における温度センサ電圧(V)−温度
(T)特性曲線図17 is a characteristic curve diagram of a temperature sensor voltage (V) -temperature (T) in FIG.
【図18】従来の温度センサの回路図FIG. 18 is a circuit diagram of a conventional temperature sensor.
【図19】従来の積層サーミスタの上面図FIG. 19 is a top view of a conventional laminated thermistor.
【図20】図19のA−B断面図20 is a sectional view taken along a line AB in FIG. 19;
1a 内部電極 1b 内部電極 1c 内部電極 1d 内部電極 1e 内部電極 1f 内部電極 1g 内部電極 2a 外部電極 2b 外部電極 2c 外部電極 2d 外部電極 3 サーミスタ層 1a Internal electrode 1b Internal electrode 1c Internal electrode 1d Internal electrode 1e Internal electrode 1f Internal electrode 1g Internal electrode 2a External electrode 2b External electrode 2c External electrode 2d External electrode 3 Thermistor layer
───────────────────────────────────────────────────── フロントページの続き (72)発明者 鈴木 孝太郎 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 (72)発明者 大槻 淳 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 (72)発明者 井上 孝 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 (72)発明者 川尻 圭嗣 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Kotaro Suzuki 1006 Kazuma Kadoma, Osaka Prefecture Inside Matsushita Electric Industrial Co., Ltd. 72) Inventor Takashi Inoue 1006 Kazuma Kadoma, Kadoma City, Osaka Prefecture Inside Matsushita Electric Industrial Co., Ltd.
Claims (4)
とを交互に積層した積層体と、この積層体の前記内部電
極の露出した端面にかつ前記内部電極に電気的に接続す
るように設けた少なくとも三つの外部電極とを備えた多
連形積層サーミスタ。1. A laminate in which a plurality of thermistor layers and a plurality of internal electrode layers are alternately laminated, and provided on an exposed end face of the internal electrode of the laminate and electrically connected to the internal electrode. And a multi-layer laminated thermistor comprising at least three external electrodes.
ようにした請求項1に記載の多連形積層サーミスタ。2. The multiple stacked thermistor according to claim 1, wherein resistance values between the internal electrodes are different from each other.
他方の抵抗値の1.5倍以上の抵抗値を有する請求項2
に記載の多連形積層サーミスタ。3. The resistance value between the internal electrodes is such that one resistance value is 1.5 times or more the other resistance value.
2. The multiple layered thermistor according to 1.
内部電極を設けた請求項1に記載の多連形積層サーミス
タ。4. The multiple layered thermistor according to claim 1, wherein an internal electrode that is not connected to the external electrode is provided inside the multilayer body.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7541397A JPH10270207A (en) | 1997-03-27 | 1997-03-27 | Multiple laminated thermistor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7541397A JPH10270207A (en) | 1997-03-27 | 1997-03-27 | Multiple laminated thermistor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH10270207A true JPH10270207A (en) | 1998-10-09 |
Family
ID=13575474
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP7541397A Pending JPH10270207A (en) | 1997-03-27 | 1997-03-27 | Multiple laminated thermistor |
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Country | Link |
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JP (1) | JPH10270207A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7696677B2 (en) * | 2003-10-31 | 2010-04-13 | Murata Manufacturing Co., Ltd. | Lamination-type resistance element |
US7974070B2 (en) * | 2007-09-21 | 2011-07-05 | Tdk Corporation | Multilayer ceramic device and mounting structure therefor |
-
1997
- 1997-03-27 JP JP7541397A patent/JPH10270207A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7696677B2 (en) * | 2003-10-31 | 2010-04-13 | Murata Manufacturing Co., Ltd. | Lamination-type resistance element |
US7974070B2 (en) * | 2007-09-21 | 2011-07-05 | Tdk Corporation | Multilayer ceramic device and mounting structure therefor |
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