JPH10269150A - Memory initializing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To fast initialize data in a memory system even if the memory system is made mass and also to drastically reduce a time that is needed for a memory initialization operation. SOLUTION: A memory chip 20 that is constituted of DRAM(dynamic random access memory) is initialized by stopping a refresh cycle with an access controller 23 which has a function that controls a refresh cycle. That is, when power is inputted or at the time of the initialization operation of a memory system 1, an initialization operation control circuit 2 detects power determination with a power determination detection circuit 31, measures a fixed time with a timer circuit 30 after the power determination is detected, controls a refresh control circuit 24 and an access control circuit 23, stops a refresh operation at a fixed time and also inhibits an access from an outside to the chip 20 for the time. With this, data in the chip 20 is volatilized and initialized to all zeros or all ones.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory initialization method, and more particularly to a DRAM (Dyn) in an information processing system.
Amic Random Access Memory
y) relates to a method for initializing a memory system equipped with a memory chip constituted by the method.

[0002]

2. Description of the Related Art In a memory system having an error correction function, the relationship between data bits and check bits needs to be initialized because the stored contents are undefined when the information processing system is powered on. Initialization has been performed.

Conventionally, in this type of memory initialization method, data is written to all addresses in order. The instruction to write data is included in the initial diagnosis program at the time of starting the information processing system, and the CPU (Ce
The central processing unit) sequentially issues a data write instruction to all addresses of the memory system. Alternatively, an address generation circuit, a data generation circuit, and the like are prepared for memory initialization, and the memory system is initialized.

An example of a conventional memory initialization method is described in Japanese Patent Application Laid-Open No. 62-222495. According to the memory initialization method described in this publication, data in a memory circuit is initialized at a high speed by adding a redundant code to constant data and continuously writing the data to a memory circuit for initialization. This is a method for hastening the initial diagnosis of the generation and error detection circuit.

FIG. 6 is a block diagram showing an example of a memory system 101 to which a conventional memory initialization method is applied. The memory system 101 includes a memory circuit 112
, Access control circuit 114, address processing circuit 11
5, a constant data generation circuit 116 for generating constant data,
An initial setting control circuit 120 for continuously generating a memory write access immediately after power-on, and a memory for adding a redundant code to constant data output from a constant data generating circuit 116 when a memory write access occurs continuously. Circuit 11
2 includes a data processing circuit 119 for writing to the address indicated by the address counter and a refresh control circuit 118 for controlling the refresh cycle.

In such a memory system 101, immediately after the power is turned on, the initialization control circuit 120 is activated by a power-on reset, and a continuous memory write is output to the access control circuit 114. The data processing circuit 119 reads the constant data output from the constant data generation circuit 116, adds a redundant code to the data, and writes the data to the address indicated by the address counter in the memory circuit 112. In this way, by adding the redundant code to the constant data and writing the data continuously to the memory circuit 112, the initial setting is speeded up, and the start of the initial diagnosis can be hastened.

[0007]

A first problem of the above-mentioned prior art is that, with the increase in storage capacity, a memory initialization operation occupying initialization and diagnosis when starting up the information processing system is required. Time is increasing. The reason is that the memory initialization operation is executed sequentially for all addresses of the memory system.
Further, with the recent increase in performance of information processing systems, large-capacity memory systems have been required, and the capacity of memory systems has tended to increase further.

The second problem is that, for memory initialization,
The provision of the constant data generation circuit, the initial setting control circuit, and the address counter increases the amount of hardware. The reason is that a constant data generating circuit, an initial setting control circuit, and an address counter are required to automatically initialize all address spaces of the memory system, and the circuit scale and wiring scale increase.

A first object of the present invention is to enable high-speed initialization of data in a memory system even if the memory system has a large capacity, and to greatly reduce the time required for the memory initialization operation. It is to provide a memory initialization method which can be performed.

It is a second object of the present invention to provide a memory diagnostic method for verifying that the memory has been securely initialized by the above-described memory initialization method.

Further, a third object of the present invention is to provide a machine-readable recording medium on which a program for realizing the above-described memory diagnosis method is recorded.

Still another object of the present invention is to provide a memory system for implementing the above-mentioned memory initialization method.

[0013]

A memory initialization method according to the present invention is a memory initialization method for a memory system equipped with a memory chip constituted by a DRAM. The memory initialization method has an access control circuit having a function of controlling a refresh cycle. The memory chip is initialized by stopping a refresh cycle.

[0014] Further, the initialization diagnosis method of the present invention comprises a DRA
A first memory read step for reading a memory, the method comprising: performing a first memory read step for reading a memory by stopping a refresh cycle in a memory system including the memory chip configured with M. A first data error detection step of detecting
A first initialization data determination step of determining whether the read data matches the initialization data, and an initialization data write for writing the initialization data to the memory when the read data does not match the initialization data A second memory read step of reading data of the memory in which the initialization data has been written, a second data error detection step of detecting an error in the read data, and whether the read data matches the initialization data And a defective memory block determining step in which a block including a memory is determined to be a defective memory block when the read data does not match the initialization data.

Further, the machine-readable recording medium of the present invention provides a computer with a first memory read function for reading a memory and a first memory read function for detecting an error in read data.
A data error detection function, a first initialization data determination function for determining whether read data matches initialization data, and writing initialization data to memory when read data does not match initialization data. Initialization data write function, a second memory read function for reading data in the memory in which the initialization data is written, a second data error detection function for detecting an error in the read data, and the read data matches the initialization data. A program for realizing a second initialization data determination function for determining whether or not the read data does not match the initialization data, and a defective memory block determination function for setting a block including a memory as a defective memory block. Record.

Further, the memory system according to the present invention comprises:
A memory chip composed of a DRAM, a data control circuit having a function of exchanging data between the data bus and the memory chip and an error correction function, and an address control for outputting an address to the memory chip from an instruction address of an address bus An access control circuit having a circuit and a function of controlling a refresh cycle and instructing access to the memory chip from a control signal line; a refresh control circuit instructing the access control circuit to refresh the memory chip; An initial operation control circuit that controls the refresh control circuit and the access control circuit at the time of initialization operation of the memory system to stop the refresh operation for a certain period of time, and prohibits external access to the memory chip during that time. Characterized by having .

[0017]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 2 is a block diagram showing a schematic configuration of an information processing system on which the memory initialization method of the present invention is based. In this information processing system, the CPU 40 has a memory system 1 and a ROM (Read On)
ly Memory) 50. ROM5
0 stores the initial diagnosis program 60 and the like.
The recording medium for storing the initial diagnosis program 60 is:
The invention is not limited to the ROM 50, and may be a magnetic disk or another recording medium.

FIG. 1 is a block diagram showing a configuration of a memory system 1 to which a memory initialization method according to one embodiment of the present invention is applied. This memory system 1 has a DRA
M, a data control circuit 21 having a function of exchanging data between the data bus 10 and the memory chip 20 and an error correction function, and an address for the memory chip 20 based on an instruction address of the address bus 12. Output address control circuit 22 and memory system 1
An access control circuit 23 for instructing the access from the control signal line 11 to the memory chip 20 to the memory chip 20, a refresh control circuit 24 for instructing the access control circuit 23 to refresh the memory chip 20, a power-on state or an initial state of the memory system 1. Operation control circuit 2 for controlling the refresh control circuit 24 and the access control circuit 23 during the conversion operation
It is composed of

The memory system 1 includes a data bus 10 and
It is connected to a control signal line 11 and an address bus 12, and stores data and programs of the information processing system.

The data bus 10, the control signal line 11, and the address bus 12 are connected to a host (CPU 4) of the information processing system.
0) to transfer data, control instructions to the memory, and designate addresses.

The memory chip 20 is composed of a DRAM and holds data and programs of the information processing system.

The data control circuit 21 is connected to the data bus 10
, The memory chip 20, and the access control circuit 23. When reading data, the data control circuit 21 reads data from the memory chip 20, performs error detection and, if possible, error correction by an error correction function, and outputs the data to the data bus 10 as read data. When writing data, the data control circuit 21 adds a check bit to the data input from the data bus 10 so that the error correction function can function normally, and sends the data bit and the check bit to the memory chip 20. Write.

The address control circuit 22 is connected to the address bus 1
2, the memory chip 20, and the access control circuit 23. The address control circuit 22 inputs a data read or write address to the memory system 1 from the address bus 12 and instructs and outputs an address to the memory chip 20 so as to indicate a specific position in the memory chip 20.

The access control circuit 23 is connected to the control signal line 11
, A memory chip 20, a data control circuit 21, an address control circuit 22, a refresh control circuit 24, and an initial operation control circuit 2. The access control circuit 23 controls the data control circuit 21, the address control circuit 22, and the memory chip 20 in accordance with an instruction from the control signal line 11, and reads and writes data. Further, the access control circuit 23 performs a refresh operation of the memory chip 20 composed of a DRAM according to an instruction from the refresh control circuit 24.
Further, the access control circuit 23 includes the initial operation control circuit 2
During the period of the memory initialization due to the refresh cycle stop indicated by (1), no access request to the memory system 1 is accepted.

The refresh control circuit 24 is connected to the access control circuit 23 and the initial operation control circuit 2. During a normal operation of the information processing system, the refresh control circuit 24 activates a refresh cycle periodically at a time that satisfies a refresh interval required for holding data of a DRAM constituting the memory chip 20. A request to start a refresh cycle is output to the access control circuit 23. Also, the refresh control circuit 24 performs a memory initialization operation at power-on,
If there is an instruction from the initial operation control circuit 2 to initialize the memory by stopping the refresh cycle, a request to start the refresh cycle is not output to the access control circuit 23.

The initial operation control circuit 2 includes a timer circuit 30
, And a power supply confirmation detection circuit 31, and are connected to the refresh control circuit 24 and the access control circuit 23. The initial operation control circuit 2 transmits a memory initialization instruction signal for stopping the refresh cycle to the refresh control circuit 24 and the access control circuit 23 in order to execute the memory initialization at power-on by stopping the refresh cycle for a predetermined time. B (see FIG. 3) is output.

The timer circuit 30 includes a power supply confirmation detection circuit 31
, Refresh control circuit 24, access control circuit 2
3 and is connected to. The timer circuit 30 receives the output of the power supply confirmation signal A (see FIG. 3) from the power supply confirmation detection circuit 31 that detects the stability of the power supply voltage when the power is turned on, and receives the memory initialization instruction signal B (see FIG.
To the refresh control circuit 24 and the access control circuit 23.

FIG. 3 is a timing chart showing the output of the memory initialization instruction signal B and the like. In FIG. 3, a power determination signal A is a signal output from a power determination circuit 31, a memory initialization instruction signal B is a signal output from a timer circuit 30, and a refresh cycle start request signal C is output from a refresh control circuit 24. The access control signal D is a signal output from the access control circuit 23. When the power is turned on at time T0 and the power determination signal A is enabled by the power determination, the memory initialization instruction signal B is disabled at time T1 after a certain refresh cycle stop time. After the time T1, the normal memory control operation is performed, and the read, write, and refresh operations by the control signal are performed.

Referring to FIG. 4 and FIG. 5, the system memory diagnosis processing of the initialization diagnosis program 60 includes a diagnosis memory start address setting step A1, a memory read step A2, a data error detection step A3, and read data = initial data. Data determination step A4, final address determination step A5, next address setting step A
6, an initialization data write step B1, a memory read step B2, a data error detection step B3,
Read data = initialized data determination step B4 and defective memory block determination step B5.

Next, the memory initialization method according to the present embodiment configured as described above will be described together with the operation of the memory system 1.

In a normal operation state, the data control circuit 21, the address control circuit 22, and the access control circuit 2
3, data is read from and written to the memory chip 20. Further, in the memory chip 20 composed of a DRAM, a refresh cycle is periodically executed by the access control circuit 23 according to an instruction of the refresh control circuit 24.

When the power is turned on, a stable power supply voltage determination state is detected by the power supply determination detection circuit 31, and a power supply determination signal A is notified to the timer circuit 30.

The timer circuit 30 includes a power supply confirmation detection circuit 31
And supplies a memory initialization instruction signal B by refresh cycle stop to the refresh control circuit 24 and the access control circuit 23 until a predetermined time elapses after the power supply voltage is stably determined at power-on. Output.

During the normal operation, the refresh cycle of the memory chip 20 operating at a cycle of 2 ms to 64 ms is stopped for a fixed time (several ms to several s).

The refresh control circuit 24 outputs a refresh cycle stop request signal C to the access control circuit 23 to stop the refresh cycle until the memory initialization instruction signal B from the initial operation control circuit 2 is released.

As described above, by stopping the refresh operation for the memory chip 20 for a certain period of time, the DR
Most of the data in the memory chip 20 is initialized by utilizing the fact that the data disappears due to the AM not performing the refresh operation. The data in the memory chip 20 is
It tends to be all 0s or all 1s depending on the circuit configuration of the memory chip 20.

Further, the access control circuit 23 prevents external access to the memory chip 20 during memory initialization due to the stop of the refresh cycle.

Incidentally, in order to improve the reliability of the memory system 1, the memory system 1 usually has an error correction function. The data control circuit 21 performs error detection or correction on data read from the memory chip 20 during the memory read operation. At the time of writing, a check bit is added to the input data bit from the data bus 10 to
Writing data to Therefore, the error correction function of the data control circuit 21 determines whether the data becomes all 0 or all 1 when the memory chip 20 initializes the memory by stopping the refresh cycle. An error correcting code that is related is used.

When performing error correction, as a typical example, a linear code can be used as one having a one-bit error correction / two-bit error detection function. In the case of a linear code, a code obtained by adding a check bit to a data bit is a generated code.
Recorded as 0. In order to perform addition and subtraction between bits of data when encoding from data bits, all check bits may be set to 0. When a Hamming code, which is a kind of linear code, is used, the data bits and the check bits can be used as all 0s. Also, check bits added to the type of encoding include, for example, all 0s.
Even if the check bit contains "1" for the data of, many encoding methods can be used if the bit line is always inverted and treated as a code. In the case of the memory chip 20, it is difficult to realize error correction of all data bits, and from a practical point of view, one-bit error correction
A code having a function of 2-bit error detection is used. The number of data bits is 32 bits, the number of check bits is 7 bits, the number of data bits is 64 bits, and the number of check bits is 8 bits.
Even if an inversion circuit is added to a part of the check bits, only a few gates need to be added, and the circuit scale does not increase. Even if the initialization data on the memory chip 20 is "1", there is no problem if the input / output stage of the data control circuit 21 handles "0" as a data bit. Usually, an input / output gate is added to the input / output stage. If a buffer or an inversion buffer is adopted according to the characteristics of the memory chip 20, no additional circuit is required.

In order to ensure that all the data in the memory chip 20 is initialized by stopping the refresh cycle, if the refresh stop time is too long, the refresh stop is performed at the time when most of the data is initialized. The time is set and the data initialization is guaranteed by the following method.

Initial diagnosis program 6 for information processing system
In the memory system diagnosis of 0, the initialization check of the memory system 1 is performed after the initialization of the memory system 1 due to the stop of the refresh cycle. All bits are initialized to all 0s or all 1s, and it is diagnosed that the error correction function operates normally. If there is data that has not been completely initialized within the refresh cycle stop period, the initialization data is written to the address and executed, and it is diagnosed that the data has the initial value again and the error correction function operates normally. . Data initialization can be guaranteed simultaneously with the initialization check of the memory system 1.

More specifically, the initialization diagnostic program 60
Memory chip 20 for starting diagnosis at diagnosis address ADR
Is set (step A1). next,
The initialization diagnostic program 60 reads the memory at the address indicated by the diagnostic address ADR (step A2), and determines whether a data error has been detected by performing the memory read (step A3). If no data error is detected, the initialization diagnosis program 60 determines whether the read data matches the initialization data (all 0s or all 1s) (step A4). If the read data matches the initialization data (all 0s or all 1s), the initialization diagnosis program 60 sets the diagnosis address AD
It is determined whether or not R has reached the final address (step A5). If the diagnostic address ADR has not reached the final address, the initialization diagnostic program 60 sets the next address in the diagnostic address ADR (step A).
6) Return control to step A2. On the other hand, step A3
When a data error is detected in step S4 and when the read data does not match the initialization data (all 0 or all 1) in step A4, the initialization diagnosis program 60 initializes the memory indicated by the diagnosis address ADR. The data is written (step B1). Next, the initialization diagnosis program 60 reads the memory at the address indicated by the diagnosis address ADR (Step B2), and executes the memory read to determine whether a data error has been detected (Step B3). If no data error is detected,
The initialization diagnosis program 60 determines whether the read data matches the initialization data (all 0s or all 1s) (step B4). If a data error is detected, or if the read data does not match the initialization data (all 0s or all 1s), the initialization diagnostic program 60 has generated an error even after writing the initialization data. Therefore, the memory block including the corresponding diagnostic address ADR is removed from the memory map of the information processing system as a defective memory block, and an error notification is performed.
(Step B5) The control is shifted to Step A5. Then, when the diagnostic address ADR reaches the final address in step A5, the initialization diagnostic program 60 ends the memory system diagnostic processing.

Further, during execution of the initial diagnosis program 60 of the information processing system, the CPU 40 executing the diagnosis by the instruction of the initial diagnosis program 60 instructs the access control circuit 23 through the control signal line 11 to stop the refresh cycle. Controlling the refresh control circuit 24,
An access control circuit 23 capable of stopping a refresh cycle for memory initialization can also be used.

[0045]

The first effect is that the initialization time of the memory can be reduced. The reason is that the entire memory can be initialized at once by stopping the operation of the refresh cycle without performing the memory initialization operation sequentially for all addresses of the memory system which takes time.

A second effect is that the amount of hardware is not increased as compared with a memory system having a constant data generation circuit for initializing a memory, an initialization control circuit, and an address counter. The reason is that the memory initialization operation can be realized only by the initial operation control circuit with the timer function that can stop the refresh control circuit when the power is turned on and the memory system initialization operation. This is because no circuit is required.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a memory system to which a memory initialization method according to an embodiment of the present invention has been applied.

FIG. 2 is a block diagram showing a schematic configuration of an information processing system which is a premise of the memory initialization method of the present invention.

FIG. 3 is a timing chart for explaining output of a memory initialization instruction signal and the like of the memory system of FIG. 1;

FIG. 4 is a flowchart showing a part of a system memory diagnosis process performed by the initialization diagnosis program for the memory system in FIG. 1;

FIG. 5 is a flowchart showing another part of the system memory diagnosis processing performed by the initialization diagnosis program for the memory system in FIG. 1;

FIG. 6 is a block diagram illustrating an example of a conventional memory system.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 memory system 2 initial operation control circuit 10 data bus 11 control signal line 12 address bus 20 memory chip 21 data control circuit 22 address control circuit 23 access control circuit 24 refresh control circuit 30 timer circuit 31 power supply fixed detection circuit 40 CPU 50 ROM 60 Initial diagnostic program A1 Diagnostic memory start address setting step A2 Memory read step A3 Data error detection step A4 Read data = initial data determination step A5 Final address determination step A6 Next address setting step A7 Initial data write step B1 Initial data write step B2 Memory read step B3 Data error detection step B4 Read data = initialization data determination step B5 Bad memory block determination step

Claims (5)

[Claims] 1. A memory initialization method for a memory system equipped with a memory chip constituted by a DRAM, comprising: an access control circuit having a function of controlling a refresh cycle; A memory initialization method characterized by performing initialization. 2. An initialization method for initializing a memory chip by stopping a refresh cycle in a memory system having a memory chip formed of a DRAM mounted thereon, comprising: a first memory read step for reading a memory; A first data error detecting step of detecting an error in the read data, a first initialization data determining step of determining whether the read data matches the initialization data, and a first data error determining step of determining whether the read data matches the initialization data. An initialization data writing step of writing the initialization data to the memory when the initialization data has not been written; a second memory reading step of reading the data of the memory in which the initialization data has been written; and a second step of detecting an error in the read data. A data error detection step, and a second initialization for determining whether the read data matches the initialization data. Data determination step and, initialization diagnosing method characterized by including the defective memory block determining step of the block including the memory and the defective memory block when the read data does not match the initialization data. 3. A first memory read function for reading a memory, a first data error detection function for detecting an error in read data, and a first function for determining whether the read data matches the initialization data. An initialization data determination function, an initialization data write function of writing initialization data to a memory when read data does not match the initialization data, and a second function of reading data of the memory in which the initialization data has been written. A memory read function, a second data error detection function for detecting read data errors,
A second initialization data determination function for determining whether or not the read data matches the initialization data, and a bad memory block in which a block including a memory is determined as a bad memory block when the read data does not match the initialization data A machine-readable recording medium on which a program for realizing a decision function is recorded. 4. A memory chip composed of a DRAM, a data control circuit having a function of exchanging data between a data bus and the memory chip and an error correction function, and an address from the designated address of the address bus to the memory chip. An address control circuit that outputs a clock signal, an access control circuit that has a function of controlling a refresh cycle, and instructs access to the memory chip from a control signal line, and a refresh control that instructs the access control circuit to refresh the memory chip. And a circuit for controlling the refresh control circuit and the access control circuit at power-on or at the time of an initialization operation of the memory system to stop the refresh operation for a certain period of time, and to prohibit external access to the memory chip during the period. With an initial operation control circuit Memory system, characterized in that. 5. The initial operation control circuit according to claim 1, further comprising: a power supply confirmation detecting circuit for detecting the power supply confirmation; and a timer circuit for measuring a fixed time after the power supply confirmation is detected by the power supply confirmation detection circuit. Item 5. The memory system according to Item 4.