JPH10268260A - Active matrix type display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a constant counter electrode driving circuit by preventing malfunctions of transistors to be provided for output push-pull circuits in the counter electrode driving circuit to be sued for an active matrix type liquid crystal display device. SOLUTION: This counter electrode driving circuit generates counter electrode driving signals VCOMs and is provided with push-pull circuits 2 consisting of bipolar transistors and protective stransistors T3s connected between the push-pull circuits and a power source in series. When the driving signal VCOM is short-circuited with a power source VDD by a sudden accident, the malfunction of the transistors in the push-pull circuit is prevented by making the protective transistor T3 be in an off state.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving circuit for periodically shifting the electrode potential of a liquid crystal panel of an active matrix type display device.

[0002]

2. Description of the Related Art A flat display device represented by a liquid crystal display device has become quite popular because of its advantages of thinness, light weight, and low power consumption. A general liquid crystal display device has a structure in which a liquid crystal composition is held between an array substrate and a counter electrode. The array substrate and the counter electrode have, for example, insulating properties and light transmissivity, respectively, and a liquid crystal cell is formed by filling a gap between the array substrate and the counter electrode with a liquid crystal composition. The array substrate includes a matrix array of a plurality of pixel electrodes, a plurality of scanning lines respectively formed along the rows of the pixel electrodes, a plurality of signal lines respectively formed along the columns of the pixel electrodes, And a first alignment film that entirely covers the matrix array of pixel electrodes. Each of the plurality of scanning lines selects a row of the pixel electrodes, and each of the plurality of signal lines is provided for applying a signal voltage to the pixel electrodes of the selected row. The counter electrode has a counter electrode facing the matrix array of the plurality of pixel electrodes, and a second alignment film that entirely covers the counter electrode. The first and second alignment films are provided for twisting nematic (TN) alignment of liquid crystal molecules in the liquid crystal cell when there is no potential difference between the pixel electrode and the counter electrode.
When polarized light enters the liquid crystal layer from one substrate side, the polarized light turns along the twist of the liquid crystal molecules arranged in the thickness direction of the liquid crystal layer, is guided to the other substrate, and is further selected via the polarizing plate. Is transparently transmitted. When a potential difference is applied between the pixel electrode and the counter electrode, the liquid crystal molecules tilt up from a plane parallel to the substrate surface on which an image is displayed by an angle proportional to the potential difference, and change the transmittance of polarized light.

In an active matrix type liquid crystal display device, a plurality of thin film transistors (TFTs) are formed adjacent to intersections of scanning lines and signal lines, respectively, and are used as switching elements for selectively driving corresponding pixel electrodes. . The gate of each TFT is connected to one scanning line, the drain is connected to one signal line, and the source is connected to one pixel electrode. The TFT supplies a signal voltage from a signal line to a pixel electrode when the TFT is turned on with a rising of a scanning pulse from the scanning line. The liquid crystal capacitance CLC between the pixel electrode and the counter electrode is charged with a potential difference, and is held even after the TFT becomes non-conductive with the falling of the scanning pulse.

By the way, if the direction of the electric field is maintained in one direction, substances other than the liquid crystal move in the liquid crystal cell by this electric field, and gather on one electrode side. This causes the life of the liquid crystal cell to be shortened. Conventionally, as a solution to this problem, a technique of inverting the polarity of a signal voltage using the potential of the counter electrode as a reference potential, for example, in order to reverse the direction of the electric field every frame period is known. Further, the polarity inversion of the signal voltage is also performed, for example, every one horizontal scanning period in order to reduce flicker. The counter electrode drive circuit is used to positively shift the reference potential in order to avoid the increase of the signal voltage amplitude, and the potential of the counter electrode is controlled by the counter electrode drive signal VCOM generated from the counter electrode drive circuit. You. In this case, the signal voltage is inverted with respect to its center level, and the signal VCOM is changed to a high level VCOMH and a low level VCO every time the signal voltage is inverted.
ML is inverted from one to the other.

In order to drive the counter electrode, the liquid crystal is driven, so that an optimum voltage amplitude and a current for charging the counter electrode are required. FIG. 4 shows a conventional counter electrode drive circuit. The polarity inversion signal PPOL is voltage-amplified by an operational amplifier, and current is amplified by a transistor having a push-pull configuration to obtain a desired output. The power supply uses VBB + and VBB- obtained from a DC-DC converter.

The push-pull circuit includes an NPN transistor connected between a positive power supply terminal and an output terminal for outputting a high level VCOMH of +3.7 V;
A PNP transistor connected between an output terminal and a negative power supply terminal for outputting a low-level VCOML of 3 V, and a high-level VCOMH and a low-level VC according to a polarity inversion signal supplied to the bases of these transistors;
Output one of OML. Considering the voltage drop corresponding to the voltage VBE between the base and the emitter of the transistor, the voltages at the positive and negative power supply terminals are +6.5 V and -5 V, respectively.
Set to about.

[0007]

However, in the counter electrode driving circuit having the above-described configuration, when the counter electrode output and the power supply VDD are short-circuited due to an unexpected accident, the transistor T2 remains ON, and the current flows to VBB-. Flows,
The DC-DC converter 5 shuts down and VBB-
The transistor T2 is still ON even if
Since the state is maintained, an overcurrent continues to flow through the transistor T2, causing a problem that the transistor T2 malfunctions.

Here, as a cause of the VDD-VCOM short-circuit, VDD and VCO at the input pad of X-TAB are set.
Since the M terminals are arranged adjacent to each other, there is a possibility that solder failure occurs in the manufacturing process. Therefore, an object of the present invention is to provide a stable counter electrode drive circuit by preventing a malfunction of the transistor T2.

[0009]

According to the present invention, there is provided a counter electrode driving circuit in which a protection transistor is arranged in series in a counter electrode driving circuit for a liquid crystal display device.
That is, the counter electrode drive circuit used in the active matrix display device of the present invention generates a counter electrode drive signal and is connected in series between the push-pull circuit composed of a bipolar transistor and the push-pull circuit and its power supply. An overcurrent prevention circuit.

By using a protection transistor for preventing an overcurrent in the counter electrode drive circuit, when the power supply VDD and the drive signal VCOM are short-circuited due to an unexpected accident, the protection transistor is turned off and the transistor in the push-pull circuit is turned off. Erroneous operation is prevented, and a stable counter electrode drive circuit is provided.

When the power supply VDD and the drive signal output VCOM are short-circuited, a current higher than a steady current flows through the transistor in the push-pull circuit and the output of the DC-DC converter, the DC-DC converter shuts down, and the output of this converter becomes GND level. become. At this time, the emitter of the protection transistor is at the GND level, and its base is also connected to GND via the resistor, so that the GND is
Become a level. Therefore, the emitter of the protection transistor
The base-to-base voltage VBE becomes 0 V, so that this transistor turns off, and the current flowing through the transistor in the push-pull circuit is cut off.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a counter electrode driving circuit provided in an active matrix display device according to the present invention will be described below with reference to the drawings. FIG. 1 shows the configuration of this active matrix counter electrode driving circuit.
1 schematically shows a circuit configuration of an active matrix type liquid crystal display device using a drive signal generated by the counter electrode drive circuit.

The liquid crystal display device shown in FIG. 2 is, for example, a normally white mode liquid crystal panel 10 capable of color display.
An X driver 12 and a Y driver 14 electrically connected to the liquid crystal panel 10;
Controller 16 for controlling the Y and Y drivers 14
And

The liquid crystal panel 10 has a structure similar to that of the related art in which a liquid crystal composition is held between an array substrate having light transmittance and an opposing substrate. Array substrate is (640 × 3) ×
A matrix array of 480 pixel electrodes 20 and a scanning line Y formed along each row of these pixel electrodes 20
1 to Y480, signal lines X1 to X640 × 3 formed along the columns of the pixel electrodes 20, respectively, and a first alignment film that entirely covers the matrix array of the pixel electrodes 20. The scanning lines Y1 to Y480 each select a row of the pixel electrodes 20, and the signal lines X1 to X640 × 3
Are provided for applying a signal voltage to the pixel electrodes 20 of the selected row. The opposing substrate includes an opposing electrode 22 opposing the matrix array of the pixel electrodes 20 and the opposing electrode 22.
And a second alignment film that covers the entire surface. First and second
The alignment film is provided to cause liquid crystal molecules in the liquid crystal cell to be twisted nematic (TN) when there is no potential difference between the pixel electrode 20 and the counter electrode 22. Two polarizing plates set in directions orthogonal to each other are attached to the outer surfaces of the array substrate and the counter electrode.

For the array substrate, (640 × 3) ×
480 thin film transistors (TFTs) 24 are further provided with scanning lines Y1 to Y480 and signal lines X1 to X640 ×
3 are respectively formed adjacent to the intersections and are used as switching elements for selectively driving the corresponding pixel electrodes 20. The gate of each TFT 24 is connected to one of the scanning lines Y1 to Y480, the drain is connected to one of the signal lines X1 to X640 × 3, and the source is connected to one of all the pixel electrodes 20. Is done. Further, the auxiliary capacitance lines 26 are formed along the rows of the pixel electrodes 20.
Each pixel electrode 20 forms a liquid crystal capacitance CLC by capacitive coupling with the counter electrode 22, and forms an auxiliary capacitance CS by capacitive coupling with the auxiliary capacitance line 26. The gate and source of each TFT 24 are connected to a parasitic capacitance CG formed between them.
Inevitably has S.

The liquid crystal controller 16 receives gradation data supplied from the outside in pixel units, generates a start pulse ST and a shift clock CK in synchronization with the supply timing of the gradation data, and outputs the start data to the start pulse S
It is supplied to the X driver 12 together with T and the shift clock CK. The start pulse ST is generated every horizontal scanning period, and the shift clock CK is generated at each supply timing of 640 × 3 pieces of gradation data sequentially supplied in synchronization with the start pulse ST. The liquid crystal controller 16 further generates a selection signal for selecting one of the scanning lines Y1 to Y480 every horizontal scanning period, and supplies this to the Y driver 14. The shift clock CK is stopped when the gradation data is no longer supplied from outside. When the operation is stopped, the liquid crystal controller 16 supplies the X driver 12 with gradation data fixed to a predetermined value representing complete black so as to prevent the deterioration of the liquid crystal composition. In addition, the liquid crystal controller 16 outputs the polarity inversion signal PPOL that alternately changes from one of 0 V and +5 V to the other every one frame period and one horizontal scanning period in order to perform the frame inversion drive and the line inversion drive of the pixel electrode. To supply. This polarity inversion signal PPOL is also supplied to the counter electrode drive circuit shown in FIG.

The X driver 12 includes a 640 × 3 shift register, a D / A converter, and 640 × 3 latch circuits (not shown). The shift register transfers the start pulse ST to a subsequent stage in response to the shift clock CK. In response to the shift clock CK, the D / A converter converts the grayscale data to a signal voltage level in a range from 0 V to +5 V obtained from the power supply voltage + VDD (+5 V). Each of the 640 × 3 latch circuits latches the output of the D / A converter in response to the start pulse ST transferred to the corresponding stage of the shift register, and responds to the next start pulse ST supplied from the liquid crystal controller 16. And the latch voltages are used as the signal voltages,
Supplies 640x3 continuously. When the gradation data is fixed at the predetermined value by the liquid crystal controller 16, the D / A converter converts the gradation data to a signal voltage level of + 5V. Also, the D / A converter outputs a polarity inversion signal PPOL supplied from the liquid crystal controller 16 of + 5V.
, The signal voltage level converted from the gradation data is +2.5 V which is the center level in the range of 0 V to +5 V.
Invert with reference to

The Y driver 14 sequentially selects the scanning lines Y1 to Y480 based on a selection signal from the liquid crystal controller 16, and outputs a scanning pulse rising from -12V equal to the power supply voltage -VOFF to + 19V equal to the power supply voltage + VON. To supply. The potential of the non-selected scanning lines is maintained at -12 V, which is equal to the power supply voltage -VOFF.

Each TFT 24 supplies a signal voltage from a corresponding signal line to the pixel electrode 20 when the TFT 24 is turned on with a rise of a scanning pulse from the corresponding scanning line. The liquid crystal capacitance CLC between the pixel electrode 20 and the counter electrode 22 and the pixel electrode 2
The storage capacitor CS between 0 and the storage capacitor line 26 is charged by this signal voltage. The TFT 24 becomes non-conductive with the fall of the scanning pulse, but the potential of the pixel electrode 20 is maintained with reference to the potential of the counter electrode 22 thereafter.
It is canceled when the FT 24 conducts again after one frame period.

The counter electrode driving circuit shown in FIG. 1 is incorporated in a liquid crystal display device for driving the counter electrode 22 and the auxiliary capacitance line 26 of the liquid crystal panel shown in FIG. FIG. 1 shows a configuration of a counter electrode drive circuit according to the present invention in which an overcurrent protection circuit is added to the drive circuit of FIG.

This opposing electrode drive circuit includes an operational amplifier OP for amplifying the amplitude and for adjusting the center of the drive signal VCOM.
1 and an operational amplifier OP2 for current amplification
And an amplification circuit 2 including transistors T1 and T2, and a protection circuit 3 including a transistor T3.
The power supply of this counter electrode drive circuit is a DC-DC converter 5
From.

Here, the voltage generated from the DC-DC converter 5 is VBB + = 6.5V, VBB − = − 5V, and the power supply voltage VDD of this circuit is 5V.
Any voltage may be used as long as there is a voltage necessary to obtain M amplitude.

The polarity inversion signal PPOL generated from the liquid crystal controller 16 in FIG. 2 is supplied to the inversion input of the operational amplifier OP1 via the resistor R1. The center value VCOMC of the drive signal VCOM is applied to the non-inverting input of the operational amplifier OP1.
Is supplied. This inverting input is connected to the output of the operational amplifier OP1, that is, the node A, via the variable resistor VR1. Therefore, the polarity inversion signal PPOL is voltage-amplified according to the ratio of the resistance values of the resistor R1 and the variable resistor VR1, and the center potential of the output signal is VCOMC.

The node A is connected to the non-inverting input of the operational amplifier OP2. The inverting input of the operational amplifier OP2 is connected to the output of the amplifier circuit 2, that is, the node C via the resistor R3. The output of the operational amplifier OP2 is connected to the node B via the resistor R2, and the node B is connected to one end of the resistor R5 and the bases of the transistors T1 and T2. A filtering capacitor C1 is connected between the inverting input and the output of the operational amplifier OP2. The other end of the resistor R5 and the emitters of the transistors T1 and T2 are connected to the output of the amplifier circuit 2, that is, the node C. The collector of the transistor T1 is connected to VBB + (6.5 V), and the collector of the transistor T2 is connected to the collector of the transistor T3. The base of the collector transistor T3 is a resistor R4
, And the emitter is connected to VBB-(− 5
V). Accordingly, the signal on the node A is current-amplified by the amplifier circuit 2.

Here, the counter electrode drive signal VCOM will be described. In the liquid crystal panel 10 of this embodiment, the signal voltage is generated from the voltage of the power supply terminal + VDD (for example, 5 V), and changes in the range of 0 V to + VDD according to the gradation data. As shown in FIG. 3, for example, when the scanning line Y1 rises from VOFF (−12V) to VON (+ 19V) by the scanning pulse from the Y driver 14, the TFT of the corresponding row is turned on.
24 becomes conductive, and applies the signal voltage supplied from the X driver 12 to the first scanning line Y1 to the corresponding pixel electrode 20. At this time, if the signal voltage is + VDD, the pixel potential of the pixel electrode 20 changes to + VDD. However, the TFT 24
Since the gate and the source, and the pixel electrode and the scanning line have a parasitic capacitance CGS formed between them,
When the TFT 24 becomes non-conductive, the charge on the pixel electrode 20 moves to charge the capacitor CGS, and this lowers the potential of the pixel electrode 20 by a predetermined level ΔVP (about 1.3 V). Further, when the level conversion of the signal voltage is performed for the frame inversion drive and the line inversion drive, the pixel potential of the pixel electrode 20 becomes 0V. in this case,
After the TFT 24 becomes non-conductive, the pixel potential further increases by a predetermined level ΔVP (about 1.3 V) due to the parasitic capacitance CGS.
Just drop. In order to obtain a required potential difference of VDD between the pixel electrode 20 and the counter electrode 22, the driving signal VCO
The high level value VCOMH of M is set to VDD−ΔVP, and the low level value VCOML of the drive signal VCOM is 0V
-ΔVP is set. In this case, the amplitude VCOM (pp) of the drive signal VCOM is set to VDD, and the center value VCOMC of the drive signal VCOM is (VCOMH-VC
OML) / 2 V.

Next, the operation of the counter electrode driving circuit of the present invention will be described. In normal operation, transistor T3 is ON
The emitter potential of the transistor T3 is-
The base potential is 5 V and the base potential is -4.3 V (because the voltage VBE between the base and the emitter of the transistor is 0.7 V in the ON state). If the VCOM output is shorted to VDD for any reason, the VCOM output on node C will be forced to 5V. At this time, since a normal signal is applied to the base of the transistor T2, the transistor T2 maintains the ON state, shifts to the constant current source state, and acts to force the current to flow. At this time, the current flowing through the transistor T2 was 150 mA.

Since this current flows directly to VBB- of the DC-DC converter via the transistor T3,
The C-DC converter shuts down and VBB-
It goes to the ND level. At this time, since the voltage VBE between the emitter and the base of the transistor T3 becomes 0 V, the transistor T3 is turned off, and the current flowing through the transistor T2 can be cut off, so that the T2 does not malfunction. Note that the present invention is not limited to the above-described embodiment, and can be variously modified without departing from the gist thereof.

[0028]

According to the counter electrode driving circuit of the present invention, it is possible to prevent a transistor malfunction when the power supply VDD and the VCOM output are short-circuited due to an unexpected accident, so that a stable counter electrode driving circuit can be provided. .

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a counter electrode driving circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram schematically showing a configuration of a liquid crystal display device in which the counter electrode driving circuit shown in FIG. 1 is incorporated.

FIG. 3 is a voltage waveform diagram for explaining a counter electrode drive signal.

FIG. 4 is a circuit diagram showing a configuration of a counter electrode drive circuit according to a first conventional example.

[Explanation of symbols]

 OP1, OP2 ... operational amplifiers TR1 to TR3 ... transistors R1 to R5 ... fixed resistors VR1 ... variable resistors

Claims (4)

[Claims] 1. A liquid crystal display device comprising: an amplifier circuit for generating a counter electrode drive signal of a liquid crystal display device; and an overcurrent prevention circuit connected in series between the amplifier circuit and a power supply thereof. Counter electrode drive circuit. 2. The amplifying circuit comprises a push-pull circuit and includes an NPN transistor and a PNP transistor. The bases of the NPN transistor and the PNP transistor are connected together to input a polarity inversion signal. An emitter is connected together to generate the counter electrode drive signal. The overcurrent prevention circuit is connected to GND via a resistor, a collector connected to a collector of a PNP transistor of the push-pull circuit, and the power supply. 2. The counter electrode driving circuit according to claim 1, further comprising an NPN transistor having an emitter connected to the common electrode. 3. The counter electrode drive circuit according to claim 1, wherein said display device is an active matrix display device. 4. A counter electrode driving circuit used in an active matrix liquid crystal display device, comprising a protection circuit for preventing a malfunction of a transistor which occurs when a counter electrode signal output and a power supply are short-circuited. Electrode drive circuit.