JPH10261770A - Manufacture of semiconductor memory element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor memory element whose leakage current density is low wherein the surface of a lower electrode is made smooth and material quality of a high dielectric film or a ferroelectric film is stabilized. SOLUTION: After a selection transistor is formed in a silicon substrate 1, an interlayer insulating film is formed, and then a contact hole is formed. After polysilicon is buried, the surface is flattened by a CMP method, and a polysilicon plug 6 is formed. A titanium film and a titanium nitride film 7 are formed on the polysilicon plug 6. A lower electrode 8 of platinum is formed. By annealing the electrode 8, its surface is made smooth. As the result, the surface of the dielectric thin film on the platinum lower electrode 8 becomes smooth, and a leakage current of the dielectric thin film can be restrained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a semiconductor memory device, and more particularly to a method of manufacturing a semiconductor memory device having a dielectric film made of a ferroelectric film material or a high dielectric film material.

[0002]

2. Description of the Related Art In recent years, a semiconductor memory device using a high dielectric thin film having a larger dielectric constant than a silicon oxide film and a semiconductor memory device using a ferroelectric thin film having spontaneous polarization have been actively studied. I have. STO (SrTiO ₃ , strontium titanate), BSTO ((Ba, Sr) TiO ₃ , barium strontium titanate) and the like as a high dielectric material, and PZT (Pb (Zr, Ti) as a ferroelectric material O ₃ , lead zirconate titanate), PbTiO ₃ (lead titanate), BaTiO
₃ (Barium titanate), PLZT ((Pb, La)
(Zr, Ti) O ₃ , lead lanthanum zirconate titanate), Bi-based layered oxide (SrBi ₂ (Ta _X Nb ₁ -x) ₂
Oxides such as O ₉ ) and BTO (Bi ₄ Ti ₃ O ₁₂ ) are mainly used, and among them, PZT and Bi-based layered oxides have been energetically studied as the most promising materials for nonvolatile memories.

In a conventional semiconductor memory using a high dielectric film material or a ferroelectric material for a dielectric film of a capacitor, for example, as shown in FIG. 4 (e), a lower electrode 28, a dielectric film 29 and an upper A stack type structure in which a dielectric capacitor composed of the electrode 31 is formed on the selection transistor composed of the gate electrode 23 and the source / drain region 24 is adopted, and the memory cell region can be reduced and high integration can be achieved. In order to realize such a stack type structure, wiring 26 connecting the selection transistor and the dielectric capacitor is required.
Need to have a plug structure. In FIG. 4E, reference numeral 21 denotes a semiconductor substrate (for example, an n-type silicon substrate);
22 is a LOCOS oxide film for element isolation, 25, 30, 3
Reference numeral 2 denotes an interlayer insulating film; 27, a barrier metal for preventing the lower electrode 28 from reacting with a wiring having a plug structure;
Reference numerals 3 and 34 denote electrodes.

Conventionally, when forming a capacitor using PZT, PZT is formed immediately after the lower electrode is formed. In this case, since the morphology deteriorates due to the increase in the grain size of PZT, as shown in FIG.
It becomes about 10 ⁻⁴ A / cm ² (the leak current density needs to be 1.0 × 10 ⁻⁷ A / cm ² or less),
Cannot be used as a capacitor.

Next, a manufacturing process of a conventional semiconductor memory device will be described with reference to FIG.

First, a LOCOS oxide film 22 having a thickness of about 5000 ° is formed on the surface of a silicon substrate 21 to form an element isolation region. Next, after forming a selection transistor including the gate electrode 23, the source / drain region 24, and the like,
A first silicon oxide film 2 by an CVD method as an interlayer insulating film;
5 was formed into a film of about 5000 °
Is formed.

Next, after polysilicon is buried by the CVD method, the surface is flattened by the CMP method to form a polysilicon plug 26.

Next, on the polysilicon plug 26,
A titanium film having a thickness of 300 .ANG. Is formed by DC magnetron sputtering, and a titanium nitride film 27 having a thickness of 2000 .ANG. Is formed by magnetron reactive sputtering. Then, D
A platinum lower electrode 28 having a thickness of 1000 ° is formed by a C magnetron sputtering method.

Next, a film thickness of 200
A 0 ° PZT film 29 is formed. The method of forming the PZT film 29 is as follows. First, lead acetate, titanium (IV) isopropoxide and zirconium isopropoxide are respectively dissolved in Pb: Ti: Zr = 10 using 2-methoxyethanol as a solvent.
The sol-gel raw material solution was dissolved at a ratio of 0:52:48 to obtain a sol-gel raw material solution.
000 rpm, 150 ° C, 10
After the drying for minutes, the pre-sintering is performed at 400 ° C. for 30 minutes in the air. Thereafter, crystallization is performed at 600 to 650 ° C. for 30 minutes in a mixed atmosphere of nitrogen and oxygen. At this time, the flow rate ratio between nitrogen and oxygen is as follows: nitrogen flow rate / oxygen flow rate = 4
/ 1.

Next, the PZT film 29, the platinum lower electrode 28, and the titanium nitride film 27 are dry-etched by, for example,
It was processed to a size of 2.6 μm square. After that, a second silicon oxide film 30 is formed as an interlayer insulating film by using the CVD method, a contact hole is formed, and a platinum upper electrode 31 of the ferroelectric film capacitor is formed by DC magnetron sputtering at 1000 °. I do.

Next, the platinum upper electrode 31 is processed by a dry etching method using chlorine gas, a third silicon oxide film 32 is formed by a CVD method, and a contact hole is formed. An aluminum lead electrode 33 from the platinum upper electrode 31 of the body capacitor was formed by DC magnetron sputtering.

[0012]

In the process of forming a high-dielectric film or a ferroelectric film used for a dielectric capacitor, a temperature of 500.degree. C. is required to crystallize these to obtain a high dielectric constant or ferroelectricity. Processing in a high-temperature oxidizing atmosphere at 700 ° C. is indispensable. Since many of these high dielectric films or ferroelectric films have a crystal structure such as a perovskite structure, it is difficult to control their physical properties.

In the case of the method of manufacturing a capacitor shown in the prior art, giant grains are generated in a ferroelectric film such as PZT, and the surface of the PZT film becomes rough (morphology becomes rough). Therefore, the leakage current density is high. Possible causes are that the surface roughness of the lower electrode and the absence of an initial nuclear layer on the surface of the lower electrode.

According to the present invention, the surface of the lower electrode is smoothed,
It is an object of the present invention to provide a method for manufacturing a semiconductor memory device having a low leakage current density by stabilizing the physical properties of a high dielectric film or a ferroelectric film.

[0015]

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor memory device, comprising: a capacitor having a ferroelectric film or a high dielectric film between an upper electrode and a lower electrode; In a method for manufacturing a semiconductor memory device including an electrode and a transistor connected through a conductive plug, a conductive diffusion barrier layer is formed on the conductive plug, the lower electrode is formed, and then heat treatment is performed. The ferroelectric film or the high dielectric film is formed.

According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor memory device according to the first aspect, wherein the diffusion barrier layer is made of titanium nitride.

By performing the heat treatment of the lower electrode as described above, the surface of the lower electrode is smoothed, the physical properties of the high dielectric film or the ferroelectric film are stabilized, and the leak current density is reduced. Can be.

Further, according to the second aspect of the present invention, titanium diffused from the diffusion barrier layer is oxidized on the surface of the lower electrode to form an initial nucleus layer of a crystal such as titanium oxide. Since a high-dielectric film or a ferroelectric film grows at the center, a high-density high-dielectric film or the like is formed, and the leak current density can be further reduced.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail based on embodiments.

FIG. 1 is a view showing a manufacturing process of a semiconductor memory device according to one embodiment of the present invention, FIG. 2 is a diagram showing a relationship between a driving voltage and an electric displacement, and FIG. FIG. In FIG. 1, 1 is an n-type silicon substrate, 2 is a LOCOS oxide film formed on the surface of the n-type silicon substrate for element isolation, 3 is a gate electrode, and 4 is a source / source electrode.
A drain region, 5 is a first silicon oxide film formed as an interlayer insulating film on the silicon substrate 1, 6 is a polysilicon plug formed to make contact between the silicon substrate 1 and the platinum lower electrode, and 7 is a polysilicon plug. A titanium film and a titanium nitride film formed as diffusion barrier layers on the silicon plug 6; 8 a platinum lower electrode formed on the titanium nitride film;
Is a ferroelectric thin film formed on the platinum lower electrode 8.
The ZT film, 10 is a second silicon oxide film formed as an interlayer insulating film, 11 is a platinum upper electrode formed on the PZT film 9, 12 is a third silicon oxide film, and 13 is a platinum upper electrode 11. A first aluminum lead electrode 14 formed for taking contact is a second aluminum lead electrode formed for taking contact with the n-type silicon substrate 1. In the present embodiment, n
The following describes the type silicon substrate, but the same applies to the case where a P type silicon substrate is used.

Hereinafter, a manufacturing process of a semiconductor memory device according to an embodiment of the present invention will be described with reference to FIG.

First, a film having a thickness of about 5
An LOCOS oxide film 2 of 2,000 ° is formed to form an element isolation region. Next, after forming a selection transistor including the gate electrode 3 and the source / drain regions 4 and the like, a first silicon oxide film 5 is formed as an interlayer insulating film by CVD.
Then, a contact hole having a diameter of 0.5 μm is formed.

Next, after polysilicon is buried by the CVD method, the surface is flattened by the CMP method to form a polysilicon plug 6.

Next, on this polysilicon plug 6, D
A titanium film having a thickness of 300 mm is formed by a C magnetron sputtering method, and a titanium film having a thickness of 2 mm is further formed by a magnetron reactive sputtering method.
A titanium nitride film 7 having a thickness of Å is formed. Subsequently, a platinum lower electrode 8 having a film thickness of 1000 ° is formed by DC magnetron sputtering.

In the present invention, the following steps are performed after the formation of the platinum electrode. That is, annealing of the platinum lower electrode 8 is performed at a temperature of 500 ° C. to 700 ° C. for 30 minutes in an inert gas atmosphere. At this time, when heat treatment is performed using oxygen, an inert gas is used because the diffusion barrier layer and the like are oxidized. By changing the time, temperature, and atmosphere, the characteristics of the dielectric thin film are variously changed. For example, by annealing at 550 ° C. for 30 minutes in a nitrogen atmosphere, the surface of the platinum lower electrode 8 is smoothed. As a result, the surface of the dielectric thin film on the platinum lower electrode 8 becomes smooth, and the dielectric thin film leaks. The current can be suppressed.

When the heat treatment temperature is lower than 500 ° C. or higher than 700 ° C., the morphology becomes poor. When the heat treatment of the platinum lower electrode 8 is not performed, the grain size of the PZT film becomes 1 to ² μm and the leak current density becomes 10 ⁻⁴ A / cm ^2. Becomes fine crystal grains of about 100 °, and the leak current density thereof is 10 ⁻⁷ A / cm ² or less.

Next, using a sol-gel method, a film thickness of 200
A 0 ° PZT film 9 is formed. The method of forming the PZT film 9 is as follows. First, using 2-methoxyethanol as a solvent, lead acetate, titanium (IV) isopropoxide, and zirconium isopropoxide are respectively Pb: Ti: Zr = 100:
The sol-gel raw material solution was dissolved at a ratio of 52:48, and this raw material solution was rotated at 30 rpm using a spinner.
After applying at 00 rpm and drying at 150 ° C. for 10 minutes in the air, temporary sintering is performed at 400 ° C. for 30 minutes in the air. Thereafter, at 600 to 650 ° C. for 30 minutes,
Crystallization is performed in a mixed atmosphere of nitrogen and oxygen. At this time, the flow rate ratio between nitrogen and oxygen is as follows: nitrogen flow rate / oxygen flow rate = 4/1.
And

Next, the PZT film 9, the platinum lower electrode 8, and the titanium nitride film 7 are dry-etched to, for example, 2.6 μm.
It was processed to the size of m square. Then, as an interlayer insulating film,
After the second silicon oxide film 10 is formed by using the CVD method, a contact hole is formed, and the platinum upper electrode 11 of the ferroelectric film capacitor is formed by DC magnetron sputtering at 1000 °.

Next, the platinum upper electrode 11 is processed by a dry etching method using chlorine gas, a third silicon oxide film 12 is formed by a CVD method, and a contact hole is formed. An aluminum lead electrode 13 from the platinum upper electrode 11 of the body capacitor was formed by DC magnetron sputtering.

By applying a triangular wave between the aluminum extraction electrode 13 from the platinum upper electrode 11 and the aluminum extraction electrode 14 from the silicon substrate 1 of the capacitor having the ferroelectric film formed by the above-described process, The hysteresis loop shown in FIG. 2 was obtained. The applied triangular wave was 5 V and the frequency was 75 Hz.
As shown in FIG. 2, a ferroelectric property large enough to be used as a ferroelectric capacitor is obtained. The leakage current density of the capacitor is 9.1 × at 5 V as shown in FIG.
10 ⁻⁸ A / cm ^2, which is small enough to be used as a capacitor.

In the above embodiment, the sol-gel method is used as the method of forming the dielectric film.
A method such as a reactive magnetron sputtering method or a MOCVD method may be used. In the present embodiment, a PZT film is used as the ferroelectric thin film, but PbTiO ₃ ,
_{(Pb X La 1-X)} TiO 3, (Pb X La 1-X) (Zr Y T
i _1-Y ) O ₃ , Bi ₄ Ti ₃ O ₁₂ , BaTiO ₃ , BaMg
F ₄ , LiNbO ₃ , LiTaO ₃ , SrBi ₂ Ti ₂ O ₉ ,
YMnO ₃ , Sr ₂ Nb ₂ O ₇ , SrBi ₂ (Ta _X N
b _1-X ) ₂ O ₉ , Bi ₄ Ti ₃ O _12, etc., and (Ba _X Sr ₁ -x) TiO ₃ , SrB
In the case of i ₄ Ti ₄ O _{15 and the} like, similarly, a sufficient ferroelectric film,
Alternatively, the control or effect of the high dielectric film can be obtained.

Further, in the present embodiment, platinum is used as the material of the lower electrode. However, the same applies when other metals, nitrides, or conductive oxides such as RuO ₂ and IrO ₂ are used. The effect is obtained.

[0033]

As described above in detail, by using the present invention, the morphology of a ferroelectric film or a high dielectric film can be smoothed, and a titanium nitride film can be used as a diffusion barrier film. If used, an initial nucleus layer is formed. As a result, a semiconductor memory device having a ferroelectric film or a high-dielectric film having a low leakage current density can be manufactured.

[Brief description of the drawings]

FIG. 1 is a manufacturing process diagram of a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a relationship between a driving voltage and an electric displacement.

FIG. 3 is a diagram showing a relationship between a driving voltage and a leakage current density when the present invention is used.

FIG. 4 is a manufacturing process diagram of a conventional semiconductor memory device.

FIG. 5 is a diagram showing a relationship between a driving voltage and a leakage current density when a conventional technique is used.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 n-type silicon substrate 2 locos oxide film 3 gate electrode 4 source / drain region 5 first silicon oxide film 6 polysilicon plug 7 titanium film and titanium nitride film 8 platinum lower electrode 9 PZT film 10 second silicon oxide film 11 Platinum upper electrode 12 Third silicon oxide film 13 First aluminum extraction electrode 14 Second aluminum extraction electrode

Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 29/792

Claims (2)

[Claims] 1. A method of manufacturing a semiconductor memory device comprising: a capacitor having a ferroelectric film or a high dielectric film between an upper electrode and a lower electrode; and a transistor connected to the lower electrode through a conductive plug. Forming a conductive diffusion barrier layer on the conductive plug, forming the lower electrode, flattening the lower electrode surface by heat treatment, and then forming the ferroelectric film or the high dielectric film. Forming a semiconductor memory device. 2. The method according to claim 1, wherein said diffusion barrier layer is titanium nitride.