JP2000311989A - Ferroelectric capacitor element and nonvolatile semiconductor memory element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase fabrication yield of nonvolatile semiconductor elements, i.e., capacitor elements comprising an Ir film or a composite film of IrO2/Ir, by providing a film for preventing oxidation and deposition of a lower electrode between a ferroelectric film and the lower electrode thereby suppressing deposition of IrO2. SOLUTION: A lower electrode 2 is formed of an Ir film on a substrate 1, and a deposition preventive film 3 for preventing deposition of lower electrode material and oxidizing the lower electrode uniformly is formed on the lower electrode 2 by subjecting SrTi0.9Nb0.1O3(STNO) to heat treatment for crystallization, for example. Subsequently, a ferroelectric film 4, for example, structured of layered bismuth compound, SrBi2(Ta1-xNbx)2O9 (0<=x<=1) (SBT) is formed on the deposition preventive film 3, and an upper electrode 5 is formed thereon. The deposition preventive film 3 can prevent uneven oxidation of Ir composing the lower electrode 2 and phenomenon where IrO2 is deposited on an SBT film during heat treatment for crystallization.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ferroelectric capacitor device and a nonvolatile semiconductor memory device provided with the ferroelectric capacitor device.

[0002]

2. Description of the Related Art A conventional non-volatile semiconductor memory device,
The read time of an EPROM, an EEPROM, a flash memory or the like is comparable to that of a DRAM, but the write time is long and high-speed operation cannot be expected. On the other hand, a non-volatile semiconductor storage element including a ferroelectric capacitor element is a non-volatile semiconductor storage element that is comparable to a DRAM in both reading and writing and can be expected to operate at high speed. The structure of the device is generally such that one selection transistor and one ferroelectric capacitor element (one transistor / one capacitor), or one cell is composed of two selection transistors and two ferroelectric capacitor elements.

[0003] Strength is typical to _{Pb (Zn 1-x Ti x} ) O 3 as a ferroelectric material used for the ferroelectric capacitor element, but in this material, a driving voltage is as high as about 5V, also, fatigue There is a problem that resistance is poor. 3
SrBi ₂ Ta ₂ O ₉ (hereinafter referred to as “SBT”), which can be driven at a low voltage of not more than V and has excellent fatigue characteristics, or SrBi ₂ (Ta ₁ -xN) in which Ta is partially substituted with Nb.
b _x ) O ₉ has attracted attention and is being actively studied.

[0004] This material is obtained by the MOD method, the sol-gel method, the MO method.
In any of the formation methods such as the CVD method and the sputtering method, it is necessary to crystallize the ferroelectric by a heat treatment in an oxygen-containing atmosphere at a high temperature of usually about 700 to 800 ° C.

However, such a heat treatment in a high-temperature oxygen-containing atmosphere is not so problematic in a ferroelectric capacitor element having a relatively low degree of integration in a planar structure. in stacked structure is essential to, TiN and Ta _x Si _{1 -x} N for preventing the diffusion of the elements constituting the lower electrode of Pt or the like into the polysilicon plug buried diffusion region of the switching transistor _When oxidation of the diffusion barrier film such as _y occurs, conduction between the plug and the lower electrode stops,
There is a problem that the diffusion barrier film expands and peels off.

As one method for solving such a problem, it is effective to form an electrode material having excellent oxidation resistance on the diffusion barrier film. In particular, Ir is a material that is extremely excellent in oxidation resistance in heat treatment in a high-temperature oxygen-containing atmosphere.
It is possible to sufficiently suppress oxidation of the diffusion barrier film, the polysilicon plug, and the like. By using this Ir as the lower electrode of the ferroelectric capacitor element, for example, by adopting the structure shown in FIG. 8, which is a configuration diagram of a conventional ferroelectric capacitor element, a ferroelectric capacitor excellent in heat resistance or oxidation resistance can be obtained. An element can be obtained. In FIG. 8, 31 is a silicon substrate, 32 is a polysilicon plug, 33 is Ta1 _-x.
Si _x N _y diffusion barrier layer, 34 is Ir lower electrode, 35 is S
An rBi ₂ Ta ₂ O ₉ film, 36 is a Pt upper electrode, and 37 is an interlayer insulating film.

[0007]

However, although Ir can sufficiently suppress the permeation of oxygen, the material itself is very susceptible to oxidation, so that Ir is subjected to a heat treatment in an oxygen-containing atmosphere to crystallize the SBT film. , 0.5 μm ² to 10
A precipitate of IrO ₂ of about μm ² is generated on the SBT film.
This phenomenon occurs when the grain size of the SBT film is 50 nm to 2 nm.
Since it is as large as about 00 nm and the morphology is very coarse, a large amount of oxygen enters from the grain boundaries of the grains. As a result, Ir is strongly oxidized at the grain boundaries, and the oxidized and expanded IrO ₂ becomes the grain grains of the SBT film. It is thought to be caused by deposition on the film surface through the field.

Further, the Ir surface is previously covered with IrO ₂ , and the Ir surface is formed to suppress the roughness due to oxidation of the Ir surface. Then, by forming an SBT film, the precipitation of IrO ₂ during crystallization of the SBT film is suppressed. Although a method may be considered, IrO ₂ covering the Ir surface is not completely oxidized, and if there is a non-uniform portion in part, IrO ₂ grows from the SBT film at the time of crystallization, and the SBT film grows. Will be connected.

In general, the morphology of a bismuth-based layered ferroelectric film is poor, and when a bismuth-based layered ferroelectric film is formed on Ir or IrO ₂ , the above-described precipitation of IrO ₂ occurs. Such precipitates cause defects in the ferroelectric capacitor element, which significantly lowers the yield.

[0010]

According to a first aspect of the present invention, there is provided a ferroelectric capacitor element comprising an Ir film or an IrO ₂ / I
In a capacitor element having a lower electrode, a ferroelectric film and an upper electrode comprising a composite film of r, a deposition preventing film for preventing oxidation and deposition of the lower electrode is provided between the ferroelectric film and the lower electrode. It is characterized by having.

Further, the ferroelectric capacitor element according to the present invention according to the second aspect is the ferroelectric capacitor element according to the first aspect, wherein the deposition preventing film is an oxide.

The ferroelectric capacitor element according to a third aspect of the present invention is the ferroelectric capacitor element according to the second aspect, wherein the deposition preventing film has a perovskite structure.

The ferroelectric capacitor element according to the present invention as set forth in claim 4 is characterized in that the deposition preventing film has conductivity. It is a capacitor element.

According to a fifth aspect of the present invention, in the ferroelectric capacitor element according to the present invention, the anti-precipitation film is formed of AB _1-x Nb _x O
_{3, C 1-x D x} EO 3 or formed by _{FRuO 3 (0 ≦ x ≦ 1} ),, of which, A is Pb, Sr, Ba, C
a and Mg, B is Ti, Zr, H
selected from the group comprising f, Mn, Fe, Co and Ni;
C is selected from the group comprising Y, La and Sc; D is S
r, Ba, Ca and Mg, wherein E is T
5. The ferroelectric capacitor element according to claim 1, wherein the ferroelectric capacitor element is selected from a group including i, Hf, Mn, Fe, Co, and Ni.

Further, in the ferroelectric capacitor element according to the present invention, the ferroelectric film is a bismuth-based layered structure ferroelectric film. 3. The ferroelectric capacitor element according to any one of 1. to 1.,

Further, in the nonvolatile semiconductor memory device according to the present invention, the source region or the drain region of the select transistor formed on the semiconductor substrate and the interlayer formed so as to cover the semiconductor substrate and the select transistor. Nonvolatile comprising a contact plug buried in a contact hole formed in an insulating film or a ferroelectric capacitor element comprising a lower electrode, a ferroelectric film, and an upper electrode formed via the contact plug and a diffusion barrier film In a semiconductor device, the ferroelectric capacitor device is a ferroelectric capacitor according to any one of claims 1 to 6.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, based on one embodiment,
The ferroelectric capacitor element and the nonvolatile semiconductor memory element of the present invention will be described in detail.

FIG. 1 is a configuration diagram of a ferroelectric capacitor according to a first embodiment of the present invention, FIG. 2 is a configuration diagram of a ferroelectric capacitor according to a second embodiment of the present invention, and FIG. FIG. 4 is a configuration diagram of the nonvolatile semiconductor memory element of the present invention, FIG. 5 is a view showing the number of foreign substances generated on the wafer surface in the first embodiment of the present invention, FIG. FIG. 7 is a diagram showing the number of foreign substances generated on the wafer surface in the second embodiment of the present invention, and FIG. 7 is a diagram showing the hysteresis characteristics of the ferroelectric capacitor of the first embodiment of the present invention. 1 to 3, reference numeral 1 denotes an SiO ₂ / Si substrate, and reference numerals ₂ and 19 denote Ir.
Films, 3, 20 deposition prevention film (STNO film), 4, 21 are ferroelectric films (SBT film), 5, 22 are Pt films, 6 is IrO
₂ film, 11 is a silicon substrate, 12 is an insulating film for element isolation,
13, 14 are impurity diffusion layers, 15 is a gate portion of a switching transistor, 16 is a first interlayer insulating film, 17 is a polysilicon plug, 18 is a TaSiN film, and 23 is Ti
O ₂ film, 24 is a second interlayer insulating film, 25 is a drive line,
26 is a third interlayer insulating film, and 27 is a bit line.

The substrate 1 used for the ferroelectric capacitor or the nonvolatile semiconductor memory device provided with the ferroelectric capacitor according to the present invention is not particularly limited as long as it can be used as a substrate for an ordinary semiconductor device or integrated circuit. Although not limited, a silicon substrate is desirable, and
A semiconductor element, a wiring, an interlayer insulating film, or the like may be formed on a silicon substrate.

When forming the ferroelectric capacitor element of the present invention, first, a lower electrode 2 made of an Ir thin film is formed on a substrate 1. The formation method is a sputtering method, a CVD method,
An EB evaporation method or the like is used.

Next, a deposition prevention film 3 for preventing deposition of the lower electrode material is formed on the lower electrode 2. Since the deposition prevention film 3 is required to prevent uneven intrusion of oxygen into the lower electrode 2 and uniformly oxidize the lower electrode, an oxide thin film having a flat and dense morphology of the film is desirable. Since the oxide thin film needs to improve the crystallinity of a ferroelectric, which is a material having a perovskite structure formed immediately above, and to draw out good ferroelectric characteristics, the oxide thin film must be an oxide having a perovskite structure. Is desirable. Further, it is desirable that the perovskite oxide has conductivity in order to sufficiently apply the voltage applied to the capacitor to the ferroelectric itself.

For example, AB _{1 -x} Nb _x O ₃ (0 ≦ x ≦ 1) (A is P
It is selected from b, Sr, Ba, Ca, and Mg. B is selected from Ti, Zr, Hf, Mn, Fe, Co, and Ni. ) Or C _1-x
D _x EO ₃ (0 ≦ x ≦ 1) (C is selected from among Y, La, Sc. D is selected from among Sr, Ba, Ca, Mg. E is Ti, Hf, Mn, Fe, C
o or Ni. ) Or FRuO ₃ (F is selected from Sr, Ba, Ca, and Mg).

The thickness of the deposition preventing film 3 is 10 nm to 2 nm.
Desirably, it is 00 nm. If the thickness is less than 10 nm, the film becomes island-shaped, and the penetration of oxygen into the lower electrode 2 becomes non-uniform, so that Ir is oxidized non-uniformly and IrO ₂ is easily deposited. On the other hand, if the thickness is more than 200 nm, the film thickness of the entire capacitor portion becomes large, and there is a problem in processing accuracy at the time of fine processing.

Thereafter, a ferroelectric film 4 is formed on the deposition preventing film 3. The ferroelectric film 4 is a bismuth-based layered compound, for example, SrBi ₂ (Ta _1-x Nb _x ) ₂ O ₉
(0 ≦ x ≦ 1), BaBi ₂ Nb ₂ O ₉ , BaBi ₂ Ta ₂
O ₉ , PbBi ₂ Nb ₂ O ₉ , PbBi ₂ Ta ₂ O ₉ , Bi ₄ T
i ₃ O ₁₂ , PbBi ₄ Ti ₄ O ₁₅ , SrBi ₄ Ti ₄ O ₁₅ ,
BaBi ₄ Ti ₄ O ₁₅ , Sr ₂ Bi ₄ Ti ₅ O ₁₈ , Ba ₂ Bi
_{4 Ti 5 O 18, Pb 2} Bi 4 Ti 5 O 18, Na 0.5 Bi 4.5 T
i ₄ O ₁₅ , K _0.5 Bi _4.5 Ti ₄ O _{15 and the} like. Among them, SrBi ₂ (Ta _1-x Nb _x ) ₂ O ₉ (0 ≦ x ≦
1) is preferred. These ferroelectric films 4 are formed on the substrate 1 by a sol-gel method or MOD (Metal Organic).
(Decomposition) method or the like,
It is formed by a method selected from MOCVD, sputtering, EB evaporation, laser ablation, and the like.

For example, in the coating film forming method, an organic solvent containing a salt or a metal alkoxide of some of the elements constituting the ferroelectric film 4 and an organic solvent containing a salt or a metal alkoxide of another element are used. Are mixed to form a raw material solution, and this raw material solution is applied in a single application to a film thickness of about 20 to 100 nm by spin coating or the like.
A drying process at about 0 to 300 ° C. is performed. After that, 500 ~
Preliminary heat treatment at about 600 ° C. and heat treatment at about 650 to 800 ° C. for crystallization of the ferroelectric film are performed in an oxygen atmosphere, an oxygen-nitrogen mixed atmosphere, or a nitrogen atmosphere.

The upper electrode 5 formed on the ferroelectric film 4 is made of a metal film such as Pt, Ir, Ru, or the like.
It is made of a conductive oxide film such as O ₂ , RuO ₂ , La _1-x Sr _x CoO ₃ , SrRuO ₃ , or a composite film thereof. As a forming method, a sputtering method, a CVD method, an EB evaporation method, or the like is used.

If the ferroelectric capacitor element is configured as described above, the deposition preventing film 3 forms the Ir
Can be prevented, and the phenomenon that IrO ₂ precipitates on the SBT film during the crystallization heat treatment of the ferroelectric film 4 made of the SBT film can be suppressed. The lower electrode 2 may be an IrO ₂ / Ir composite film in which an IrO ₂ film is laminated on an Ir film as shown in FIG.

If a composite film of IrO ₂ / Ir is used,
Since the rO ₂ film is formed, precipitation due to oxidation of Ir during SBT crystallization can be reduced. Further, by providing a deposition prevention film, the precipitation of IrO ₂ can be effectively suppressed. (First Embodiment) First, a thermal oxide film (SiO ₂ , 400 nm thick) having a thickness of 400 nm is formed on a silicon substrate by heat treatment at 1050 ° C. for 40 minutes in an oxygen atmosphere containing water vapor.
(Not shown). Thereafter, an Ir lower electrode 2 having a film thickness of 200 nm was formed on the SiO ₂ / Si substrate 1 by DC magnetron sputtering at a DC power of 0.5 kW, a substrate temperature of 500 ° C., and an Ar gas pressure of 0.6 Pa. . Next, SrTi _0.9 N is applied to the Ir lower electrode 2.
A sol-gel solution of b _0.1 O ₃ (hereinafter referred to as “STNO”) was applied, and a drying step at 150 ° C. for 5 minutes and a preliminary firing at 400 ° C. for 10 minutes in a normal pressure oxygen atmosphere were repeated twice. . Thereafter, crystallization heat treatment was performed at 600 ° C. for 30 minutes in an atmospheric oxygen atmosphere to form a 40 nm-thick STNO film 3 serving as a deposition prevention film.

Next, a MOD solution of an SBT film as a ferroelectric film is applied on the STNO film 3 in a thickness of about 50 nm, and a drying process is performed at 250 ° C. for 5 minutes. The SBT film was crystallized by a heat treatment at a substrate temperature of 700 ° C. for 30 minutes. This application, drying,
By repeating the crystallization process four times, a film thickness of 200
The SBT film 4 of nm was formed.

With respect to the film having the above structure, IrO ₂
In order to examine the effect of suppressing deposition, a sample having an SBT / Ir structure in which an SBT film 4 was formed immediately above the Ir lower electrode 2 under the same conditions as the above-described film without forming a deposition prevention film was prepared, and a foreign matter inspection machine was used. The number of relics on the surface of the 6-inch wafer was measured and compared with that of the SBT / STNO / Ir structure having a deposition preventing film. The result is shown in FIG. In the sample of the SBT / Ir structure, the foreign matter is 200 to 300 for each size.
SBT / S
In the case of the TNO / Ir structure, the number was 300 or less for each size. The generated foreign matter is collected by EPMA (Electro
As a result of analyzing constituent elements by n Probe Micro Analysis, it was found that the element was IrO ₂ , and it was confirmed that the element was deposited from the Ir lower electrode 2. Therefore, it was demonstrated that the deposition was suppressed by providing the STNO film 3.

Next, Pt, DC power of 2 kW, substrate temperature of 500 ° C., and Ar gas pressure of 0.
67 Pa, formed by a DC magnetron sputtering method, and further processed by a known dry etching method to form Pt.
The upper electrode 5 was used. An ECR etcher was used for dry etching, and the gas used was a mixed gas of C ₂ F ₆ , CHF ₃ and Cl ₂ . Thereafter, the substrate temperature is set to 400 ° C. and 30 ° C. in an atmospheric oxygen atmosphere for the purpose of suppressing the leakage current.
A minute heat treatment was applied.

The upper electrode area of the ferroelectric capacitor manufactured by the above-described method was set to 1 × 10 ⁻⁴ cm ² . FIG. 7 shows the hysteresis characteristics of this ferroelectric capacitor. Ferroelectric characteristics: Pr = 13.2 μC / c when ± 3 V is applied
m ² and Ec = 45 kV / cm. The leakage current density when +3 V was applied was 5 × 10 ⁻⁸ A / cm ² . Thus, the capacitor in the first embodiment is
On the STNO film 3, which is a perovskite-type oxide,
Since the BT film 4 is formed, the crystallinity of the SBT film 4 is good, and since the STNO film 3 has conductivity,
Almost all the voltage applied between the Pt upper electrode 5 and the Ir lower electrode 2 of the capacitor is applied to the SBT film 4, and good ferroelectric characteristics can be obtained.

Further, in the first embodiment, STNO was used for the deposition prevention film, but AB _1-x Nb _x O ₃ (0
≦ x ≦ 1 (A is selected from Pb, Sr, Ba, Ca, Mg. B is Ti, Zr, Hf, Mn, F
e, Co, or Ni. ) Or C _1-x D _x EO ₃ (0 ≦ x ≦ 1) (C is Y,
It is selected from La and Sc. D is Sr, B
a, Ca, or Mg. E is Ti,
It is selected from Hf, Mn, Fe, Co, and Ni. )
Or FRuO ₃ (F is Sr, B
a, Ca, or Mg. The same effect can be obtained with (). Also, instead of the SBT film, SrBi
The same effect can be obtained with ₂ (Ta _1-x Nb _x ) O ₉ (0 ≦ x ≦ 1). (Second Embodiment) First, a thermal oxide film (SiO ₂ , 400 nm thick) is formed on a silicon substrate by heat treatment at 1050 ° C. for 40 minutes in an oxygen atmosphere containing water vapor.
(Not shown). Then, DC power is set to 0.5 kW, substrate temperature is set to 500 ° C., Ar gas pressure is set to 0.6 Pa on the SiO ₂ / Si substrate 1 by DC magnetron sputtering.
An r film 2 was formed.

Next, a DC power of 0.5 kW, a substrate temperature of 500 ° C., an Ar / O ₂ mixed gas pressure of 0.6 Pa, and a lower electrode having a thickness of 300 nm were formed on the Ir lower electrode by DC magnetron sputtering. An IrO ₂ film 6 was formed.

Next, a sol-gel solution of STNO is applied on the IrO ₂ film 6, and a drying step at 150 ° C. for 5 minutes and a preliminary firing at 400 ° C. for 10 minutes in a normal pressure oxygen atmosphere are performed. Repeated. Then, in an atmospheric oxygen atmosphere, 600
Crystallization heat treatment for 30 minutes at 40 ° C.
The TNO film 3 was formed.

Next, on the STNO film 3, an MOD solution of an SBT film as a ferroelectric material is applied in a thickness of about 50 nm, and
After performing a drying process at 250 ° C. for 5 minutes, the SBT film was crystallized by a heat treatment at a substrate temperature of 700 ° C. for 30 minutes in an atmospheric oxygen atmosphere. By repeating the steps of coating, drying and crystallization four times, a film thickness of 200 nm
Was formed.

With respect to the film having the above structure, IrO ₂
In order to examine the effect of suppressing deposition, a sample having an SBT / IrO ₂ / Ir structure in which an SBT film was formed directly on the IrO ₂ film under the same conditions as the above-mentioned film without forming a deposition prevention film was prepared.
The number of relics on the surface of the 6-inch wafer is measured by a foreign matter inspection device, and SBT / STNO / IrO ₂ with a deposition prevention film
/ Ir structure. FIG. 6 shows the result.
In the sample having the SBT / IrO ₂ / Ir structure, foreign matter is distributed in the range of about 200 to 2000 particles for each size, whereas in the sample having the SBT / STNO / IrO ₂ / Ir structure, the size is 200 Or less. As a result of analyzing constituent elements of the generated foreign matter by EPMA,
It was found to be rO ₂ , which was confirmed to be precipitation from the lower electrode. Therefore, it was demonstrated that the deposition was suppressed by providing the STNO film 3.

Next, Pt, DC power of 2 kW, substrate temperature of 500 ° C., and Ar gas pressure of 0.2 μm are formed on the SBT film 4.
The upper Pt electrode 5 was formed by a DC magnetron sputtering method at 67 Pa and further processed by a known dry etching method. An ECR etcher was used for dry etching, and the gas used was a mixed gas of C ₂ F ₆ , CHF ₃ and Cl ₂ . Thereafter, the substrate temperature is set to 400 ° C. and 30 ° C. in an atmospheric oxygen atmosphere for the purpose of suppressing the leakage current.
A minute heat treatment was applied.

The area of the upper electrode of the ferroelectric capacitor manufactured by the above method was set to 1 × 10 ⁻⁴ cm ² . The ferroelectric characteristics were as follows: when applying ± 3 V, Pr = 13.2 μC / cm ² , E
c = 45 kV / cm. The leakage current density when +3 V was applied was 5 × 10 ⁻⁸ A / cm ² . As described above, in the capacitor according to the first embodiment, since the SBT film 4 is formed on the STNO film 3 which is a perovskite-type oxide, the SBT film has good crystallinity.
Since the STNO film 3 has conductivity, almost all of the voltage applied between the Pt upper electrode and the IrO ₂ / Ir lower electrode of the capacitor is applied to the SBT film 4, and good ferroelectric characteristics can be obtained.

Further, in the first embodiment, STNO was used for the deposition prevention film, but AB _1-x Nb _x O ₃ (0
≦ x ≦ 1 (A is selected from Pb, Sr, Ba, Ca, Mg. B is Ti, Zr, Hf, Mn, F
e, Co, or Ni. ) Or C _1-x D _x EO ₃ (0 ≦ x ≦ 1) (C is Y,
It is selected from La and Sc. D is Sr, B
a, Ca, or Mg. E is Ti,
It is selected from Hf, Mn, Fe, Co, and Ni. )
Or FRuO ₃ (F is Sr, B
a, Ca, or Mg. The same effect can be obtained with (). Also, instead of the SBT film, SrBi
The same effect can be obtained with ₂ (Ta _1-x Nb _x ) O ₉ (0 ≦ x ≦ 1). (Third Embodiment) First, as shown in FIG. 3A, a switching transistor is formed by a known MOSFET forming process, and an NSG (Non-doped Silicon) is formed.
After covering with a first interlayer insulating film 16 made of ateGlass, a contact hole is formed on the impurity diffusion layer 13 serving as a source or drain region of the switching transistor by using a known photolithography method and a dry etching method. After the impurity-doped polysilicon is buried in the contact hole, a known CMP (Chemic) is used.
The first interlayer insulating film 16 and the polysilicon plug 1 are formed by an Al Mechanical Polishing method.
7 surfaces were flattened. In FIG. 3, reference numeral 11 denotes a silicon substrate, 12 denotes an element isolation insulating film, 14 denotes an impurity diffusion layer serving as a source or drain region of the switching transistor, and 15 denotes a gate of the switching transistor.

Next, Ta _x Si _1-x N to be a diffusion barrier film
_y (0.2 ≦ x ≦ 1, 0 ≦ y ≦ 1, hereinafter “TaSiN”
The film 18 has a thickness of 5 by a known sputtering method.
After the formation of 0 nm, the Ir film 19 serving as the lower electrode, the STNO film 20 serving as the deposition preventing film,
A BT film 21 and a Pt film 22 serving as an upper electrode were sequentially formed to have a thickness of 200 nm, 40 nm, 200 nm, and 100 nm, respectively.

Next, the Pt film 22 was processed to have a size of 1.7 μm square using known photolithography and dry etching. Then, at a substrate temperature of 400 ° C. in a normal pressure oxygen atmosphere for stabilizing the leak current characteristic,
A 0 minute heat treatment was applied.

Next, the SBT film 21, STNO film 20, I
The r film 19 and the TaSiN film 18 were processed into a size of 2.0 μm square by using a known photolithography method and a dry etching method to obtain a shape as shown in FIG. 3B. Use ECR etcher for dry etching,
The gas type used was SBT film 21 and STNO film 20 of Ar.
/ Cl ₂ / CF ₄ mixed gas, Ir film 19 is C ₂ F ₆ / CH
The mixed gas of F ₃ / Cl ₂ and the TaSiN film 18 are formed of Cl ₂ / C ₂
A mixed gas of F ₆ was used.

Next, a 30 nm-thick TiO ₂ barrier insulating film 23 is formed by a known sputtering method, and then a 150 nm-thick silicon oxide film is formed as a second interlayer insulating film 24 by a known CVD method. And then the Pt film 22
A contact hole of 1.2 μm square was formed in the upper second interlayer insulating film 24 by using a known photolithography method and a dry etching method, to obtain a structure as shown in FIG.

Next, as shown in FIG. 3D, an Al film having a thickness of 400 nm is formed, and is processed by a known photolithography method and a dry etching method to form a drive line 25. Heat treatment was performed at 400 ° C. for 30 minutes in a pressure nitrogen atmosphere to stabilize the electrode interface. afterwards,
A third interlayer insulating film 26 is formed using a known CVD method, and a contact hole is formed on the other impurity diffusion region 14 of the switching transistor using a known photolithography method and a dry etching method. Then, as shown in FIG. 4, the bit line 27 was formed by using a known Al wiring technique, and a nonvolatile semiconductor memory device having a ferroelectric capacitor was completed.

When the ferroelectric characteristics of the ferroelectric memory cell manufactured in this manner were measured, values of Pr = 10.5 μC / cm ² and Ec = 45 kV / cm ² were obtained at an applied voltage of ± 3 V. As a result, sufficient operation as a ferroelectric capacitor was confirmed.

Next, the leak current density of the ferroelectric memory cell was measured. The leak current density at an applied voltage of +3 V is 5 × 10 ⁻⁸ cm ² , and the applied voltage is +10
Since no dielectric breakdown occurred at V, sufficient characteristics as a ferroelectric capacitor were confirmed.

In the embodiment, the diffusion barrier film is made of Ta.
_{Although x} Si _1-x N _y is used, G _x Si _1-x N _y , G
_x Al _1-x N _y , GN _z (0.2 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0
≤ z ≤ 1). Where G is Ti, Zr,
Hf, V, Nb, Ta, Cr, Mo, W, Ru, Os,
It shall be selected from Co, Rh, Ir, Ni, Pb, and Pt. In addition, although the lower electrode of the ferroelectric capacitor is made of Ir, it may be made of an IrO ₂ / Ir composite film.

Further, in the third embodiment, STNO was used for the deposition prevention film, but AB _1-x Nb _x O ₃ (0
≦ x ≦ 1 (A is selected from Pb, Sr, Ba, Ca, Mg. B is Ti, Zr, Hf, Mn, F
e, Co, or Ni. ) Or C _1-x D _x EO ₃ (0 ≦ x ≦ 1) (C is Y,
It is selected from La and Sc. D is Sr, B
a, Ca, or Mg. E is Ti,
It is selected from Hf, Mn, Fe, Co, and Ni. )
Or FRuO ₃ (F is Sr, B
a, Ca, or Mg. The same effect can be obtained with (). Also, instead of the SBT film, SrBi
The same effect can be obtained with ₂ (Ta _1-x Nb _x ) O ₉ (0 ≦ x ≦ 1).

As a comparative example of the third embodiment, a ferroelectric memory cell of the above-described ferroelectric memory cell having a structure without a deposition preventing film was also manufactured. The ferroelectric characteristics of each of the 1000 ferroelectric memory cells provided with these deposition prevention films and the ferroelectric memory cells not provided were measured,
The proportion of cells whose characteristics could not be measured due to defects or the like was compared. As a result, in a memory cell without a deposition prevention film,
The number of cells in which the ferroelectric characteristics could not be measured was 325, whereas the number of cells provided with the deposition prevention film was 12. As described above, the effect of suppressing the deposition of IrO ₂ by the deposition preventing film and reducing cell defects was obtained.

[0051]

As described in detail above, the use of the present invention suppresses the precipitation of IrO ₂ and improves the yield of the nonvolatile semiconductor memory element.

Further, by using an oxide for the deposition prevention film as in the present invention, it is possible to prevent more uniform intrusion of oxygen into the lower electrode.

Further, since the precipitation preventing film has a perovskite structure as in the present invention, the crystallinity of the ferroelectric film can be improved and good ferroelectric characteristics can be obtained.

Further, by using a conductive film as the deposition prevention film as in the present invention, the voltage applied to the capacitor electrode can be sufficiently applied to the ferroelectric film itself.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a ferroelectric capacitor according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a ferroelectric capacitor according to a second embodiment of the present invention.

FIG. 3 is a manufacturing process diagram of the nonvolatile semiconductor memory element of the present invention.

FIG. 4 is a configuration diagram of a nonvolatile semiconductor memory element of the present invention.

FIG. 5 is a diagram showing the number of foreign substances generated on the wafer surface in the first embodiment of the present invention.

FIG. 6 is a diagram showing the number of foreign substances generated on the wafer surface according to the second embodiment of the present invention.

FIG. 7 is a diagram showing a hysteresis characteristic of the ferroelectric capacitor according to the first embodiment of the present invention.

FIG. 8 is a configuration diagram of a conventional ferroelectric capacitor.

[Explanation of symbols]

1 SiO ₂ / Si substrate 2, 19 Ir film 3, 20 STNO film 4 and 21 SBT film 5 and 22 Pt film 6 IrO ₂ film 11 a silicon substrate 12 for element isolation insulating films 13 and 14 the impurity diffusion layer 15 of the switching transistor Gate part 16 First interlayer insulating film 17 Polysilicon plug 18 TaSiN film 23 TiO ₂ film 24 Second interlayer insulating film 25 Drive line 26 Third interlayer insulating film 27 Bit line

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (Reference) H01L 29/788 29/792

Claims (7)

[Claims] 1. A capacitor element having a lower electrode, a ferroelectric film, and an upper electrode comprising an Ir film or an IrO ₂ / Ir composite film, wherein the lower electrode is disposed between the ferroelectric film and the lower electrode. A ferroelectric capacitor element comprising a deposition preventing film for preventing oxidation and deposition. 2. The ferroelectric capacitor element according to claim 1, wherein said deposition prevention film is an oxide. 3. The ferroelectric capacitor element according to claim 2, wherein said precipitation preventing film has a perovskite structure. 4. The ferroelectric capacitor element according to claim 1, wherein said deposition prevention film has conductivity. 5. The method according to claim 1, wherein the deposition preventing film is formed of AB _{1 -x} Nb _x O ₃ ,
Formed by C _1-x D _x EO ₃ or _{FRuO 3, (0 ≦ x ≦} 1), of which, A is selected from the group comprising Pb, Sr, Ba, Ca and Mg, B is Ti, Zr, Hf , Mn, Fe, Co and Ni, C is selected from the group containing Y, La and Sc, D is selected from the group containing Sr, Ba, Ca and Mg, E is Ti, Hf , Mn, Fe, Co and Ni are selected from the group comprising:
The ferroelectric capacitor element according to any one of the above. 6. The ferroelectric capacitor element according to claim 1, wherein said ferroelectric film is a bismuth-based layered structure ferroelectric film. 7. A contact plug buried in a contact hole formed in a source region or a drain region of a select transistor formed in a semiconductor substrate and an interlayer insulating film formed so as to cover the semiconductor substrate and the select transistor. A nonvolatile semiconductor device comprising a ferroelectric capacitor element comprising a lower electrode, a ferroelectric film and an upper electrode formed via a contact plug and a diffusion barrier film, wherein the ferroelectric capacitor element is A nonvolatile semiconductor memory device, comprising the ferroelectric capacitor according to claim 6.