JPH10261723A - Semiconductor memory device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a resist pattern and a gate insulating film from coming into direct contact with each other in a manufacturing process by a method wherein a gate electrode layer is formed on a gate insulating film protective layer on a gate insulating film. SOLUTION: A first electrode 2c is formed on a semiconductor substrate 13 and element isolation regions 1a and 1b to serve as the gate electrode of a driver transistor. Gate insulating films 5a and 5b are formed in a prescribed region on a first conductive layer 4. A gate insulating film protective layer 7 is formed on the gate insulating films 5a and 5b. The gate insulating films 5a and 5b and the gate insulating film protective layer 7 are partly and selectively removed to form a poly contact 9b. At this point, a resist pattern is formed on the gate insulating film protective layer 7. By this setup, a resist pattern is prevented from coming into direct contact with the gate insulating films 5a and 5b.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly to a semiconductor memory device having a thin film transistor and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, as one of semiconductor storage devices, SR
AM (static random access memory) is known. An SRAM memory cell generally includes a flip-flop circuit and transistors for reading and writing data. An SRAM is a semiconductor memory device that retains data by substituting an operation state of a flip-flop circuit. Conventionally, an SRAM using a thin film transistor as a load transistor in a flip-flop circuit forming a memory cell has been known. FIG. 28 is an equivalent circuit diagram of an SRAM memory cell using a conventional thin film transistor as a load transistor. Referring to FIG. 28, the memory cell of the SRAM is 6
Transistors (D1, D2, T1, T2, A1, A
It consists of 2). Specifically, a flip-flop circuit is configured by two driver transistors (D1, D2) and two load transistors (T1, T2). In addition, as a transistor for reading and writing data, 2
Two access transistors (A1, A2) are provided. The drain region of the access transistor (A1) is connected to the bit line (BIT) 101, and the drain region of the access transistor (A2) is connected to the complementary bit line (/
BIT) 102. A word line (WL) 103 is connected to the gate electrodes of the access transistors (A1) and (A2).

FIGS. 29 to 30 are plan views showing a memory cell pattern of an SRAM using a conventional top gate thin film transistor as a load transistor.

More specifically, FIG. 29 shows a memory cell pattern formed on the main surface of a semiconductor substrate, and FIG. 30 shows a memory cell pattern located above the memory cell pattern shown in FIG.

As described above, the load transistors (T1, T2) formed of thin film transistors are replaced with the access transistors (A1, A2) and the driver transistors (D1, D2).
Above, the memory cells of the SRAM can have a hierarchical structure, thereby achieving integration.

Referring to FIG. 29, element isolation regions 1a to 1d are formed on a main surface of a semiconductor substrate, and an active region is formed so as to be surrounded by element isolation regions 1a to 1d. In the active region, a pair of driver transistors (D1, D2) and a pair of access transistors (A1, A2) are formed.

The access transistor (A1) has a drain region 10c, a source region 10b, and a gate electrode 2a.
And The driver transistor (D1) includes a drain region 10b, a source region 10a, and a gate electrode 2c.
And The driver transistor (D2) includes a drain region 10d, a source region 10a, and a gate electrode 2d.
And The access transistor (A2) includes a drain region 10e, a source region 10d, and a gate electrode 2b.
And Each of the gate electrodes 2a to 2d is formed to extend in substantially the same direction at a predetermined interval.

Referring to FIG. 30, a pair of driver transistors (D1, D2) formed on the main surface of the semiconductor substrate
Two load transistors (T1, T2) are formed on the pair of access transistors (A1, A2) with an interlayer insulating film (not shown) interposed. The load transistor (T1) has a drain region 4c and a source region 4c.
d and a gate electrode 6b. The load transistor (T2) has a drain region 4a, a source region 4b, and a gate electrode 6a. The gate electrode 6b of the load transistor (T1) is formed to extend in a direction substantially orthogonal to the direction in which the gate electrode 2a of the access transistor (A1) extends on the main surface of the semiconductor substrate. The gate electrode 6a of the load transistor (T2) is formed to extend in substantially the same direction as the gate electrode 6b of the load transistor (T1) at a predetermined interval. Further, the transistors (A1, A2,...) Formed on the main surface of the semiconductor substrate
D1 and D2) and polycontacts connecting the transistors (T1 and T2) formed on the interlayer insulating film on the main surface of the semiconductor substrate are shown in 9a to 9b and 11a to 11b.

The poly contact 9a is connected to the gate electrode 6a of the load transistor (T2) and the load transistor (T2).
The drain region 4c of 1) is connected to the gate electrode 2d of the driver transistor (D2) on the main surface of the semiconductor substrate. Similarly, poly contact 9b is connected to gate electrode 6b of load transistor (T1), drain region 4a of load transistor (T2), and gate electrode 2 of driver transistor (D1) on the main surface of the semiconductor substrate.
c.

The poly contact 11a connects the gate electrode 6a of the load transistor (T2), the source region 10b of the access transistor (A1) on the main surface of the semiconductor substrate, and the drain region 10b of the driver transistor (D1). Connected. Similarly, poly contact 1
1b is a gate electrode 6b of the load transistor (T1);
The access transistor (A) on the main surface of the semiconductor substrate
2) and a driver transistor (D
1) is connected to the drain region 10d.

FIG. 31 is a cross-sectional view of the conventional SRAM memory cell shown in FIGS. 29 to 30 taken along line 100-100.

Referring to FIG. 31, a sectional structure of a memory cell portion of a conventional SRAM will be described. Element isolation regions 1a and 1b are formed in predetermined regions on the semiconductor substrate 13. Semiconductor substrate 13 and element isolation region 1a,
A first electrode 2c constituting a gate electrode of the driver transistor (D1) is formed on 1b. On the first electrode 2c, interlayer insulating films 3a and 3b are formed.
Polycontacts 9a (not shown) and 9b are formed by selectively removing portions of interlayer insulating films 3a and 3b. On the interlayer insulating films 3a, 3b and the poly contacts 9a (not shown) and 9b, a first conductive layer 4 made of a silicon layer constituting a channel region and a source / drain region of the load transistors (T1, T2). Are formed. Gate insulating films 5a and 5b are formed in predetermined regions on the first conductive layer 4. Gate insulating film 5
Poly contacts 9a (not shown) and 9b are formed by selectively removing portions of a and 5b.
Load transistors (T1, T2) are provided on the gate insulating films 5a, 5b and the poly contacts 9a (not shown) and 9b.
2) Gate electrodes 6a and 6b of thin film transistor as
Are formed. In a region of the first conductive layer 4 where the load transistor (T2) is formed, a drain region 15 and a source region 16 are formed at a predetermined interval so as to sandwich the channel region 17. A load transistor (T2) is formed on the channel region 17 via the gate insulating film 5b.
Gate electrode 6a is formed.

FIGS. 32 to 40 show the conventional SR shown in FIG.
FIG. 4 is a cross-sectional view for explaining a manufacturing process of an AM memory cell. With reference to FIGS.
The manufacturing process of the AM memory cell will be described.

First, as shown in FIG.
Element isolation regions 1a and 1b are formed on the main surface of the semiconductor device 3. Next, doped polysilicon is subjected to chemical vapor deposition (CVD).
The first electrode 2c is formed by depositing 80 to 160 nm. The first electrode 2c is formed by depositing 40-80 nm of doped polysilicon and then depositing 40-80 nm of WSi.
It may be formed by depositing 80 nm. Phosphorus or arsenic is used as an impurity of the doped polysilicon. Next, an oxide film is formed in a thickness of 600 to 10 using a chemical vapor deposition method (CVD method).
The interlayer insulating film 3 is formed by depositing 00 nm. Next, the surface of the interlayer insulating film 3 is flattened by an etch-back process.

Next, as shown in FIG.
A resist pattern 14 is formed in a predetermined region above a and 3b. Then, poly-contacts 9a (not shown) and 9b are formed by dry-etching interlayer insulating films 3a and 3b using resist pattern 14 as a mask.
CF is used as an etching gas for this dry etching.
₄ , C ₂ F ₆ or a gas having similar properties is used.
Further, the etching time is selected according to the thickness of the interlayer insulating film so that no etching residue occurs. After the formation of the poly contacts 9a (not shown) and 9b, the resist pattern 14 is removed by ashing.

Next, as shown in FIG.
A silicon layer (not shown) is deposited on a, 3b and the poly contacts 9a (not shown), 9b. Then, using the resist pattern as a mask, the silicon layer (not shown)
Is dry-etched to form the first conductive layer 4. The silicon layer constituting the first conductive layer 4 is made of non-doped polysilicon by chemical vapor deposition (CVD).
It is formed by depositing about 50 nm. The first conductive layer 4 is formed by depositing non-doped amorphous silicon in a thickness of 20 to 50 nm by chemical vapor deposition (CVD), and then depositing 580 nm.
Heat treatment may be performed at a temperature of about 650 ° C. for several hours to crystallize amorphous silicon. In addition, a load transistor (T
In order to adjust the threshold voltage of the thin film transistor as (1, T2), impurity ions may be implanted into the first conductive layer 4. As impurity ions, phosphorus, arsenic, boron, or BF ₂ is used.

Next, as shown in FIG. 35, the first conductive layer 4
A gate oxide film 5 is formed by depositing a silicon oxide film thereon by a chemical vapor deposition method (CVD method) using a silane-based gas or a TEOS-based gas. This gate insulating film 5 is formed to have a thickness of about 20 to 40 nm.

Next, as shown in FIG. 36, using the resist pattern 14 as a mask, the gate insulating film 5 in the first poly contacts 9a (not shown) and 9b is removed by dry etching. At the same time, resist pattern 1
4 as a mask, gate insulating film 5 and interlayer insulating film 3
The second poly contacts 11a and 11b shown in FIG. 30 are formed by dry-etching a and b. CF ₄ , C ₂ F ₆ , or a gas having similar properties is used as an etching gas. Also, the second poly contact 11a,
At the bottom of 11b, the etching time is adjusted so that no etching residue occurs and the first conductive layer 4 in the first poly contacts 9a, 9b is not removed.

Next, as shown in FIG. 37, the resist pattern 14 is removed by performing ashing on the surfaces of the gate insulating films 5a and 5b. Thereafter, a light etching process is performed for several tens of seconds to remove foreign substances on the surfaces of the gate insulating films 5a and 5b.

Next, as shown in FIG. 38, the first conductive layer 4
A second electrode 6 is formed by depositing doped polysilicon or doped amorphous silicon on the gate insulating films 5a and 5b by chemical vapor deposition (CVD). The second electrode 6 is formed to have a thickness of 100 to 300 nm. In addition, phosphorus or arsenic is used as an impurity in the second electrode 6. In this step, the first conductive layer 4 and the second electrode 6 are connected.

Next, as shown in FIG. 39, the gate electrode 6a, 6b of the load transistor (T1, T2) is formed by dry-etching the second electrode 6 using the resist pattern 14 as a mask. The etching gas is C
F ₄ , C ₂ F ₆ , or a gas having similar properties is used.

Next, as shown in FIG. 40, boron or BF ₂ is added to the source region 16 of the load transistor (T2).
And the drain region 15 are ion-implanted. The implantation energy at the time of this ion implantation is such that the range of the ions matches the inside of the source region 16 and the drain region 15 and penetrates through the second electrodes 6a and 6b to form a channel below the second electrodes 6a and 6b. Adjustment is made so as not to affect the area 17. Boron or BF ₂ ion implantation amount is 1.0E14
adjusting the cm ^-2 to 1.0E16cm ^-2.

Next, the second electrodes 6a and 6b and the gate insulating film 5
After that, an interlayer insulating film is deposited, an aluminum contact is opened, and an aluminum wiring is formed. Thus, the conventional semiconductor memory device has been formed.

[0024]

In the conventional manufacturing process shown in FIG. 35, the deposited gate insulating film 5 finally becomes a gate insulating film of a thin film transistor as a load transistor (T1, T2). It becomes a film. The thickness of the gate insulating film 5 is becoming smaller year by year as the degree of integration of elements is increased. On the other hand, the gate electrodes 6a, 6
It is difficult to reduce the voltage applied to b due to restrictions on circuit design. Therefore, load transistors (T1, T
The electric field intensity applied to the gate insulating film 5 in 2) is extremely large, and its value is about 1 to 10 MV / cm. Therefore, even if the gate insulating film 5 has a defect which has not been a problem in the related art, a problem that the withstand voltage is reduced and the electrical characteristics of the load transistor are deteriorated is caused.

However, in the conventional process, a resist pattern 14 is applied directly on the gate insulating film 5 as shown in FIGS. And the resist pattern 1
4 is used as a mask to dry-etch the gate insulating film 5. Thereafter, the resist pattern 14 is removed by ashing, and a write etching process is performed to remove foreign substances on the surface of the gate insulating film 5.

In particular, when removing the resist pattern 14,
Due to the ashing process, defects (local irregularities) occur on the surface of the gate insulating film 5. Defects generated on the surface of the gate insulating film 5 cause non-uniform electric field distribution. For this reason, local concentration of an electric field occurs in the gate insulating film 5, and the withstand voltage of the gate insulating film 5 is reduced. As a result, problems such as deterioration of electrical characteristics of the thin film transistor as a load transistor have occurred.

Further, the thickness of the gate insulating film 5 is reduced by a write etching process performed for removing foreign substances on the surface of the gate insulating film 5. The decrease in the thickness of the gate insulating film 5 leads to a decrease in the withstand voltage of the gate insulating film 5. For this reason, similar to the above-described problem at the time of removing the resist pattern, there has been a problem that the electrical characteristics of the thin film transistor as the load transistor are deteriorated.

Referring to FIG. 28, P-type transistors are used as load transistors (T1, T2) and N-type transistors are used as driver transistors (D1, D2).
A PN junction is formed at the junction between T2) and the driver transistors (D1, D2).

More specifically, in the process shown in FIGS. 32 to 40, the polysilicon constituting the layer including the source region 16 and the drain region 15 of the load transistor (T2) is P-type, and the gate of the load transistor (T1) is formed. Since the polysilicon forming the electrode 6b is N-type, a PN junction is formed at the junction of both layers at the poly contact 9b and the like.
Then, a voltage drop occurs due to the PN junction, and as a result, the potential of the storage node set to a high potential is reduced. If this tendency is promoted, there has been a problem that the data is inverted, which adversely affects the reliability of the memory cell.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and one object of the present invention is to provide a semiconductor memory device having a defect on a surface of a gate insulating film of a thin film transistor during a manufacturing process thereof. The purpose is to prevent the occurrence of such a phenomenon, thereby preventing a decrease in the withstand voltage of the gate insulating film.

Another object of the present invention is to prevent a decrease in the withstand voltage of the gate insulating film 5 in the semiconductor memory device by preventing the thickness of the gate insulating film of the thin film transistor from being reduced during the manufacturing process. That is.

Still another object of the present invention is to reduce a voltage drop at a PN junction formed in a circuit in a semiconductor memory device.

[0033]

According to a first aspect of the present invention, there is provided a semiconductor memory device having a thin film transistor, comprising a semiconductor layer, a gate insulating film, a gate insulating film protection layer, and a gate electrode layer. ing. The semiconductor layer is
It is formed on a substrate. The gate insulating film is formed on the semiconductor layer. The gate insulating film protection layer is formed on the gate insulating film. The gate electrode layer is formed on the gate insulating film protection layer. By providing the gate insulating film protective layer in this manner, direct contact between the resist pattern and the gate insulating film during the manufacturing process is prevented. Thus, in an ashing process for removing a resist pattern in a semiconductor manufacturing process, generation of a defect (local unevenness) due to the ashing process on the surface of the gate insulating film can be prevented. Further, also in the light etching process at the time of removing the resist pattern, since the direct light etching process is prevented on the surface of the gate insulating film, a decrease in the thickness of the gate insulating film can be prevented. Therefore, a decrease in the withstand voltage due to a surface defect or a decrease in the thickness of the gate insulating film can be prevented, and deterioration of the electrical characteristics of the load transistor can be prevented.

According to a second aspect of the present invention, in the semiconductor memory device according to the first aspect, the gate insulating film protective layer is formed of the same material as the gate electrode layer. By forming the gate insulating film protective layer with the same material as the gate electrode layer in this manner, even if a defect (local unevenness) due to the ashing process occurs on the surface of the gate insulating film protective layer, the gate electrode layer is formed. In the formation process, a layer made of the same material as the gate insulating film protective layer is formed on the defect. As a result, the defect can be regarded as a grain boundary in a substance forming the gate electrode layer. Therefore, it is possible to prevent non-uniform electric field distribution at the boundary between the gate electrode layer and the gate insulating film protection layer due to a defect generated during the ashing process on the surface of the gate insulating film protection layer.

According to a third aspect of the present invention, in the semiconductor memory device according to the first aspect, the gate insulating film protective layer is formed of a thermal oxide film. By forming the gate insulating film protective layer with a thermal oxide film in this manner, an ashing process for removing a resist pattern and a light etch process for removing foreign substances can be performed on the thermal oxide film having high etching resistance. Become. Therefore, the occurrence of surface defects on the surface of the gate insulating film protective layer is suppressed by the ashing process, and the decrease in the thickness of the gate insulating film protective layer is reduced by the light etching process.

According to a fourth aspect of the present invention, a semiconductor layer is first formed on a substrate. A gate insulating film is formed over the semiconductor layer. A gate insulating film protection layer is formed on the gate insulating film. A resist pattern is formed on the gate insulating film protection layer. Using the resist pattern as a mask, the gate insulating film and the gate insulating film protective layer in a predetermined region are removed by dry etching. A gate electrode layer is formed on the gate insulating film protection layer. As described above, by providing the step of providing the gate insulating film protective layer, direct contact between the resist pattern and the gate insulating film in the subsequent steps is prevented. Thus, in an ashing process for removing a resist pattern in a semiconductor manufacturing process, generation of a defect (local unevenness) due to the ashing process on the surface of the gate insulating film can be prevented. Further, also in the light etching process at the time of removing the resist pattern, since the direct light etching process is prevented on the surface of the gate insulating film, a decrease in the thickness of the gate insulating film can be prevented. Therefore, a decrease in the withstand voltage due to a surface defect or a decrease in the thickness of the gate insulating film can be prevented, and as a result, a deterioration in the electrical characteristics of the load transistor can be prevented.

According to a fifth aspect of the present invention, there is provided a method of manufacturing a semiconductor memory device according to the fourth aspect, further comprising the step of forming the gate insulating film protective layer by a thermal oxide film. Since the step of forming the gate insulating film protective layer by the thermal oxide film as described above is performed, an ashing process for removing a resist pattern and a light etch process for removing foreign substances are performed on the thermal oxide film having high etching resistance. Will be.
Therefore, the occurrence of surface defects on the surface of the gate insulating film protective layer due to the ashing process and the decrease in the thickness of the gate insulating film protective layer due to the light etching process are reduced.

According to a sixth aspect of the present invention, in a method of manufacturing a semiconductor memory device, a semiconductor layer containing a first conductivity type impurity is formed on a substrate. A gate insulating film is formed on the semiconductor layer.
A gate electrode layer containing an impurity of the second conductivity type is formed on the gate insulating film so as to be in contact with the semiconductor layer. A first conductivity type impurity is introduced into the gate electrode layer. In this manner, by introducing the first conductivity type impurity into the gate electrode layer containing the second conductivity type impurity, part of the second conductivity type impurity of the gate electrode layer is changed by the first conductivity type impurity. Is counteracted. Accordingly, the impurity concentration of the second conductivity type of the gate electrode layer is reduced, and as a result, a voltage drop at a PN junction formed at a contact portion between the semiconductor layer and the gate electrode layer can be reduced.

[0039]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 is a sectional view showing a structure of a memory cell of an SRAM according to a first embodiment of the present invention, which corresponds to the sectional view of the conventional memory cell shown in FIG. I do. Referring to FIG. 1, element isolation regions 1a and 1b are formed in a predetermined region on semiconductor substrate 13.
On the semiconductor substrate 13 and the element isolation regions 1a and 1b, a first electrode 2c constituting a gate electrode of the driver transistor (D1) is formed. On the first electrode 2c, interlayer insulating films 3a and 3b are formed. Interlayer insulating film 3
Poly contacts 9a (not shown) and 9b are formed by selectively removing portions of a and 3b. On the interlayer insulating films 3a and 3b and the poly contacts 9a (not shown) and 9b, load transistors (T1, T
The first conductive layer 4 made of a silicon layer constituting the channel region and the source / drain region of 2) is formed. Gate insulating films 5a, 5b are provided in predetermined regions on first conductive layer 4.
Are formed. A gate insulating film protection layer 7 is formed on the gate insulating films 5a and 5b. Gate insulating film 5
a, 5b and a part of the gate insulating film protection layer 7 are selectively removed to form poly contacts 9a (not shown), 9a.
b is formed. On the gate insulating film protection layer 7 and the poly contacts 9a (not shown) and 9b, thin film transistor gate electrodes 6a and 6b are formed as load transistors (T1 and T2). In the region of the first conductive layer 4 where the load transistor (T2) is to be formed, the drain region 1 is separated by a predetermined distance so as to sandwich the channel region 17.
5 and a source region 16 are formed. On the channel region 17, the gate oxide film 5b and the gate oxide protection layer 7
And the gate electrode 6a of the load transistor (T2)
Are formed.

In the memory cell of the first embodiment, FIG.
As shown in FIG. 7, a gate insulating film protection layer 7 is formed on the gate insulating films 5a and 5b. Therefore, when forming the first poly contacts 9a (not shown) and 9b in a manufacturing process described later, a resist pattern 14 is formed on the gate insulating film protection layer 7. This prevents the resist pattern 14 from being formed in direct contact with the gate insulating films 5a and 5b. As a result, it is possible to prevent defects from being generated on the surfaces of the gate insulating films 5a and 5b during the ashing process for removing the resist pattern 14 and the light etching process for removing foreign substances, and to prevent the gate insulating film 5a from being defective. It is possible to prevent the thickness of the films 5a and 5b from decreasing. Therefore, it is possible to prevent a decrease in the withstand voltage due to a surface defect or a decrease in the film thickness of the gate insulating films 5a and 5b, and it is possible to prevent the electrical characteristics of the thin film transistors (T1, T2) as load transistors from deteriorating.

FIGS. 2 to 12 show the first embodiment shown in FIG.
FIG. 9 is a cross-sectional view for illustrating the memory cell manufacturing process according to the first embodiment. Hereinafter, a manufacturing process of the memory cell according to the first embodiment will be described with reference to FIGS.

First, as shown in FIG.
Element isolation regions 1a and 1b are formed on the main surface of the semiconductor device 3. Next, doped polysilicon is subjected to chemical vapor deposition (CVD).
The first electrode 2c is formed by depositing 80 to 160 nm. The first electrode 2c is formed by depositing 40-80 nm of doped polysilicon and then depositing 40-80 nm of WSi.
It may be formed by depositing 80 nm. Phosphorus or arsenic is used as an impurity of the doped polysilicon. Next, an oxide film is formed in a thickness of 600 to 1 using a chemical vapor deposition method (CVD method).
The interlayer insulating film 3 is formed by depositing 000 nm. Next, the surface of the interlayer insulating film 3 is flattened by an etch-back process.

Next, as shown in FIG.
A resist pattern 14 is formed in a predetermined region above a and 3b. Then, poly-contacts 9a (not shown) and 9b are formed by dry-etching interlayer insulating films 3a and 3b using resist pattern 14 as a mask. As an etching gas at the time of this dry etching, CF ₄ , C ₂ F ₆ , or a gas having similar properties is used. Further, the etching time is selected according to the thickness of the interlayer insulating film so that no etching residue occurs. After forming the poly contacts 9a (not shown) and 9b,
The resist pattern 14 is removed by ashing.

Next, as shown in FIG.
A silicon layer (not shown) is deposited on a, 3b and the poly contacts 9a (not shown), 9b. Then, the first conductive layer 4 is formed by dry-etching the silicon layer 4 using the resist pattern as a mask. First
The silicon layer constituting the conductive layer 4 is made of non-doped polysilicon by chemical vapor deposition (CVD) with a thickness of 20 to 50 nm.
It is formed by depositing. This first conductive layer 4
Uses undoped amorphous silicon by chemical vapor deposition (C
VD method) to deposit 20 to 50 nm and then 580 to 65
A heat treatment may be performed at 0 ° C. for several hours to crystallize amorphous silicon. In addition, load transistors (T1, T
In order to adjust the threshold voltage of the thin film transistor as 2), impurity ions may be implanted into the first conductive layer 4. The impurity ions include phosphorus, arsenic, boron, or B
The F ₂ is used.

Next, as shown in FIG. 5, a silicon oxide film is deposited on the first conductive layer 4 by a chemical vapor deposition (CVD) method using a silane-based gas or a TEOS-based gas. A gate insulating film 5 is formed. This gate insulating film 5 is formed to have a thickness of about 20 to 40 nm.

Next, as shown in FIG.
Of doped polysilicon or doped amorphous silicon by chemical vapor deposition (CVD)
The gate insulating film protection layer 7 is formed by depositing nm. Phosphorus or arsenic is used as an impurity of doped polysilicon or doped amorphous silicon.

Next, as shown in FIG. 7, after forming a resist pattern 14 on the gate insulating film protection layer 7, the first poly contact 9 is formed using the resist pattern 14 as a mask.
The gate insulating film protection layer 7 and the gate insulating film 5 in a (not shown) and 9b are removed by dry etching. At the same time, using the resist pattern 14 as a mask, the gate insulating film protective layer 7, the gate insulating film 5, and the interlayer insulating film 3
a and 3b are dry-etched to form second poly contacts 11a and 11b shown in FIG. CF ₄ , C ₂ F ₆ , or a gas having similar properties is used as an etching gas. Also, the second poly contact 11
The etching time is adjusted so that no etching residue occurs at the bottoms of a and 11b and the first conductive layer 4 in the first poly contacts 9a (not shown) and 9b is not removed.

Next, as shown in FIG. 8, the resist pattern 14 is removed by performing ashing on the surface of the gate insulating film protection layer 7. Thereafter, in order to remove foreign substances on the surface of the gate insulating film protection layer 7, a write etching process is performed for several tens of seconds. Here, in the manufacturing process of the first embodiment, the gate insulating film protection layer 7 is formed on the gate insulating film 5.
To form Therefore, in the step of forming first poly contacts 9a (not shown) and 9b shown in FIG. 7, direct contact between resist pattern 14 and gate insulating film 5 is prevented. Thereby, in the ashing process for removing the resist pattern 14 shown in FIG. 8, it is possible to prevent the occurrence of defects (local irregularities) due to the ashing process on the surface of the gate insulating film 5. Also, in the write etching process for removing foreign matter after the ashing process, since the direct write etching process is prevented on the surface of the gate insulating film 5, the thickness of the gate insulating film 5 can be prevented from decreasing. it can.

Next, as shown in FIG. 9, doped polysilicon or doped amorphous silicon is formed on the first conductive layer 4 and the gate insulating film protection layer 7 by chemical vapor deposition (CVD). By depositing, the second electrode 6
To form The second electrode 6 is formed to have a thickness of 100 to 300 nm. N-type phosphorus or arsenic is used as an impurity in the second electrode 6. In this step, the first conductive layer 4 and the second electrode 6 are connected.

Next, as shown in FIG.
P-type boron or BF ₂ is ion-implanted using an oblique rotation implantation method of about 5 °. The implantation energy at the time of this ion implantation is as follows: the second electrode 6, the gate insulating film protection layer 7,
The adjustment is performed so that the implanted ions do not affect the first conductive layer 4 through the gate insulating films 5a and 5b. The amount of implanted boron or BF ₂ ions is 1.0E15 cm ^−2.
Adjust to ~ 1.0E17cm ^-2 . Here, the second electrode 6
Of the thin film transistor (T2) serving as a load transistor is finally formed by the drain region 15 (not shown) and the source region 16 (not shown) of the thin film transistor (T2) as a load transistor. ), It becomes P-type. Therefore, poly contacts 9a (not shown), 9b
In the contact portion between the second electrode 6 and the first conductive layer 4 as described above, PN
A bond is formed. However, in the first embodiment, as shown in FIG. 10, second electrode 6 doped with an N-type impurity is formed.
Then, P-type boron or BF ₂ is ion-implanted using an oblique rotation implantation method of about 45 °. Since boron or BF ₂ injected into the second electrode 6 is a P-type impurity, a part of the N-type impurity of the second electrode 6 is canceled by the introduced boron or BF ₂ . Thereby, the N of the second electrode 6
As a result, the voltage drop at the PN junction can be reduced.

Next, as shown in FIG.
The electrode 14 is used as a mask to protect the second electrode 6 and the gate insulating film.
The load transformer is formed by dry etching the protective layer 7.
Forming gate electrodes 6a, 6b of the transistors (T1, T2);
You. CF for etching gas _Four, C_TwoF₆Or similar
A gas having the following properties is used.

Next, as shown in FIG.
BF_TwoTo the source region 16 of the load transistor (T2).
And the drain region 15 are ion-implanted. This ion
The implantation energy at the time of implantation depends on the source region 16 and the drain.
The range of the ions is in the interior of the inside region 15 and the second
Penetrating through the electrodes 6a, 6b, and under the second electrodes 6a, 6b
Adjusted so as not to affect the channel region 17 in the section
I do. Boron or BF _TwoThe ion implantation amount is 1.0E
14cm^-2~ 1.0E16cm^-2Adjust to

Next, an interlayer insulating film is deposited on the second electrodes 6a and 6b and the gate insulating film 5, and after opening an aluminum contact, an aluminum wiring is formed.

(Embodiment 2) FIG. 13 is a cross-sectional view for illustrating the structure of a memory cell according to Embodiment 2 of the present invention. In the memory cell according to the second embodiment,
The thickness Tp1 of the gate insulating film protection layer 7 is set to 10 nm <Tp1.
<30 nm. Usually in dry etching,
Since the process conditions for the silicon layer forming the gate insulating film protection layer 7 and the silicon oxide films forming the gate insulating films 5a and 5b are different from each other, FIG.
When a polycontact is formed as shown in FIG. 1, a two-stage etching process is required. However, as described above, the thickness of the gate insulating film protection layer 7 is reduced (10 nm <Tp1 <30n).
m) If formed, the silicon layer forming the gate insulating film protection layer 7 is also etched using only the etching process conditions suitable for the silicon oxide film. Thereby, in one etching process, the gate insulating films 5a, 5b,
The gate insulating film protection layer 7 can be etched,
As a result, in addition to the effect of the first embodiment, the etching step at the time of forming the poly contact shown in FIG. 7 can be further simplified.

When Tp1 <10 nm, it is difficult to form the gate insulating film protection layer 7 uniformly.
When Tp1> 30 nm, the gate insulating films 5a, 5b are used in the dry etching for forming the poly contact.
It becomes difficult to etch the gate insulating film protective layer 7 only under the etching process conditions suitable for the above.

(Embodiment 3) FIG. 14 is a cross-sectional view for illustrating a structure of a memory cell according to Embodiment 3 of the present invention. In the memory cell of the third embodiment, the thickness Tp2 of the second electrodes 6a and 6b is set to 200 nm or less. FIG.
In the step shown in FIG. 1, the second electrode 6a, 6b and the gate insulating film protection layer 7 are formed using the resist pattern 14 as a mask.
When dry etching is performed, overetching is performed in consideration of a process margin. Since the amount of overetching at this time is proportional to the total film thickness of the second electrodes 6a and 6b and the gate insulating film protection layer 7, the film thickness T of the second electrodes 6a and 6b is
By limiting p2 to 200 nm or less, the amount of overetch is limited. As a result, in addition to the effect of the first embodiment, in the dry etching process as shown in FIG. 11, the thickness of the gate insulating films 5a and 5b is reduced due to the overetch, and the gate insulating films 5a and 5b It is possible to prevent the problem that the first conductive layer 4 is etched by disappearing by the etching.

When Tp2> 200 nm, FIG.
As shown in FIG. 5, when the second electrodes 6a and 6b and the gate insulating film protective layer 7 are dry-etched using the resist pattern 14 as a mask, up to the gate insulating films 5a and 5b disappear by etching due to overetching, and
There is a possibility that even the conductive layer 4 is etched.

(Embodiment 4) FIG. 15 is a sectional view showing a structure of a memory cell according to Embodiment 4 of the present invention. Referring to FIG. 15, the memory cell of the fourth embodiment differs from the memory cell of the first embodiment in that gate insulating film protection layer 8 is formed of a thermal oxide film. In the fourth embodiment, the gate insulating film protection layer 8 is formed of a thermal oxide film, so that ashing process for removing a resist pattern and foreign matter removal are performed on the thermal oxide film having high etching resistance in the manufacturing process. Is performed for this purpose. Therefore, the occurrence of defects on the surface of the gate insulating film protection layer 8 due to the ashing process and the decrease in the thickness of the gate insulating film protection layer 8 due to the light etching process are reduced.

FIGS. 16 to 27 are cross-sectional views for illustrating a manufacturing process of the memory cell according to the fourth embodiment shown in FIG. The manufacturing process of the memory cell according to the fourth embodiment will be described below with reference to FIGS.

First, as shown in FIG. 16, element isolation regions 1a and 1b are formed on the main surface of silicon substrate 13.
Next, doped polysilicon is deposited by chemical vapor deposition (CVD).
1) by depositing 80 to 160 nm by
The electrode 2c is formed. The first electrode 2c is formed by depositing 40 to 80 nm of doped polysilicon and further adding WSi to 4
It may be formed by depositing 0 to 80 nm. Phosphorus or arsenic is used as an impurity of the doped polysilicon. Next, an oxide film is formed using a chemical vapor deposition (CVD) method.
The interlayer insulating film 3 is formed by depositing 0 to 1000 nm. Next, the surface of the interlayer insulating film 3 is flattened by an etch-back process.

Next, as shown in FIG.
A resist pattern 14 is formed in a predetermined region above a and 3b. Then, poly-contacts 9a (not shown) and 9b are formed by dry-etching interlayer insulating films 3a and 3b using resist pattern 14 as a mask.
CF is used as an etching gas for this dry etching.
₄ , C ₂ F ₆ or a gas having similar properties is used.
Further, the etching time is selected according to the thickness of the interlayer insulating film so that no etching residue occurs. After the formation of the poly contacts 9a (not shown) and 9b, the resist pattern 14 is removed by ashing. next,
As shown in FIG. 18, a silicon layer (not shown) is deposited on interlayer insulating films 3a and 3b and poly contacts 9a (not shown) and 9b. Then, the first conductive layer 4 is formed by dry etching the silicon layer (not shown) using the resist pattern as a mask. First conductive layer 4
Is formed by depositing 20 to 50 nm of non-doped polysilicon by chemical vapor deposition (CVD). The first conductive layer 4 is formed by depositing non-doped amorphous silicon with a thickness of 20 to 50 nm by a chemical vapor deposition method (CVD method), and then performing a heat treatment at 580 to 650 ° C. for several hours to crystallize the amorphous silicon. It may be formed. Further, in order to adjust the threshold voltage of the thin film transistor as the load transistor (T1, T2),
Impurity ions may be implanted into the first conductive layer 4. As impurity ions, phosphorus, arsenic, boron, or BF ₂ is used.

Next, as shown in FIG. 19, the first conductive layer 4
A gate oxide film 5 is formed by depositing a silicon oxide film thereon by a chemical vapor deposition method (CVD method) using a silane-based gas or a TEOS-based gas. This gate insulating film 5 is formed to have a thickness of about 20 to 40 nm.

Next, as shown in FIG. 20, doped polysilicon or doped amorphous silicon is deposited on the gate insulating film 5 by a chemical vapor deposition method (CVD method) to thereby form the gate insulating film protective layer 7. To form The gate insulating film protection layer 7 has a thickness of about 10 to 30 nm and a total thickness of the gate insulating film 5 and the gate insulating film protection layer 7 of about 30 to 50 nm. Form.

Next, as shown in FIG. 21, the gate insulating film protection layer 7 is thermally oxidized to form a silicon oxide film 8. This thermal oxidation is performed at a temperature of 580 to 650 ° C. for several hours.

Next, as shown in FIG. 22, using the resist pattern 14 as a mask, the gate insulating film protective layer 8 and the gate insulating film 5 in the first poly contacts 9a (not shown) and 9b are dry-etched. To remove. At the same time, the second poly contacts 11a and 11b shown in FIG. 30 are formed by dry-etching the gate insulating film protective layer 8, the gate insulating film 5, and the interlayer insulating films 3a and 3b using the resist pattern 14 as a mask. CF ₄ , C ₂ F ₆ , or a gas having similar properties is used as an etching gas. In addition, at the bottom of the second poly contacts 11a, 11b, no etching residue occurs, and the first polysilicon contacts 9a (not shown),
The etching time is adjusted so that the conductive layer 4 is not removed.

Here, the poly contact 9a shown in FIG.
(Not shown), since both the gate insulating film 5 and the gate insulating film protection layer 8 are formed of a silicon oxide film at the time of forming 9b, etching is performed using only etching process conditions suitable for the silicon oxide film. be able to. As a result, in addition to the effect of the first embodiment, the etching step for forming the polycontact shown in FIG. 22 can be further simplified.

Next, as shown in FIG. 23, the resist pattern 14 is removed from the surface of the gate insulating film protection layer 8 by performing ashing. Thereafter, a write etch process is performed for several tens of seconds to remove foreign substances on the surface of the gate insulating film protection layer 8.

Next, as shown in FIG. 24, the first conductive layer 4
A second electrode 6 is formed by depositing doped polysilicon or doped amorphous silicon on the gate insulating film protection layer 8 by chemical vapor deposition (CVD). The second electrode 6 is formed to have a thickness of 100 to 300 nm. In addition, phosphorus or arsenic is used as an impurity in the second electrode 6. In this step, the first conductive layer 4 and the second electrode 6 are connected.

Next, as shown in FIG. 25, boron or BF
₂ is ion-implanted. The implantation energy at the time of this ion implantation is adjusted so that the implanted ions do not affect the first conductive layer 4 through the second electrode 6, the gate insulating film protective layer 8, and the gate insulating films 5a and 5b. I do. Further, the implantation amount of boron or BF ₂ ions is 1.0E15 cm ⁻² to 1.0.
Adjust to 0E17cm- ² .

Next, as shown in FIG. 26, the gate electrodes 6a and 6b of the load transistors (T1, T2) are formed by dry-etching the second electrode 6 using the resist pattern 14 as a mask. The etching gas is C
F ₄ , C ₂ F ₆ , or a gas having similar properties is used.

Next, as shown in FIG. 27, boron or BF ₂ is added to the source region 16 of the load transistor (T2).
And the drain region 15 are ion-implanted. The implantation energy at the time of this ion implantation is such that the range of the ions matches the inside of the source region 16 and the drain region 15 and penetrates through the second electrodes 6a and 6b to form a channel below the second electrodes 6a and 6b. Adjustment is made so as not to affect the area 17. Boron or BF ₂ ion implantation amount is 1.0E14
adjusted to cm ^-2 ~1.0E16cm ^-2.

Next, an interlayer insulating film is deposited on the second electrodes 6a and 6b and the gate insulating film 5, an aluminum contact is opened, and an aluminum wiring is formed.

[0074]

According to the semiconductor memory device of the first aspect, by providing the gate insulating film protective layer on the gate insulating film, direct contact between the resist pattern and the gate insulating film during the manufacturing process is prevented. Is done. This allows
In the semiconductor manufacturing process, generation of defects (local irregularities) on the gate insulating film surface due to ashing can be prevented. Further, also in the light etching process at the time of removing the resist pattern, since the direct light etching process is prevented on the surface of the gate insulating film, a decrease in the thickness of the gate insulating film can be prevented. Therefore, a decrease in the withstand voltage due to a surface defect or a decrease in the thickness of the gate insulating film can be prevented, and deterioration of the electrical characteristics of the load transistor can be prevented.

Further, if the gate insulating film protective layer is formed of the same material as the gate electrode layer as described in claim 2, the surface of the gate insulating film protective layer has defects (local irregularities) caused by ashing. ) Occurs, a layer of the same material as that of the gate insulating film protective layer is formed on the defect in the process of forming the gate electrode layer, and as a result, the defect is formed in the material forming the gate electrode layer. It can be regarded as a grain boundary.
Therefore, it is possible to prevent non-uniform electric field distribution at the boundary between the gate electrode layer and the gate insulating film protection layer due to a defect generated during the ashing process on the surface of the gate oxide film protection layer.

Further, when the gate insulating film protective layer is formed of a thermal oxide film, an ashing process for removing a resist pattern or a foreign substance may be performed on the thermal oxide film having high etching resistance. Since the light etching process for removal is performed, the occurrence of surface defects on the surface of the gate insulating film protective layer due to the ashing process is suppressed, and the thickness of the gate insulating film protective layer is reduced due to the light etching process. Is reduced.

According to the method of manufacturing a semiconductor memory device of the fourth aspect, the step of providing the gate insulating film protective layer on the gate insulating film allows direct contact between the resist pattern and the gate insulating film in the subsequent steps. Is prevented. Thus, in an ashing process for removing a resist pattern in a semiconductor manufacturing process, generation of a defect (local unevenness) due to the ashing process on the surface of the gate insulating film can be prevented. Further, also in the light etching process at the time of removing the resist pattern, since the direct light etching process is prevented on the surface of the gate insulating film, a decrease in the thickness of the gate insulating film can be prevented. Therefore, a decrease in the withstand voltage due to a surface defect or a decrease in the thickness of the gate insulating film can be prevented, and as a result, the deterioration of the electrical characteristics of the load transistor can be prevented.

Further, according to the fifth aspect of the present invention, the method further includes the step of forming the gate insulating film protective layer by a thermal oxide film.
Since an ashing process for removing the resist pattern and a light etching process for removing foreign matter are performed,
The occurrence of surface defects on the surface of the gate insulating film protective layer due to the ashing process and the decrease in the thickness of the gate insulating film protective layer due to the light etching process are reduced.

According to the method of manufacturing a semiconductor memory device of the present invention, the gate electrode layer containing the second conductivity type impurity formed on the semiconductor layer containing the first conductivity type impurity includes:
By introducing the first conductivity type impurity, part of the second conductivity type impurity in the gate electrode layer is canceled by the first conductivity type impurity. Thereby, the second of the gate electrode layer
The conductivity type impurity concentration is reduced, and as a result, a voltage effect at a PN junction formed at a contact portion between the semiconductor layer and the gate electrode layer can be reduced.

[Brief description of the drawings]

FIG. 1 is a sectional structural view showing a memory cell of an SRAM according to a first embodiment of the present invention;

FIG. 2 is a cross-sectional structure diagram for describing a first step of a manufacturing process of the SRAM memory cell according to the first embodiment shown in FIG. 1;

FIG. 3 is a cross-sectional structure diagram for describing a second step of the manufacturing process of the SRAM memory cell according to the first embodiment shown in FIG. 1;

FIG. 4 is a sectional structural view for illustrating a third step of the manufacturing process of the SRAM memory cell according to the first embodiment shown in FIG. 1;

FIG. 5 is a sectional structural view for illustrating a fourth step of the manufacturing process of the SRAM memory cell according to the first embodiment shown in FIG. 1;

FIG. 6 is a sectional structural view for illustrating a fifth step of the manufacturing process of the SRAM memory cell according to the first embodiment shown in FIG. 1;

FIG. 7 is a sectional structural view for illustrating a sixth step of the manufacturing process of the SRAM memory cell according to the first embodiment shown in FIG. 1;

FIG. 8 is a sectional structural view for illustrating a seventh step of the manufacturing process of the SRAM memory cell according to the first embodiment shown in FIG. 1;

FIG. 9 is a sectional structural view for illustrating an eighth step of the manufacturing process of the SRAM memory cell according to the first embodiment shown in FIG. 1;

FIG. 10 shows the SRAM according to the first embodiment shown in FIG.
FIG. 32 is a cross-sectional structure diagram for describing a ninth step of the memory cell manufacturing process.

FIG. 11 is an SRAM according to the first embodiment shown in FIG.
FIG. 35 is a cross-sectional structure diagram for describing a tenth step of the memory cell manufacturing process.

FIG. 12 is an SRAM according to the first embodiment shown in FIG.
FIG. 32 is a cross-sectional structure diagram for describing an eleventh step of the memory cell manufacturing process.

FIG. 13 is a sectional structural view showing a memory cell of an SRAM according to a second embodiment of the present invention;

FIG. 14 is a sectional structural view showing a memory cell of an SRAM according to a third embodiment of the present invention.

FIG. 15 is a sectional view showing a memory cell of an SRAM according to a fourth embodiment of the present invention;

FIG. 16 shows an SRA according to the fourth embodiment shown in FIG.
FIG. 32 is a cross-sectional structure diagram for describing a first step in the manufacturing process of the M memory cell.

17 is an SRA according to the fourth embodiment shown in FIG.
FIG. 29 is a cross-sectional structure diagram for describing a second step in the manufacturing process of the M memory cell.

FIG. 18 is an SRA according to the fourth embodiment shown in FIG.
FIG. 29 is a cross-sectional structure diagram for describing a third step in the manufacturing process of the M memory cell.

FIG. 19 is an SRA according to the fourth embodiment shown in FIG.
FIG. 21 is a sectional structural view for describing a fourth step of the manufacturing process of the M memory cell.

20 is an SRA according to the fourth embodiment shown in FIG.
FIG. 29 is a cross-sectional structure diagram for describing a fifth step in the manufacturing process of the M memory cell.

FIG. 21 is an SRA according to the fourth embodiment shown in FIG.
FIG. 32 is a cross-sectional structure diagram for describing a sixth step in the manufacturing process of the M memory cell.

FIG. 22 is an SRA according to the fourth embodiment shown in FIG.
FIG. 32 is a cross-sectional structure diagram for describing a seventh step in the manufacturing process of the M memory cell.

FIG. 23 is an SRA according to the fourth embodiment shown in FIG.
FIG. 28 is a cross-sectional structure diagram for describing an eighth step of the manufacturing process of the M memory cell.

FIG. 24 is an SRA according to the fourth embodiment shown in FIG.
FIG. 32 is a cross-sectional structure diagram for describing a ninth step of the manufacturing process of the M memory cell.

FIG. 25 is an SRA according to the fourth embodiment shown in FIG.
FIG. 32 is a cross-sectional structure diagram for describing a tenth step of the manufacturing process of the M memory cell.

FIG. 26 is an SRA according to the fourth embodiment shown in FIG.
FIG. 32 is a cross-sectional structure diagram for describing an eleventh step of the manufacturing process of the M memory cell.

FIG. 27 is an SRA according to the fourth embodiment shown in FIG.
FIG. 35 is a cross-sectional structure diagram for describing a twelfth step of the manufacturing process of the M memory cell.

FIG. 28 is an equivalent circuit diagram of a conventional SRAM memory cell.

FIG. 29 is a plan view showing a memory cell pattern formed on a main surface of a substrate of a conventional SRAM memory cell.

30 is a plan view showing a memory cell pattern formed in an upper layer of the memory cell pattern shown in FIG. 29.

FIG. 31 is a cross-sectional view of the memory cell of the conventional SRAM shown in FIG. 29, taken along line 100-100.

FIG. 32 is a cross-sectional structure diagram for describing a first step of the manufacturing process of the memory cell of the conventional SRAM shown in FIG. 31;

FIG. 33 is a sectional structural view for illustrating a second step of the manufacturing process of the memory cell of the conventional SRAM shown in FIG. 31;

FIG. 34 is a sectional structural view for illustrating a third step of the manufacturing process of the memory cell of the conventional SRAM shown in FIG. 31;

FIG. 35 is a sectional structural view for illustrating a fourth step of the manufacturing process of the conventional SRAM memory cell shown in FIG. 31;

FIG. 36 is a sectional structural view for illustrating a fifth step of the manufacturing process of the conventional SRAM memory cell shown in FIG. 31;

FIG. 37 is a sectional structural view for illustrating a sixth step of the manufacturing process of the conventional SRAM memory cell shown in FIG. 31;

FIG. 38 is a sectional structural view for illustrating a seventh step of the manufacturing process of the memory cell of the conventional SRAM shown in FIG. 31;

FIG. 39 is a sectional structural view for illustrating an eighth step of the manufacturing process of the conventional SRAM memory cell shown in FIG. 31;

40 is a sectional structural view for illustrating a ninth step of the process for manufacturing the memory cell of the conventional SRAM shown in FIG. 31;

[Explanation of symbols]

1 device isolation region, 2nd electrode, 3 interlayer insulating film, 4
First conductive layer, 5 gate insulating film, 6 second electrode, 7
A gate insulating film protective layer made of a silicon layer, 8 a gate insulating film protective layer made of a thermal oxide film, 9 first poly contacts,
10 N + diffusion layer, 11 second poly contact, 13
Substrate, 14 resist pattern, 15 drain region, 1
6 Source region, 17 channel region.

Claims (6)

[Claims] 1. A semiconductor memory device having a thin film transistor, comprising: a semiconductor layer formed on a substrate; a gate insulating film formed on the semiconductor layer; and a gate insulating film formed on the gate insulating film A semiconductor memory device comprising: a protective layer; and a gate electrode layer formed on the gate insulating film protective layer. 2. The semiconductor memory device according to claim 1, wherein said gate insulating film protective layer is formed of the same material as said gate electrode layer. 3. The semiconductor memory device according to claim 1, wherein said gate insulating film protective layer is a thermal oxide film. 4. A method for manufacturing a semiconductor memory device having a thin film transistor, comprising: forming a semiconductor layer on a substrate; forming a gate insulating film on the semiconductor layer; Forming a gate insulating film protective layer; forming a resist pattern on the gate insulating film protective layer; and forming the gate insulating film and the gate insulating film protective layer by dry etching using the resist pattern as a mask. A method of manufacturing a semiconductor memory device, comprising: a step of removing a portion; and a step of forming a gate electrode layer on the gate insulating film protective layer. 5. The method according to claim 4, wherein the gate insulating film protective layer is a thermal oxide film. 6. A method for manufacturing a semiconductor memory device having a thin film transistor, comprising: forming a semiconductor layer containing a first conductivity type impurity on a substrate; and forming a gate insulating film on the semiconductor layer. Forming a gate electrode layer containing a second conductivity type impurity on the gate insulating film so as to be in contact with the semiconductor layer; and introducing a first conductivity type impurity into the gate electrode layer. A method for manufacturing a semiconductor storage device, comprising: