KR960000363B1 - Semiconductor device and fabricating method thereof - Google Patents

Abstract

a lower wiring layer formed on a semiconductor substrate; the first interlayer insulating film formed for enveloping the lower wiring layer; the contact part formed on the first interlayer insulating film to expose the part of the lower wiring layer; an upper wiring layer connecting tungsten silycide layer with the contact pad by connecting the lower wiring layer through the first contact part .

Description

Semiconductor device and manufacturing method

1 is a cross-sectional view showing a conventional wiring film structure having a contact pad made of tungsten polyside.

2 is a cross-sectional view showing a state in which an upper wiring layer is not deposited and voids are formed due to a decrease in design rules in the wiring film structure of FIG.

3 is a cross-sectional view showing a wiring film structure according to the present invention.

4A to 4D are process flow charts showing a method of forming the wiring film structure of FIG.

Figure 5a is a cross-sectional view showing a conventional wiring film structure used for the contact resistance experiment.

Figure 5b is a cross-sectional view showing the wiring film structure of the present invention used for the contact resistance experiment.

6 is a graph showing experimental values of contact resistance obtained using the wiring film structures of FIGS. 5A and 5B.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a method for manufacturing a wiring film structure for reducing contact resistance.

As the elements of integrated circuits become finer and more integrated, the area of contact holes for connecting the gate electrodes or the source and drain diffusion regions of polycrystalline silicon with the metal wiring becomes very small, and the PN junctions of the diffusion regions are also very small. As the depth becomes thinner, the contact resistance of the wiring is increased, and the PN junction is destroyed due to the wiring formation. In addition, since the reduction of the lateral dimension is a main factor in the actual device miniaturization, the aspect ratio of the surface step increases with high integration. Therefore, the coating power of the metal wiring film formed by the general sputtering method is deteriorated and the wiring is broken, thereby causing a problem of greatly lowering the reliability of the device.

Accordingly, in order to solve the above problems, namely, increase in contact resistance and increase in aspect ratio of contact holes, a technique of interposing a conductive layer called a contact pad between an upper wiring layer and a lower wiring layer has been proposed. As the conductive layer of the contact pad, a structure in which a tungsten silicide (WSi) layer is laminated on a polysilicon layer (hereinafter referred to as 'tungsten polyside') is generally used.

The conventional interconnection film structure having the contact pad made of the tungsten polyside is as shown in FIG. 1, which is described below through a manufacturing process.

Referring to FIG. 1, first, a field oxide film 101 is formed on a semiconductor substrate 100 to define a device isolation region and a device formation region, and a lower wiring layer 1 on the device formation region (see FIG. 1). The diffusion region is illustrated as an example, but may be a pattern of a conductive layer formed on the semiconductor substrate), and then the first interlayer insulating film 3 is formed on the entire surface of the resultant. Subsequently, a photoresist pattern having a desired size is formed on the first interlayer insulating film through photoresist coating, mask exposure and development, and then the photoresist pattern is applied to etch the first interlayer insulating film to a desired portion. A first contact hole is formed to expose the lower wiring layer.

After forming the first contact hole, a conductive layer for forming a contact pad, for example, a polysilicon layer 5a and a tungsten silicide layer 5b doped with impurities, are sequentially stacked and patterned on the entire surface of the resultant to form a tungsten polyside. The contact pads 5 are formed, and a second interlayer insulating film 7 is formed on the entire surface of the resultant. Subsequently, a photoresist pattern having a desired size is formed on the second interlayer insulating film through a process such as photoresist coating, mask exposure and development, and then the photoresist pattern is applied to etch the second interlayer insulating film to a desired portion. A second contact hole for exposing the contact pad 5 connected to the lower wiring layer 1 is formed.

After the formation of the second contact hole, a barrier metal layer 9, for example titanium (Ti), or a double layer of titanium and titanium nitride (TiN), and an upper wiring layer 11, for example, aluminum or an aluminum alloy, are sequentially deposited on the entire surface of the resultant. As a result, the lower wiring layer 1 and the upper wiring layer 11 are connected.

As described above, the conventional method for manufacturing a wiring film is a contact made of polyside because it is subjected to a heat treatment process using an oxide film such as a high temperature oxide (HTO) film or a BOSG (Boro-Phosphorus Silicate Glass) film as an interlayer insulating film. The lower tungsten silicide layer in the pad is partially oxidized and its composition is changed. Therefore, when trying to connect the upper wiring layer, the contact resistance is large, there is a problem that the value change is very severe.

The contact resistance of the contact pad made of tungsten polyside and the upper wiring layer is from several kΩ to several tens of kΩ (when the contact hole has a size of 0.6 µm), which is larger than the expected value (hundreds of Ω) and where the change in value is formed. It is severe depending on process and is bad in reproducibility.

In addition, the aspect ratio varies according to the type and design rule of the semiconductor device. For example, the pattern size of the lower wiring layer is reduced and the contact pad size is reduced due to the reduction of the design rule due to the high integration of the semiconductor device. As shown in FIG. 2, a problem arises in that the barrier metal layer and the upper wiring layer are not properly covered. As another example, a void may occur in the second contact hole when the upper wiring layer is formed.

Therefore, an object of the present invention is to provide a wiring film structure that can reduce the contact resistance by improving the contact pad technology to solve the problems of the prior art as described above.

Another object of the present invention is to provide a method for producing a wiring film structure which can efficiently produce a wiring film having the above structure.

The present invention to achieve the above object, the lower wiring layer formed on the semiconductor substrate; A first interlayer insulating film formed to cover the lower wiring layer; A first contact hole formed in the first interlayer insulating film to expose a portion of the lower wiring layer; A contact pad connected to the lower interconnection layer through the first contact hole and including a tungsten silicide layer in a sandwich structure; And an upper wiring layer connected to the contact pad.

According to another aspect of the present invention, there is provided a method of forming a lower wiring layer on a semiconductor substrate; Forming a first interlayer insulating film to cover the lower wiring layer; Forming a first contact hole in the first interlayer insulating film to expose a portion of the lower wiring layer; Forming a contact pad connected to the lower interconnection layer through the first contact hole and including a tungsten-silicide layer in a sandwich structure; Forming a second interlayer insulating film to cover the contact pads; Forming a second contact hole in the second interlayer insulating film to expose a portion of the contact pad; And forming an upper wiring layer connected to the contact pad through the second contact hole.

Hereinafter, with reference to the accompanying drawings will be described the present invention. Like parts in the accompanying drawings will be denoted by the same reference numerals.

3 is a cross-sectional view showing a wiring film structure according to the present invention.

Referring to FIG. 3, first, a field oxide film 101 is formed on a semiconductor substrate 100 to define a device isolation region and a device formation region, and the lower wiring layer 1, for example, an impurity, is formed on the device formation region. The diffusion region is formed, and a part of the lower wiring layer 1 is exposed by the first contact hole formed in the first interlayer insulating layer 3, and the doped polysilicon / tungsten silicide / impurity is doped. It is connected to a contact pad 5 made of a polysilicon stack structure, a part of the contact pad 5 is exposed by a second contact hole formed in the second interlayer insulating film 7, the barrier metal layer 9 and A polysilicon plug 8 connected to the upper interconnection layer 11 and doped with impurities in the second contact hole between the contact pad 5 and the barrier metal layer 9 is interposed therebetween.

4A to 4D are process flowcharts showing the method of forming the wiring film structure of FIG.

4A illustrates a process of forming the lower wiring layer 1 and the first contact channel CH1. First, a field oxide film 101 is formed on the semiconductor substrate 100 to define device isolation regions and device formation regions. A lower interconnection layer 1, for example, an impurity diffusion region, is formed on the device formation region, and a first interlayer insulating film 3, for example, an HTO film or a BPSG film, is formed on the entire surface of the resultant product, and then a photo is formed on the first interlayer insulating film. Through the process of resist coating, mask exposure and development, a photoresist pattern having a desired size is formed. Subsequently, the first interlayer insulating layer is etched by applying the photoresist pattern to form a first contact hole CH1 for exposing the lower wiring layer to a desired portion.

FIG. 4B illustrates a process of forming the contact pad 5. The first conductive layer 5A, for example, the polysilicon and the second conductive layer 5B doped with impurities, are formed on the entire surface of the resultant after the first contact hole is formed. Tungsten silicide, and the third conductive layer 5C, such as polysilicon doped with impurities, polysilicon doped with impurities, black or amorphous silicon, are formed in turn, and then tungsten silicide is formed by silicon patterning. The contact pad 5 which entered into the sandwich structure between them is completed. At this time, since the tungsten silicide is covered with silicon, it is possible to prevent the oxidation reaction or the change of composition due to the subsequent subsequent step (heat treatment step), which is a problem in the prior art.

FIG. 4C illustrates a process of forming the second contact hole CH2. After the process of forming the contact pad 5, the second interlayer insulating film 7, for example, the HTO film or the BPSG film is formed on the entire surface of the resultant material. A photoresist pattern having a desired size is formed on the interlayer insulating film by a process such as photoresist coating, mask exposure and development. Subsequently, the second interlayer insulating layer is etched by applying the photoresist pattern to form a second contact hole CH2 for exposing the lower wiring layer to a desired portion.

4d illustrates a process of forming the fourth conductive layer plug 8, the barrier metal layer 9, and the upper wiring layer 11. First, the inside of the second contact hole is formed on the entire surface of the resultant product in which the second contact hole is formed. By depositing a fourth conductive layer for filling, such as polysilicon doped with impurities (or amorphous silicon doped with impurities), and then performing an etch back process, as shown, the second contact A fourth conductive layer plug 8, i.e., a polysilicon plug doped with impurities (or an amorphous silicon plug doped with impurities) is formed only in the hole. The lower wiring layer 1 and the lower barrier layer 1 are deposited by sequentially depositing a barrier metal layer 9 such as titanium, or a double layer of titanium and titanium nitride, and an upper wiring layer 11, such as aluminum or an aluminum alloy, on the entire surface of the product on which the polysilicon plug 8 is formed. The upper wiring layer 11 is connected.

Figure 5a is a cross-sectional view showing a conventional wiring film structure used for the contact resistance experiment, Figure 5b is a cross-sectional view showing the wiring film structure of the present invention used for the contact resistance experiment.

Referring to FIGS. 5A and 5B, a structure except the device forming region is illustrated to clearly check resistance improvement between the conductive layer plug 8, for example, the polysilicon plug and the contact pad 5. FIG. 5A is a wiring film structure according to the conventional method, and FIG. 5B is a wiring film structure according to the present invention. Referring to the data for the experiment, the contact hole in which the polysilicon plug 8 is formed is 0.6 µm in diameter. The height of the polysilicon plug 8 is about 3000 mm 3. The thickness of the tungsten silicide layer, which is the second conductive layer 5b, is 1500 kPa and 1000 kPa in FIGS. 5A and 5B, respectively, and the thickness of the first and third conductive layers 5A and 5C is about 500 kPa, respectively. to be.

6 is a graph showing experimental values of contact resistance obtained using the wiring film structures shown in FIGS. 5A and 5B.

Referring to FIG. 6, the graph of FIG. 6 is a resistance value obtained by dividing the structure of FIGS. 5A and 5B in series by measuring 200 and dividing by 400, and corresponds to a resistance value per contact. The X axis represents wafer # and the Y axis represents contact resistance, respectively. The wafer numbers Wl to Wl6 represent the resistance values obtained in the conventional wiring film structure of FIG. 5a, indicating that the resistance value is very changeable for each position in the wafer, and there is no reproducibility. The resistance value obtained in the wiring film structure according to the present invention shown in FIG. 5B is shown. The contact resistance value of the tungsten silicide layer of the present invention in a sandwich structure drops to 500 Ω or less, and the uniformity in the wafer is achieved. This shows good.

Here, as shown in FIG. 6, one wafer has six resistance values, which are based on the flat surface of the wafer, and the flat surface portion is the bottom of the wafer. The part farthest from the flat surface is at the top, the middle part of the bottom and the top is at the center, and the right and left parts are divided based on the flat surface. It shows the resistance of each part and the average of these (5 parts).

The present invention described above is not only applied to the structure having the impurity diffusion region as a lower wiring layer, but also a gate electrode of a transistor as a lower wiring layer (used in the same function, and used as a gate electrode of a transistor of a DRAM (SRAM) as a memory device). Of course, black may be extended to other structures, such as a contact pad including a tungsten silicide layer in a sandwich structure, within the limits of the technical idea of the present invention.

As described above, in the wiring film structure according to the present invention, tungsten silicide is a component of a contact pad (typically, tungsten polyside) for connecting the upper wiring layer and the lower wiring layer after the formation of an HTO film or a BPSG film, which is an interlayer insulating film. In order to eliminate the problem of partially oxidizing during the heat treatment process or changing its composition, after depositing the tungsten silicide layer, a polysilicon layer doped with an impurity, a polysilicon layer not doped with an impurity, or an amorphous silicon layer By directly depositing, the property of the tungsten silicide layer was kept constant.

Therefore, the contact resistance value can be reduced when the upper wiring layer and the lower wiring layer are connected, and the uniformity and reproducibility of the contact resistance value can be improved, thereby increasing the integration density and improving the yield.

In addition, since the property of the tungsten silicide layer is constant, it is not affected by the subsequent process, so that the process margin of the heat treatment process during the entire process is greatly increased, and the lifting phenomenon of the tungsten silicide layer is also eliminated.

In addition, even when the polysilicon plug is used, since the contact resistance is low and the device characteristics are stabilized, the contact size for connecting the upper wiring layer and the lower wiring layer can be further reduced, thereby increasing the layout margin of the memory cell. In addition, the area of semiconductor devices can be reduced, enabling the development of next generation highly integrated memory cells.

In addition, since the contact resistance value is low and uniform, the probability of unbalance of the electrical characteristics of the memory cell is reduced, so that the stability of the cell may be improved even when the operating power supply voltage is low.

Claims (20)

A semiconductor device having a contact pad for connecting a lower wiring layer and an upper wiring layer, the semiconductor device comprising: the lower wiring layer formed on a semiconductor substrate; A first interlayer insulating film formed to cover the lower wiring layer; A first contact hole formed in the first interlayer insulating film to expose a portion of the lower wiring layer; A contact pad connected to the lower interconnection layer through the first contact hole and having a tungsten silicide layer; And the upper wiring layer connected to the contact pad. The semiconductor device of claim 1, wherein the semiconductor device comprises: a second interlayer insulating layer formed between the contact pad and the upper wiring layer to cover the contact pad; A second contact hole formed in the second interlayer insulating film to expose a portion of the contact pad; A conductive layer plug formed in the second contact hole; And a barrier metal layer formed on the entire surface of the resultant after the conductive layer plug is formed. The method of claim 1, wherein the contact pad has the tungsten silicide layer interposed therebetween, and a lower layer thereof is a polysilicon layer doped with impurities, and an upper layer thereof is polysilicon doped with impurities or doped with impurities. A semiconductor device, characterized in that it is undoped polysilicon or amorphous silicon. The semiconductor device according to claim 1 or 2, wherein the first and second interlayer insulating films are HTO films or BPSG films. 4. The semiconductor device of claim 3, wherein the conductive layer plug is a polysilicon plug doped with an impurity. 4. The semiconductor device of claim 3, wherein the conductive layer plug is an amorphous silicon plug doped with impurities. The semiconductor device according to claim 2, wherein the barrier metal layer is titanium or a double layer of titanium and titanium nitride. The semiconductor device according to claim 1, wherein the lower wiring layer is an impurity diffusion region. The semiconductor device of claim 1, wherein the lower wiring layer is a transistor gate electrode. A method of manufacturing a semiconductor device having a contact pad for connecting a lower wiring layer and an upper wiring layer, the method comprising: forming the lower wiring layer on a semiconductor substrate; Forming a first interlayer insulating film to cover the lower wiring layer; Forming a first contact hole in the first interlayer insulating film to expose a portion of the lower wiring layer; Forming the contact pad having a sandwich structure connected to the lower interconnection layer through the first contact hole and having a silicon layer formed at both sides thereof with a tungsten silicide layer interposed therebetween; Forming a second interlayer insulating film to cover the contact pad, and forming a second contact hole in the second interlayer insulating film to expose a portion of the contact pad; And forming the upper wiring layer connected to the contact pad through the second contact hole. The method of claim 10, further comprising: forming a conductive layer plug by forming a conductive layer on the entire surface of the resultant and then etching back after forming the second contact hole; And forming the barrier metal layer and the upper wiring layer in order on the entire surface of the resultant after the formation of the conductive layer plug. 12. The method of claim 11, wherein the conductive layer plug is a polysilicon plug doped with an impurity. 12. The method of claim 11, wherein the conductive layer plug is an amorphous silicon plug doped with an impurity. The semiconductor device of claim 10, wherein the contact pad is formed by sequentially stacking and patterning a first conductive layer, tungsten silicide, and a second conductive layer on an entire surface of a resultant in which the first contact hole is formed. Method of manufacturing the device. 15. The method of claim 14, wherein the first conductive layer is a polysilicon layer doped with impurities. 16. The method of claim 15, wherein the second conductive layer is polysilicon doped with impurities or polysilicon or amorphous silicon doped with impurities. The method of claim 11, wherein the barrier metal layer is titanium or a double layer of titanium and titanium nitride. The method of claim 10, wherein the lower wiring layer is an impurity diffusion region. The method of claim 10, wherein the lower wiring layer is a gate electrode of a transistor. The method of claim 10, wherein the lower wiring layer is a contact pad including a tungsten silicide layer in a sandwich structure.