JPH10261660A - Electrode of laminated structure and manufacture therefor - Google Patents

Electrode of laminated structure and manufacture therefor

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Publication number
JPH10261660A
JPH10261660A JP6575397A JP6575397A JPH10261660A JP H10261660 A JPH10261660 A JP H10261660A JP 6575397 A JP6575397 A JP 6575397A JP 6575397 A JP6575397 A JP 6575397A JP H10261660 A JPH10261660 A JP H10261660A
Authority
JP
Japan
Prior art keywords
electrode
laminated
layers
layer
laminated structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP6575397A
Other languages
Japanese (ja)
Inventor
Kojiro Kawai
耕二郎 川合
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Tungsten Co Ltd
Original Assignee
Tokyo Tungsten Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Tungsten Co Ltd filed Critical Tokyo Tungsten Co Ltd
Priority to JP6575397A priority Critical patent/JPH10261660A/en
Publication of JPH10261660A publication Critical patent/JPH10261660A/en
Withdrawn legal-status Critical Current

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Abstract

PROBLEM TO BE SOLVED: To reduce the usage of Mo, a rare metal, to reduce the entire cost and obtain an electrode of laminated structure with a high breakdown voltage and reliability maintained which can be used in a wide variety of applications as a substitute for Mo electrode by forming both the ends in the direction of lamination from a Mo layer in a laminate formed by alternately laminating Mo layers and a Cu layer. SOLUTION: The electrode is a laminate, formed by alternately laminating Mo layers 12 and a Cu layer 14. Both the ends of the laminate in the direction of lamination are formed on the Mo layers 12 having the same thickness, and the layers 12, 14 constituting the laminate are jointed with one another using brazing material 21. For example, an electrode 7 of laminated structure for use in semiconductor devices is formed by jointing Mo parts 12, 12 with upper and lower base 15, formed on a Cu part 14 on the upper and lower sides, using brazing material 21. Further, for example, the parallelism of the mating faces of the Mo layers 12 and the Cu layer 14 is controlled to within 5 μm/10mm or below, and either or both of the Mo layers 12 and the Cu layer 14 are plated with Ni. In addition a brazing material 21 containing Ag and Cu is used.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は,積層構造電極とそ
の製造方法に関し,詳しくは,大電力素子に使用される
半導体チップに直接接触する電極に用いられる積層構造
電極とその製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a laminated electrode and a method of manufacturing the same, and more particularly, to a laminated electrode used for an electrode directly contacting a semiconductor chip used in a high power device and a method of manufacturing the same.

【0002】[0002]

【従来の技術】大電力素子に使用されるシリコン(S
i)チップに直接使用する電極として金属モリブデン
(Mo)が使用されている。Moは,他の金属に比べ熱
膨張が小さく,その熱膨張係数がSiチップの熱膨張係
数に近いために,使用時の発熱による熱膨張差が少ない
利点がある。また,Moは,セラミック等に比べ熱伝導
率が大きくSiチップからの発熱を逃がし,Siチップ
の熱破壊を防ぐ働きをする。
2. Description of the Related Art Silicon (S) used for high power devices
i) Metal molybdenum (Mo) is used as an electrode directly used for the chip. Mo has the advantage that the thermal expansion is smaller than other metals and the thermal expansion coefficient is close to the thermal expansion coefficient of the Si chip. Further, Mo has a higher thermal conductivity than ceramics or the like, and has a function of releasing heat generated from the Si chip and preventing thermal destruction of the Si chip.

【0003】従来法によるMo電極の製造は次のように
行われていた。
[0003] Manufacturing of a Mo electrode by a conventional method has been performed as follows.

【0004】図8は従来法によるMo電極の製造方法の
説明に供せられる図である。先ず,図8(a)に示すよ
うに,素材としてMo板51を使用する。Mo板51
は,Mo純度99.9%以上を有する圧延ロールで圧延
された板材であり,板厚が製品の厚さと研磨代分あるも
のを用意する。
FIG. 8 is a diagram for explaining a method of manufacturing a Mo electrode according to a conventional method. First, as shown in FIG. 8A, a Mo plate 51 is used as a material. Mo plate 51
Is a plate rolled by a roll having a Mo purity of 99.9% or more, and a plate having a thickness corresponding to the product thickness and a polishing allowance is prepared.

【0005】次に,図8(b)に示すように,コッタマ
シンにより角板52に切断する(荒取り)。尚,図8
(b)中において,一点鎖線は切断線を示している。
[0005] Next, as shown in FIG. 8B, the rectangular plate 52 is cut by a cotter machine (roughing). FIG.
In (b), a dashed line indicates a cutting line.

【0006】次に,図8(c)に示すように,角板52
の外周部をフライスで切断し,寸法出し,直角度を出し
て,加工板53を得る。尚,上下面は,研磨又はラップ
を行い厚み出しを行う。
[0006] Next, as shown in FIG.
Is cut with a milling machine, the dimensions are set, and the squareness is set, to obtain a processed plate 53. The upper and lower surfaces are polished or wrapped to increase the thickness.

【0007】更に,図8(d)に示すように,左図に示
した研磨上がりの加工板53の斜線部をフライスによっ
て削り取り,段付けを行い,右図に示すMo電極54の
製品を得る。
Further, as shown in FIG. 8 (d), a hatched portion of the polished work plate 53 shown in the left diagram is scraped off by milling and stepped to obtain a Mo electrode 54 product shown in the right diagram. .

【0008】[0008]

【発明が解決しようとする課題】しかしながら,Moを
使用した電極は,鉄(Fe)や銅(Cu)に比べ,硬
く,加工時の工具の消耗が激しく,加工に時間がかか
り,加工コストが高くなるという欠点を有した。
However, an electrode using Mo is harder than iron (Fe) or copper (Cu), consumes a lot of tools at the time of processing, takes a long time to process, and requires a high processing cost. There was a drawback of becoming high.

【0009】特に,上述したように,段付け加工が必要
な製品では,切削代が大きく,材料の無駄が多かった。
さらには,Moはレアメタルであるため,材料も高価で
あり,一部の高耐圧と高い信頼性を要求される装置に使
用が限定されてきた。
[0009] In particular, as described above, in the case of products that require step processing, the cutting allowance is large and material is wasted.
Furthermore, since Mo is a rare metal, its material is expensive, and its use has been limited to some devices that require high withstand voltage and high reliability.

【0010】そこで,本発明の技術的課題は,レアメタ
ルであるMoの使用量を減らして全体のコストを下げ,
且つ高耐圧性と高信頼性を維持したMo電極の代用とし
て汎用的に使用できる積層構造電極とその製造方法とを
提供することにある。
[0010] Therefore, the technical problem of the present invention is to reduce the amount of Mo, which is a rare metal, to lower the overall cost,
Another object of the present invention is to provide a multilayer structure electrode which can be generally used as a substitute for a Mo electrode maintaining high withstand voltage and high reliability, and a method of manufacturing the same.

【0011】[0011]

【課題を解決するための手段】本発明によれば,Mo層
とCu層を交互に積層した積層体であって,前記積層体
は,積層方向両端が同一の厚さのMo層に形成され,前
記積層体を構成する各層は,ろう材を用いて接合されて
いることを特徴とする積層構造電極が得られる。
According to the present invention, there is provided a laminate in which Mo layers and Cu layers are alternately laminated, wherein the laminate has a Mo layer having the same thickness at both ends in the laminating direction. Each layer constituting the laminate is joined by using a brazing material to obtain a laminated electrode.

【0012】また,本発明によれば,前記積層構造電極
において,前記Mo層と前記Cu層の内の少なくとも一
方にNiめっきが施されていることを特徴とする積層構
造電極が得られる。
Further, according to the present invention, there is provided a laminated structure electrode in which at least one of the Mo layer and the Cu layer is plated with Ni in the laminated structure electrode.

【0013】また,本発明によれば,前記積層構造電極
において,前記ろう材は,Ag及びCuを含むことを特
徴とする積層構造電極が得られる。
Further, according to the present invention, in the laminated electrode, the brazing material contains Ag and Cu.

【0014】ここで,本発明においては,Ag及びCu
を含むろう材として,JIS Z−3261に規定され
るBAg−8(Ag72%Cu28%)が好ましい。
Here, in the present invention, Ag and Cu
As a brazing filler metal containing, BAg-8 (Ag 72% Cu 28%) specified in JIS Z-3261 is preferable.

【0015】また,本発明によれば,前記いずれかの積
層構造電極において,少なくとも300W/m・Kの熱
伝導率を有することを特徴とする積層構造電極が得られ
る。
According to the present invention, there is provided any one of the above-mentioned laminated electrodes having a thermal conductivity of at least 300 W / m · K.

【0016】さらに,本発明によれば,Mo層とCu層
の接合面の平面度を5μm/10mm以下にして,ろう
接して交互に積層することを特徴とする積層構造電極の
製造方法が得られる。
Further, according to the present invention, there is provided a method of manufacturing a laminated structure electrode characterized in that the flatness of the joint surface between the Mo layer and the Cu layer is 5 μm / 10 mm or less, and the layers are alternately brazed. Can be

【0017】[0017]

【発明の実施の形態】以下,本発明の実施の形態につい
て図面を参照して説明する。
Embodiments of the present invention will be described below with reference to the drawings.

【0018】図1は本発明の実施の形態による積層構造
電極を用いた半導体装置を概略断面図である。
FIG. 1 is a schematic sectional view of a semiconductor device using a laminated electrode according to an embodiment of the present invention.

【0019】図1を参照すると,半導体装置10は,半
導体チップとしてSiチップ1と,Siチップ1を搭載
する熱補償板2と,熱補償板2の底部に設けられたコレ
クタ電極3と,Siチップ上に設けられた積層構造電極
7と,積層構造電極7の上部に設けられたエミッタ電極
4と,Siチップ1から積層構造電極7及びエミッタ電
極1に隣接し,上方に延在するゲート電極6と,これら
の周囲を覆う角筒形状のテフロンガイド5と,このテフ
ロンガイド5の上下両端部を,各電極を露出させて覆う
セラミックからなる封止部材8a,8bを備えて構成さ
れている。
Referring to FIG. 1, a semiconductor device 10 includes a Si chip 1 as a semiconductor chip, a heat compensator 2 on which the Si chip 1 is mounted, a collector electrode 3 provided on the bottom of the heat compensator 2, A stacked electrode 7 provided on the chip, an emitter electrode 4 provided above the stacked electrode 7, and a gate electrode extending upward from the Si chip 1 adjacent to the stacked electrode 7 and the emitter electrode 1. 6, a Teflon guide 5 in the form of a square tube that covers the periphery thereof, and sealing members 8a and 8b made of ceramic that cover the upper and lower ends of the Teflon guide 5 by exposing the respective electrodes. .

【0020】図2は,図1の半導体装置に用いられる積
層構造電極7を示す斜視図である。図2に示すように,
積層構造電極7は,台部15を備えた銅(Cu)部品1
4の上下の台部15にMo部品12,12をろう材21
を用いて夫々接合した構成を有している。
FIG. 2 is a perspective view showing the laminated electrode 7 used in the semiconductor device of FIG. As shown in FIG.
The laminated structure electrode 7 is a copper (Cu) component 1 having a base 15.
The Mo parts 12, 12 are mounted on the upper and lower
Have a configuration in which they are joined together.

【0021】図3〜図7は図2の積層構造電極7の製造
工程を順に示す図である。図3〜図7を用いて積層構造
電極7の製造工程について説明する。
FIG. 3 to FIG. 7 are views sequentially showing the steps of manufacturing the laminated electrode 7 of FIG. The manufacturing process of the laminated structure electrode 7 will be described with reference to FIGS.

【0022】図3に示すように,先ず素材として,圧延
により加工されている純度99.9%以上の純Mo板1
1を用意した。
As shown in FIG. 3, first, as a raw material, a pure Mo plate 1 having a purity of 99.9% or more, which is processed by rolling.
1 was prepared.

【0023】次に,図4に示すように,純Mo板11か
らプレス機によりMo片を打ち抜く。ここで,平面度は
ボイド率10%以下を保証する為に,各Mo部品のろう
付け面となる面は,平面度5μm/10mm以下に形成
されMo部品12となる。
Next, as shown in FIG. 4, Mo pieces are punched out of the pure Mo plate 11 by a press machine. Here, in order to guarantee a flatness of 10% or less in void ratio, the surface to be a brazing surface of each Mo component is formed into a flatness of 5 μm / 10 mm or less and becomes a Mo component 12.

【0024】一方,Mo板11とは別に,図5に示すよ
うに,Cu素材として,無酸素銅板13を用意する。
On the other hand, separately from the Mo plate 11, as shown in FIG. 5, an oxygen-free copper plate 13 is prepared as a Cu material.

【0025】次に,図6に示すように,プレス加工によ
り,段付けプレス加工を行う。ろう付け面となる上下の
段部の台部15の表面は,ボイド率10%以下を保証す
る為に,平面度5μm/10mmが必要である。
Next, as shown in FIG. 6, step forming press working is performed by press working. The surface of the upper and lower steps 15 serving as a brazing surface needs to have a flatness of 5 μm / 10 mm in order to guarantee a void ratio of 10% or less.

【0026】次に,図7(a)に示すように,ベースと
なるカーボン治具17に製品形状に対応した形状の溝1
8を加工し,一方,蓋となるカーボン治具16には,製
品形状に対応した孔部19を形成し,溝部18と孔部1
9とで,ポケット部を形成する。このポケット部内に各
部品を挿入する。
Next, as shown in FIG. 7A, a groove 1 having a shape corresponding to the product shape is formed in a carbon jig 17 serving as a base.
On the other hand, a hole 19 corresponding to the product shape is formed in the carbon jig 16 serving as a lid, and the groove 18 and the hole 1 are formed.
9 forms a pocket portion. Each part is inserted into this pocket.

【0027】図7(b)に示すように,挿入する部品
は,Mo部品12,BAg−8(JIS Z−326
1,参照)からなるろう材21,Cu部品14,BAg
−8からなるろう材21,Mo部品12の順で,カーボ
ン治具に挿入する。この時のMo部品12とCu部品1
4の片方又は両方に前処理としてろう付け性向上を目的
としたメッキ(Ni,Ag,又はAu)を施すことが好
ましい。これらの積層された部品を挿入したカーボン治
具16,17を還元雰囲気を備えた炉に通して,最大8
30℃以上でろう付け処理を行う。
As shown in FIG. 7B, the parts to be inserted are Mo parts 12, BAg-8 (JIS Z-326).
1, see)), Cu parts 14, BAg
-8 are inserted into the carbon jig in this order. Mo part 12 and Cu part 1 at this time
It is preferable to apply plating (Ni, Ag, or Au) for improving the brazing property as one of the pretreatment to one or both of them. The carbon jigs 16 and 17 into which these laminated parts are inserted are passed through a furnace provided with a reducing atmosphere, and a maximum of 8
Perform brazing at 30 ° C. or higher.

【0028】以上の工程により,図2に示された積層構
造電極7が製造される。
Through the above steps, the laminated electrode 7 shown in FIG. 2 is manufactured.

【0029】このように製造された積層構造電極7は,
Cu部品14に段付け加工を施すことによって,Moの
使用量を減小させることができる。また,Cu部品14
の段付けの高さを調節することによって,両側に貼り合
わされるMo部品12の厚みを同一にして,同じ部品を
使用できるようにしてあり,また,両側を同じ厚さのM
o板で挟む構造にすることで,Cuとの熱膨張差による
変形を防止している。
The thus-produced laminated electrode 7 has
By performing the step processing on the Cu component 14, the usage amount of Mo can be reduced. In addition, Cu parts 14
By adjusting the height of the step, the thickness of the Mo parts 12 bonded on both sides is made the same so that the same parts can be used.
The structure sandwiched between o-plates prevents deformation due to the difference in thermal expansion with Cu.

【0030】また,片面がCuの場合においては,Mo
に比べて軟らかいCuが優先的にラップされ,片減りし
てしまうが,本発明の実施の形態に積層構造電極7にお
いては,両側をMo板で挟むことによって,これを防止
するとともに,トータルの厚み調整,面精度(平面度,
平行度)出しを目的とした両面ラップ処理が容易にでき
る。
When one surface is made of Cu, Mo
Although soft Cu is preferentially wrapped and partially reduced as compared with the above, in the embodiment of the present invention, in the laminated structure electrode 7, this is prevented by sandwiching both sides with Mo plates, and the total Thickness adjustment, surface accuracy (flatness,
Double-sided lapping for the purpose of parallelism) can be easily performed.

【0031】(具体例)次に,本発明の実施の形態によ
る積層構造電極の製造の具体例に再び図2乃至図7を参
照して説明する。
(Specific Example) Next, a specific example of the production of the laminated electrode according to the embodiment of the present invention will be described with reference to FIGS. 2 to 7 again.

【0032】図3に示すように,厚さ1.0mm,幅6
5mm,長さ300mmの純度99.9%Mo圧延板1
1を用意した。
As shown in FIG. 3, the thickness is 1.0 mm and the width is 6 mm.
5mm, 300mm length, 99.9% Mo rolled plate 1
1 was prepared.

【0033】次に,図2に示すように,打ち抜きプレス
機によりMo板片を17mm平方の寸法で厚さ1.0m
mに打ち抜いた。ここで,表面を平面度30μm/10
mm以下に仕上げ,表面に厚さ2μmのNiめっきを施
し,Mo部品12とする。ここで,Niめっきは,ろう
付けの確実性を増す為に行う。
Next, as shown in FIG. 2, a Mo plate piece was sized to a size of 17 mm square and a thickness of 1.0 m by a punching press machine.
m. Here, the surface is set to a flatness of 30 μm / 10
mm or less, and the surface is plated with Ni having a thickness of 2 μm to obtain Mo parts 12. Here, Ni plating is performed to increase the reliability of brazing.

【0034】一方,図5に示すように,銅素材として,
厚さ2.5mm,幅20mm,長さ300mmの無酸素
銅板13を用意した。
On the other hand, as shown in FIG.
An oxygen-free copper plate 13 having a thickness of 2.5 mm, a width of 20 mm, and a length of 300 mm was prepared.

【0035】図6に示すように,打ち抜きプレス機によ
り17mm平方の台部15を両面に備えた20mm平
方,厚さ2.5mmの段付き形状にプレス加工をする。
これをCu部品14とする。
As shown in FIG. 6, a 20 mm square, 2.5 mm thick stepped shape having a 17 mm square base 15 on both sides is pressed by a punching press machine.
This is referred to as a Cu component 14.

【0036】次に,図7(b)に示すように,Mo部品
12,ろう材21,Cu部品14,ろう材21,Mo部
品12の順に,図7(a)に示すカーボン治具20に挿
入する。ここで,ろう材21は,10mm平方で厚さ
0.1mmのBAg−8(Ag72%Cu28%)を使
用した。
Next, as shown in FIG. 7B, the Mo part 12, the brazing material 21, the Cu part 14, the brazing material 21, and the Mo part 12 are sequentially placed on the carbon jig 20 shown in FIG. insert. Here, BAg-8 (Ag 72% Cu 28%) having a square of 10 mm and a thickness of 0.1 mm was used as the brazing material 21.

【0037】この積層された各部品が挿入されたカーボ
ン治具20を加熱炉の水素雰囲気中で,830℃以上5
分間加熱した。冷却後,カーボン治具20より取り出し
た。ここで,カーボン治具20は,ろう付けの際の寸法
精度向上に用いられる。取り出された一体となった積層
構造電極全体にNiめっきを施した。Mo部両面にラッ
プ加工(#8000)を施し,全体の厚さ調整,平面
度,平行度出しを行った。ろう付け後に,Niめっきを
表面に施す事で,ラップ加工時に発生するろう付け部分
へのラップ砥粒の汚れを防止することができる。
The carbon jig 20 into which the laminated components are inserted is placed in a hydrogen atmosphere of a heating furnace at 830 ° C. or higher.
Heated for minutes. After cooling, it was taken out of the carbon jig 20. Here, the carbon jig 20 is used for improving dimensional accuracy during brazing. Ni plating was applied to the whole of the taken-out integrated laminated structure electrode. Lapping (# 8000) was performed on both sides of the Mo portion, and the overall thickness was adjusted, flatness, and parallelism were determined. By applying Ni plating to the surface after brazing, it is possible to prevent lap abrasive grains from being contaminated on the brazed portion during lapping.

【0038】下記表1は,上記のように製造された本発
明の実施の形態による積層構造電極と従来法によるMo
電極の熱特性を夫々示している。
Table 1 below shows the laminated electrode according to the embodiment of the present invention manufactured as described above and the Mo electrode according to the conventional method.
Each shows the thermal characteristics of the electrodes.

【0039】[0039]

【表1】 [Table 1]

【0040】上記表1に示すように,本発明の実施の形
態による積層構造電極は,従来品に比べて熱膨張係数が
少し大きくなるが,使用上問題の無い範囲であり,熱伝
導率は,従来品より約2倍良くなっている。ここで,熱
伝導率は,ろう付け部のボイドの大きさに影響を受け
る。下記表2は,本発明の実施の形態による積層構造電
極のボイド率を示している。また,このろう付け部のボ
イド率と熱伝導率との関係を下記表3に示す。
As shown in Table 1 above, the laminated electrode according to the embodiment of the present invention has a slightly larger coefficient of thermal expansion than the conventional product, but within a range where there is no problem in use, and the thermal conductivity is lower. , Which is about twice as good as conventional products. Here, the thermal conductivity is affected by the size of the void at the brazing portion. Table 2 below shows the void ratio of the laminated electrode according to the embodiment of the present invention. Table 3 below shows the relationship between the void fraction and the thermal conductivity of the brazed portion.

【0041】[0041]

【表2】 [Table 2]

【0042】[0042]

【表3】 [Table 3]

【0043】上記表3に示すように,熱伝導率は,ろう
付け部のボイドの大きさにより影響を受けるが,本発明
の実施の形態による積層構造電極のろう付け部のボイド
率が10%でも,熱伝導率は317.323W/m・K
と従来品の2倍の熱伝導率を示し,また本発明の実施の
形態による積層構造電極のボイド率は,上記表2に示す
ように最大時でも6.25%であった。
As shown in Table 3 above, the thermal conductivity is affected by the size of the void in the brazed portion, and the void ratio in the brazed portion of the laminated electrode according to the embodiment of the present invention is 10%. But the thermal conductivity is 317.323 W / m · K
And a thermal conductivity twice that of the conventional product, and the void ratio of the laminated electrode according to the embodiment of the present invention was 6.25% at the maximum as shown in Table 2 above.

【0044】[0044]

【発明の効果】以上,説明したように,本発明によれ
ば,一体のMo電極よりもCu部品をMo部品で挟み,
ろう付けした構造を備えているために,レアメタルであ
り,且つ高価なMoの使用量を減らし,資源の節約がで
きるとともに,加工性を向上させ,全体のコストを下げ
且つ熱膨張率をわずかしか変化させないで熱伝導率を2
倍にしたMo電極として使用できる積層構造電極とその
製造方法とを提供することができる。
As described above, according to the present invention, a Cu component is sandwiched between Mo components rather than an integral Mo electrode,
Since it has a brazed structure, it is possible to reduce the use of rare metal and expensive Mo, save resources, improve workability, lower overall cost and reduce the coefficient of thermal expansion only slightly. 2 without changing the thermal conductivity
It is possible to provide a laminated structure electrode that can be used as a doubled Mo electrode and a method of manufacturing the same.

【0045】また,本発明によれば,プレス機による打
ち抜き加工及び炉中のろう付け加工を導入でき,Mo電
極の製造に用いられた個々に加工しなければならない切
削加工に比べて量産が可能であり,加工エネルギーの節
約ができるとともに,工業化が容易である積層構造電極
とその製造方法とを提供することができる。
According to the present invention, punching by a press machine and brazing in a furnace can be introduced, and mass production can be performed as compared with the cutting which must be performed individually used in the production of Mo electrodes. In addition, it is possible to provide a laminated structure electrode which can save processing energy and can be easily industrialized, and a method for manufacturing the same.

【0046】また,本発明によれば,コストを低減する
ことができ,今まで一部の高耐圧,高信頼性を要求され
る装置にしか使用できなかったMo電極の代用として,
汎用的に使用できる積層構造電極を提供することができ
る。
Further, according to the present invention, the cost can be reduced, and as a substitute for the Mo electrode which has been used only in some devices requiring high withstand voltage and high reliability until now,
A laminated electrode that can be used for general purposes can be provided.

【図面の簡単な説明】[Brief description of the drawings]

【図1】図1は本発明の実施の形態による積層構造電極
を用いた半導体装置を概略断面図である。
FIG. 1 is a schematic sectional view of a semiconductor device using a laminated structure electrode according to an embodiment of the present invention.

【図2】図1の半導体装置に用いられる積層構造電極7
を示す斜視図である。
FIG. 2 is a diagram showing a laminated electrode 7 used in the semiconductor device of FIG. 1;
FIG.

【図3】図2の積層構造電極7の製造工程を示す図であ
る。
FIG. 3 is a view showing a manufacturing process of the laminated electrode 7 of FIG. 2;

【図4】図2の積層構造電極7の製造工程を示す図であ
る。
FIG. 4 is a view showing a manufacturing process of the laminated electrode 7 of FIG. 2;

【図5】図2の積層構造電極7の製造工程を示す図であ
る。
FIG. 5 is a view showing a manufacturing process of the laminated electrode 7 of FIG. 2;

【図6】図2の積層構造電極7の製造工程を示す図であ
る。
FIG. 6 is a view showing a manufacturing process of the laminated electrode 7 of FIG. 2;

【図7】(a)及び(b)は図2の積層構造電極7の加
熱工程に用いるカーボン治具を示す図である。
FIGS. 7A and 7B are views showing a carbon jig used in a heating process of the laminated electrode 7 of FIG.

【図8】(a)〜(d)は従来法によるMo電極の製造
方法の説明に供せられる図である。
FIGS. 8A to 8D are views for explaining a method for manufacturing a Mo electrode according to a conventional method.

【符号の説明】[Explanation of symbols]

1 Siチップ 2 熱補償板 3 コレクタ電極 4 エミッタ電極 5 テフロンガイド 6 ゲート電極 7 積層構造電極 8a,8b 封止部材 10 半導体装置 11 Mo板 12 Mo部品 13 無酸素銅板 14 銅(Cu)部品 15 台部 16,17,20 カーボン治具 18 溝部 19 孔部 21 ろう材 51 Mo板 52 角板 53 加工板 54 Mo電極 DESCRIPTION OF SYMBOLS 1 Si chip 2 Heat compensating plate 3 Collector electrode 4 Emitter electrode 5 Teflon guide 6 Gate electrode 7 Laminated structure electrode 8a, 8b Sealing member 10 Semiconductor device 11 Mo plate 12 Mo component 13 Oxygen-free copper plate 14 Copper (Cu) component 15 Part 16, 17, 20 Carbon jig 18 Groove part 19 Hole part 21 Brazing material 51 Mo plate 52 Square plate 53 Work plate 54 Mo electrode

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 Mo層とCu層を交互に積層した積層体
であって,前記積層体は,積層方向両端が同一の厚さの
Mo層に形成され,前記積層体を構成する各層は,ろう
材を用いて接合されていることを特徴とする積層構造電
極。
1. A laminated body in which Mo layers and Cu layers are alternately laminated, wherein the laminated body has Mo layers having the same thickness at both ends in the laminating direction. An electrode having a laminated structure, which is joined by using a brazing material.
【請求項2】 請求項1記載の積層構造電極において,
前記Mo層と前記Cu層の内の少なくとも一方にNiめ
っきが施されていることを特徴とする積層構造電極。
2. The laminated electrode according to claim 1, wherein
A laminated electrode, wherein at least one of the Mo layer and the Cu layer is plated with Ni.
【請求項3】 請求項1又は2記載の積層構造電極にお
いて,前記ろう材は,Ag及びCuを含むことを特徴と
する積層構造電極。
3. The laminated electrode according to claim 1, wherein the brazing material contains Ag and Cu.
【請求項4】 請求項1乃至3の内のいずれかに記載の
積層構造電極において,少なくとも300W/m・Kの
熱伝導率を有することを特徴とする積層構造電極。
4. The laminated electrode according to claim 1, wherein the laminated electrode has a thermal conductivity of at least 300 W / m · K.
【請求項5】 Mo層とCu層の接合面の平面度を5μ
m/10mm以下にして,ろう接して交互に積層するこ
とを特徴とする積層構造電極の製造方法。
5. The flatness of the joint surface between the Mo layer and the Cu layer is 5 μm.
A method of manufacturing an electrode having a laminated structure, wherein the laminated structure is alternately laminated by brazing with a thickness of m / 10 mm or less.
JP6575397A 1997-03-19 1997-03-19 Electrode of laminated structure and manufacture therefor Withdrawn JPH10261660A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6575397A JPH10261660A (en) 1997-03-19 1997-03-19 Electrode of laminated structure and manufacture therefor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6575397A JPH10261660A (en) 1997-03-19 1997-03-19 Electrode of laminated structure and manufacture therefor

Publications (1)

Publication Number Publication Date
JPH10261660A true JPH10261660A (en) 1998-09-29

Family

ID=13296110

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6575397A Withdrawn JPH10261660A (en) 1997-03-19 1997-03-19 Electrode of laminated structure and manufacture therefor

Country Status (1)

Country Link
JP (1) JPH10261660A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007053246A (en) * 2005-08-18 2007-03-01 Toshiba Corp Heat dissipation substrate and semiconductor device using it

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007053246A (en) * 2005-08-18 2007-03-01 Toshiba Corp Heat dissipation substrate and semiconductor device using it
JP4707501B2 (en) * 2005-08-18 2011-06-22 株式会社東芝 Heat dissipation substrate and semiconductor device using the same

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