JPH10261644A - Manufacture of solder bump - Google Patents
Manufacture of solder bumpInfo
- Publication number
- JPH10261644A JPH10261644A JP9066815A JP6681597A JPH10261644A JP H10261644 A JPH10261644 A JP H10261644A JP 9066815 A JP9066815 A JP 9066815A JP 6681597 A JP6681597 A JP 6681597A JP H10261644 A JPH10261644 A JP H10261644A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- solder bump
- bump
- height
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3494—Heating methods for reflowing of solder
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、はんだバンプの製
造方法、特にはんだバンプ形成中のボイド除去の方法に
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a solder bump, and more particularly to a method for removing voids during formation of a solder bump.
【０００２】はんだバンプをチップ全面に有するＬＳＩ
等のチップにおいて、めっきにより形成されたバンプは
加熱（リフロー）によりはんだバンプの形状を球形にす
る必要がある。LSI having solder bumps on the entire surface of a chip
In such a chip, the bump formed by plating needs to make the shape of the solder bump spherical by heating (reflow).
【０００３】[0003]
【従来の技術】図６は従来例の説明図である。図におい
て、１はチップ、２ははんだバンプ、３はボイドであ
る。2. Description of the Related Art FIG. 6 is an explanatory diagram of a conventional example. In the figure, 1 is a chip, 2 is a solder bump, and 3 is a void.
【０００４】従来、図６（ａ）に平面図、図６（ｂ）に
断面図で示すように、チップ１上に複数形成されたはん
だバンプ２をリフローする場合、はんだバンプ２の形成
時にはんだバンプ２内に閉じ込められていたガスが蒸発
してボイド（空隙）３を生じて、加熱時にはんだバンプ
２の形が崩れて高さが不均一となる場合がある。Conventionally, as shown in a plan view of FIG. 6A and a sectional view of FIG. 6B, when a plurality of solder bumps 2 formed on a chip 1 are reflowed, the solder bumps 2 are formed when the solder bumps 2 are formed. The gas trapped in the bumps 2 evaporates to form voids (voids) 3, which may cause the shape of the solder bumps 2 to collapse during heating, resulting in an uneven height.
【０００５】実装基板へ実装するチップ１上のはんだバ
ンプは、全数のはんだバンプ２の高さや形状を測定し
て、特にボイド３のあるはんだバンプ２はガスの発生で
巨大化するために、はんだバンプ２の高さの基準値と比
較して高さ不良とされていた。また、その後の接続性テ
スト等で接続不良となる等、歩留りを低下させていた。For the solder bumps on the chip 1 mounted on the mounting board, the height and shape of all the solder bumps 2 are measured. It was determined that the height was defective compared to the reference value of the height of the bump 2. Further, the yield is lowered, for example, a connection failure occurs in a subsequent connectivity test or the like.
【０００６】[0006]
【発明が解決しようとする課題】実装基板へ実装するチ
ップのはんだバンプは、前述のようにチップの状態で全
はんだバンプの高さを測定し、ボイドのあるはんだバン
プは高さ不良となったり、また、接続性テストで不良と
なるため、あらかじめボイドを除去する必要があり、本
出願は以上の点に鑑みて、はんだバンプ形成時に高さ不
良のはんだバンプ内のボイドを除去することを目的とし
て提供されるものである。For the solder bumps of the chip mounted on the mounting board, the height of all the solder bumps is measured in the state of the chip as described above. In addition, it is necessary to remove voids in advance because a failure occurs in a connectivity test. In view of the above points, the present application aims to remove voids in solder bumps having a defective height when forming solder bumps. It is provided as.
【０００７】[0007]
【課題を解決するための手段】図１は本発明の原理説明
図、図２ははんだバンプの高さ測定法である。図におい
て、１はチップ、２ははんだバンプ、３はボイド、４は
レーザ光、５は反射光、６は走査ステージ、７は結像レ
ンズ、８は位置センサである。FIG. 1 is a view for explaining the principle of the present invention, and FIG. 2 is a method for measuring the height of a solder bump. In the figure, 1 is a chip, 2 is a solder bump, 3 is a void, 4 is a laser beam, 5 is a reflected beam, 6 is a scanning stage, 7 is an imaging lens, and 8 is a position sensor.
【０００８】本発明では、上記の問題を解決するため
に、図１（ａ）に断面図で示すように、チップ１上に複
数形成されたはんだバンプ２内のボイド３を除去するた
め、チップ１上のはんだバンプ２の高さを図２に示すよ
うにレーザ光４等を照射して全数測定を行う。具体的に
は図２に示すように、はんだバンプ２の頭頂部に４５度
方向からレーザ光４を照射し、はんだバンプ２の高さに
比例して変動する反射光５の位置を変動幅Ｌより計算し
てはんだバンプ２の高さを判定する。このようにして、
ボイド３を含んで基準値に比べて高さ不良となっている
はんだバンプ２を選択して、高さが基準値より高い不良
のはんだバンプ２の位置座標をマップに作製し、このマ
ップを用いて、高さ不良となっているはんだバンプ２の
頭頂部にレーザ光４を照射してはんだバンプ２のボイド
３内のガス抜き等を行ってボイド３を除去し、正常な高
さのはんだバンプ２にした後、はんだバンプ２をはんだ
が溶ける温度でリフローして、はんだバンプ２を球状に
成形する。In the present invention, in order to solve the above problem, as shown in a sectional view of FIG. 1A, a chip 3 is formed by removing a plurality of voids 3 in solder bumps 2 formed on a chip 1. The height of the solder bumps 2 on 1 is irradiated with a laser beam 4 or the like as shown in FIG. Specifically, as shown in FIG. 2, a laser beam 4 is applied to the top of the solder bump 2 from a 45 ° direction, and the position of the reflected light 5 which varies in proportion to the height of the solder bump 2 is changed by a variation width L. Then, the height of the solder bump 2 is determined. In this way,
The solder bumps 2 including the voids 3 and having a defective height compared to the reference value are selected, and the position coordinates of the defective solder bump 2 whose height is higher than the reference value are prepared in a map, and this map is used. Then, a laser beam 4 is applied to the top of the solder bump 2 having a defective height to remove gas from the void 3 in the void 3 of the solder bump 2, thereby removing the void 3. After that, the solder bump 2 is reflowed at a temperature at which the solder can be melted to form the solder bump 2 into a spherical shape.
【０００９】本発明では、ボイドを有するはんだバンプ
の頂点に集束されたレーザ光を微小スポットで照射する
ことによりはんだバンプ内のボイドの原因となるガスが
逃げる道を作ることが出来、その後のはんだバンプのリ
フローによってガス抜きが容易となり、ボイドが除去さ
れた球状のはんだバンプが形成される。According to the present invention, a laser beam focused on the apex of a solder bump having a void is irradiated in a minute spot, thereby making it possible to create a path through which a gas causing a void in the solder bump escapes. Degassing is facilitated by the reflow of the bump, and a spherical solder bump from which voids have been removed is formed.
【００１０】また、はんだバンプが融点以上に加熱さ
れ、溶融された状態でレーザ光を照射した場合にはガス
による気泡が破れる作用があり、ボイドの原因となるガ
スが容易に抜ける効果がある。Further, when the solder bumps are heated to a temperature higher than the melting point and irradiated with laser light in a molten state, the gas bubbles have the effect of breaking bubbles, and the gas causing voids is easily released.
【００１１】即ち、本発明の目的は、チップ上に形成さ
れた複数のはんだバンプの高さを全数測定する工程と、
高さが基準値より大きいはんだバンプを選択して該はん
だパンプの頭頂部にレーザ光を照射し、該はんだバンプ
内のボイドを除去する工程と、チップ上の複数のはんだ
バンプにフラックスを被覆する工程と、該はんだバンプ
を加熱して、球状に形成する工程とを含むことにより達
成される。That is, an object of the present invention is to measure the total number of heights of a plurality of solder bumps formed on a chip;
Selecting a solder bump having a height greater than a reference value and irradiating a laser beam to the top of the solder pump to remove voids in the solder bump; and coating flux on a plurality of solder bumps on the chip. This is achieved by including a step of heating the solder bump to form the solder bump into a spherical shape.
【００１２】[0012]
【発明の実施の形態】図３〜図５は本発明の一実施例の
工程順模式断面図である。図において、９はシリコン
（Ｓｉ）基板、10は二酸化シリコン（ＳｉＯ2 ）膜、11
はアルミニウム（Ａｌ）パッド、12は燐珪酸ガラス（Ｐ
ＳＧ）膜、13はポリイミド膜、14はチタン（Ｔｉ）膜、
15はニッケル（Ｎｉ）膜、16はレジスト膜、17はＮｉめ
っき膜、18ははんだめっき、19はシリンジ（注射器）、
20はフラックスである。3 to 5 are schematic cross-sectional views in the order of steps of an embodiment of the present invention. In the figure, 9 is a silicon (Si) substrate, 10 is a silicon dioxide (SiO 2 ) film, 11
Is an aluminum (Al) pad, 12 is a phosphosilicate glass (P
SG) film, 13 is a polyimide film, 14 is a titanium (Ti) film,
15 is a nickel (Ni) film, 16 is a resist film, 17 is a Ni plating film, 18 is solder plating, 19 is a syringe (syringe),
20 is a flux.
【００１３】本発明の一実施例について説明する。先
ず、図３（ａ）に示すように、二酸化シリコン（ＳｉＯ
2 ）膜10が被覆されたシリコン（Ｓｉ）基板９上に形成
されたアルミニウム（Ａｌ）パッド11領域以外をパッシ
ベーション膜としての燐珪酸ガラス（ＰＳＧ）膜12、続
いてポリイミド膜13によりＳｉ基板９全面を被覆する。An embodiment of the present invention will be described. First, as shown in FIG.
2 ) Except for the area of the aluminum (Al) pad 11 formed on the silicon (Si) substrate 9 covered with the film 10, a phosphosilicate glass (PSG) film 12 as a passivation film, Cover the entire surface.
【００１４】それからスパッタ法により、バリアメタル
としてめっき導通膜を兼ねたチタン（Ｔｉ）膜14を５，
０００Åの厚さに被覆し、その上に５，０００Åの厚さ
にニッケル（Ｎｉ）膜15を被覆する。Then, a titanium (Ti) film 14 also serving as a plating conductive film is
Then, a nickel (Ni) film 15 is coated to a thickness of 5,000 mm.
【００１５】次に、フォトリソグラフィにより図示しな
いレジスト膜をマスクとしてＮｉ膜15を選択的にエッチ
ングし、図３（ｂ）に示すように、はんだバンプ形成領
域以外のＮｉ膜15を除去する。Next, the Ni film 15 is selectively etched by photolithography using a resist film (not shown) as a mask, and the Ni film 15 other than the solder bump formation region is removed as shown in FIG.
【００１６】図３（ｃ）に示すように、再びレジスト膜
16を３０μｍの厚さに被覆し、フォトリソグラフィによ
りはんだバンプ２形成領域を開口するようにパターニン
グし、はんだ２バンプ形成領域のレジスト膜16の開口部
をスパッタで酸化物等の残滓を除去した後、Ｎｉめっき
膜17を２μｍの厚さに被覆する。As shown in FIG. 3C, the resist film is again formed.
16 is coated to a thickness of 30 μm, patterned by photolithography so as to open the solder bump 2 formation region, and the opening of the resist film 16 in the solder 2 bump formation region is removed by sputtering to remove residues such as oxides. , Ni plating film 17 is coated to a thickness of 2 μm.
【００１７】次に、図３（ｄ）に示すように、Ｔｉ膜14
を給電膜としてめっきによりはんだめっき18を５０μｍ
の厚さに行う。そして、図４（ｅ）に示すように、レジ
スト膜16を除去する。ここで形成されたはんだバンプ用
のはんだめっき18の高さを前述の方法で全数測定する。
この時にはんだめっき18内にガスが発生したりしてボイ
ド（空隙）３が出来ると一般に高さが基準値より高くな
る。Next, as shown in FIG.
50μm of solder plating 18 by plating using
To a thickness of Then, as shown in FIG. 4E, the resist film 16 is removed. The total height of the solder plating 18 for the solder bumps formed here is measured by the method described above.
At this time, if gas (gas) is generated in the solder plating 18 and voids (voids) 3 are formed, the height is generally higher than a reference value.
【００１８】高さが高いはんだめっき18の位置座標をマ
ップに作製しておき、走査ステージ６上に載置したチッ
プ１上の高さ不良のはんだバンプ２に選択的にレーザ光
４を照射してはんだを溶解し、中に包含するガスを抜い
てボイド３を消滅させ、図４（ｆ）に示すように、正常
なはんだめっき18と同じ高さに揃える。The position coordinates of the solder plating 18 having a high height are prepared in a map, and the laser beam 4 is selectively applied to the solder bump 2 having a defective height on the chip 1 mounted on the scanning stage 6. Then, the solder is melted and the gas contained therein is removed to eliminate the voids 3, and the solder 3 is adjusted to the same height as the normal solder plating 18 as shown in FIG.
【００１９】この後に、図５（ｇ）に示すように、チッ
プ１上のはんだバンプ２にシリンジ（注射器）19よりは
んだバンプ表面に出来た薄い酸化膜等を除去するために
フラックス20を適量滴下すると、図５（ｈ）に示すよう
に表面張力で全数のはんだバンプ２を覆うように、チッ
プ１全体に拡げる。続いて、加熱するとフラックス20内
の溶剤が蒸発して、図５（ｉ）に示すように、はんだバ
ンプ２全体をフラックス20が被覆した状態になる。Thereafter, as shown in FIG. 5 (g), an appropriate amount of flux 20 is dropped onto the solder bump 2 on the chip 1 by using a syringe (syringe) 19 to remove a thin oxide film or the like formed on the surface of the solder bump. Then, as shown in FIG. 5H, the entire surface of the chip 1 is spread so as to cover all the solder bumps 2 by surface tension. Subsequently, when heated, the solvent in the flux 20 evaporates, and the flux 20 covers the entire solder bump 2 as shown in FIG. 5 (i).
【００２０】ここで、はんだバンプ２に用いたはんだの
融点１８０℃より高い温度で、且つはんだが溶解する温
度、すなわち、はんだが鉛（Ｐｂ）−錫（Ｓｎ）（９５
％−５％）の場合には３５５℃で２０分間加熱した後、
冷却すると表面張力で球状に溶解していたはんだめっき
18が冷却して、図４（ｊ）に示すように、高さ、形状が
均一な球状のはんだバンプ２が形成出来る。Here, the melting point of the solder used for the solder bump 2 is higher than 180 ° C. and the temperature at which the solder melts, that is, the solder is made of lead (Pb) -tin (Sn) (95).
% -5%), after heating at 355 ° C. for 20 minutes,
Solder plating that melted spherically due to surface tension when cooled
As shown in FIG. 4 (j), the spherical solder bump 2 having a uniform height and shape can be formed.
【００２１】尚、チップ１内の高さが基準値より高い不
良はんだバンプ２へのレーザ光４の照射工程は、チップ
へのフラックス塗布工程、或いはチップ加熱による球状
のはんだバンプ形成後に行うことも可能である。The step of applying the laser beam 4 to the defective solder bump 2 whose height inside the chip 1 is higher than the reference value may be performed after a step of applying a flux to the chip or after forming a spherical solder bump by heating the chip. It is possible.
【００２２】[0022]
【発明の効果】以上説明したように、はんだバンプの高
さを全数測定し、ボイドを含んで基準値より高さの高い
はんだバンプのみ、選択的にその頭頂部にレーザ光を照
射してガス抜き等によりボイドを除去すると、全数が均
一なはんだバンプになる。As described above, the total number of the solder bumps is measured, and only the solder bumps having a height higher than the reference value, including voids, are selectively irradiated with the laser beam to the top of the solder bumps to obtain gas. When voids are removed by punching or the like, all the solder bumps become uniform.
【００２３】これにより、はんだバンプを有するチップ
を実装基板に接着する際、はんだバンプの高さが均一な
ため、一部はんだバンプの接着不良等の問題が解消さ
れ、実装基板の信頼性の向上に寄与するところが大き
い。Accordingly, when the chip having the solder bumps is bonded to the mounting board, since the height of the solder bumps is uniform, problems such as poor bonding of the solder bumps are partially solved, and the reliability of the mounting board is improved. It greatly contributes to
【図１】 本発明の原理説明図FIG. 1 is a diagram illustrating the principle of the present invention.
【図２】 はんだバンプの高さ測定法Fig. 2 Method for measuring solder bump height
【図３】 本発明の一実施例の工程順模式断面図（その
１）FIG. 3 is a schematic cross-sectional view of an embodiment of the present invention in the order of steps (part 1).
【図４】 本発明の一実施例の工程順模式断面図（その
２）FIG. 4 is a schematic cross-sectional view of an embodiment of the present invention in the order of steps (part 2).
【図５】 本発明の一実施例の工程順模式断面図（その
３）FIG. 5 is a schematic sectional view of a process in an embodiment of the present invention (part 3).
【図６】 従来例の説明図FIG. 6 is an explanatory view of a conventional example.
図において １ チップ ２ はんだバンプ ３ ボイド ４ レーザ光 ５ 反射光 ６ 走査ステージ ７ 結像レンズ ８ 位置センサ ９ Ｓｉ基板 10 ＳｉＯ2 膜 11 Ａｌパッド 12 ＰＳＧ膜 13 ポリイミド膜 14 Ｔｉ膜 15 Ｎｉ膜 16 レジスト膜 17 Ｎｉめっき膜 18 はんだめっき 19 シリンジ 20 フラックスIn the figure, 1 chip 2 solder bump 3 void 4 laser light 5 reflected light 6 scanning stage 7 imaging lens 8 position sensor 9 Si substrate 10 SiO 2 film 11 Al pad 12 PSG film 13 polyimide film 14 Ti film 15 Ni film 16 resist film 17 Ni plating film 18 Solder plating 19 Syringe 20 Flux
Claims (3)
プの高さを測定する工程と、高さが基準値より大きいは
んだバンプを選択して該はんだパンプの頭頂部にレーザ
光を照射し、該はんだバンプ内のボイドに貫通孔を開け
る工程と、該はんだバンプを加熱して球状に形成する工
程とを含むことを特徴とするはんだパンプの製造方法。A step of measuring a height of a plurality of solder bumps formed on a chip, selecting a solder bump having a height larger than a reference value, and irradiating a laser beam to a top of the solder pump; A method of manufacturing a solder pump, comprising: a step of forming a through hole in a void in the solder bump; and a step of heating the solder bump to form a spherical shape.
だパンプの頭頂部にレーザ光を照射し、反射光をセンサ
で受光して行うことを特徴とする請求項１記載のはんだ
パンプの製造方法。2. The manufacturing of the solder pump according to claim 1, wherein the measurement of the height of the solder bump is performed by irradiating a laser beam to the top of the solder pump and receiving reflected light by a sensor. Method.
プの融点を超える温度で、且つはんだバンプが完全に溶
解しない範囲の温度で行うことを特徴とする請求項１記
載のはんだバンプの製造方法。3. The method according to claim 1, wherein the heating of the solder bump is performed at a temperature exceeding the melting point of the solder bump and at a temperature within a range in which the solder bump is not completely melted.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9066815A JPH10261644A (en) | 1997-03-19 | 1997-03-19 | Manufacture of solder bump |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9066815A JPH10261644A (en) | 1997-03-19 | 1997-03-19 | Manufacture of solder bump |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH10261644A true JPH10261644A (en) | 1998-09-29 |
Family
ID=13326741
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9066815A Withdrawn JPH10261644A (en) | 1997-03-19 | 1997-03-19 | Manufacture of solder bump |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH10261644A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005109496A (en) * | 2003-09-29 | 2005-04-21 | Phoenix Precision Technology Corp | Semiconductor package substrate for forming pre-solder structure, the semiconductor package substrate in which pre-solder structure is formed, and the manufacturing methods |
| JP2007317957A (en) * | 2006-05-26 | 2007-12-06 | Sony Corp | Solder ball, semiconductor device, and method of manufacturing solder ball |
| JP2009514228A (en) * | 2005-10-25 | 2009-04-02 | フリースケール セミコンダクター インコーポレイテッド | Method for forming solder contacts on a mounting substrate |
-
1997
- 1997-03-19 JP JP9066815A patent/JPH10261644A/en not_active Withdrawn
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005109496A (en) * | 2003-09-29 | 2005-04-21 | Phoenix Precision Technology Corp | Semiconductor package substrate for forming pre-solder structure, the semiconductor package substrate in which pre-solder structure is formed, and the manufacturing methods |
| JP4660643B2 (en) * | 2003-09-29 | 2011-03-30 | 欣興電子股▲分▼有限公司 | Semiconductor package substrate for forming pre-solder structure, semiconductor package substrate on which pre-solder structure is formed, and manufacturing method thereof |
| JP2009514228A (en) * | 2005-10-25 | 2009-04-02 | フリースケール セミコンダクター インコーポレイテッド | Method for forming solder contacts on a mounting substrate |
| JP2007317957A (en) * | 2006-05-26 | 2007-12-06 | Sony Corp | Solder ball, semiconductor device, and method of manufacturing solder ball |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 20040601 |