JPH10256083A - Chip type composite electronic device - Google Patents
Chip type composite electronic deviceInfo
- Publication number
- JPH10256083A JPH10256083A JP9057791A JP5779197A JPH10256083A JP H10256083 A JPH10256083 A JP H10256083A JP 9057791 A JP9057791 A JP 9057791A JP 5779197 A JP5779197 A JP 5779197A JP H10256083 A JPH10256083 A JP H10256083A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- capacitance
- chip substrate
- resistor
- type composite
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000002131 composite material Substances 0.000 title claims description 23
- 239000000758 substrate Substances 0.000 claims abstract description 57
- 239000011521 glass Substances 0.000 claims abstract description 40
- 239000011248 coating agent Substances 0.000 claims abstract description 14
- 238000000576 coating method Methods 0.000 claims abstract description 14
- 239000010409 thin film Substances 0.000 claims abstract description 11
- 239000010408 film Substances 0.000 claims description 32
- 238000010304 firing Methods 0.000 claims description 6
- 239000003990 capacitor Substances 0.000 abstract description 37
- 239000004020 conductor Substances 0.000 abstract description 14
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 abstract description 2
- 230000001681 protective effect Effects 0.000 description 14
- 238000010586 diagram Methods 0.000 description 12
- 230000012447 hatching Effects 0.000 description 10
- 230000003071 parasitic effect Effects 0.000 description 6
- 238000007650 screen-printing Methods 0.000 description 5
- 238000009966 trimming Methods 0.000 description 5
- 238000001035 drying Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 229920003002 synthetic resin Polymers 0.000 description 1
- 239000000057 synthetic resin Substances 0.000 description 1
Landscapes
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、チップ型複合電子
部品に関する。The present invention relates to a chip-type composite electronic component.
【0002】[0002]
【従来の技術】従来、デジタル信号を伝達する回路又は
ラインの終端部(以下終端部という)がオープンである
か、又は、ハイインピーダンスの入力部に接続されてい
る場合、同終端部を抵抗体とコンデンサとを介し電源又
はグランドに接続し、同終端部で発生する反射による信
号波形の乱れを抑制して誤動作を防止している。2. Description of the Related Art Conventionally, when a terminal (hereinafter referred to as a terminal) of a circuit or a line for transmitting a digital signal is open or connected to a high impedance input part, the terminal is connected to a resistor. The capacitor is connected to the power supply or the ground via the capacitor, and the signal waveform is prevented from being disturbed due to reflection occurring at the same terminating end, thereby preventing malfunction.
【0003】[0003]
【発明が解決しようとする課題】ところが、上記終端部
に抵抗体やコンデンサを接続する場合、抵抗体やコンデ
ンサを個別に形成したチップを接続するため多大の手間
を要してコストがかさみ、更に、同終端部の外形が大き
くなって実装密度が低下するという問題があった。However, when a resistor or a capacitor is connected to the above-mentioned terminal portion, connecting a chip in which the resistor or the capacitor is individually formed requires a great deal of trouble and increases the cost. However, there has been a problem that the outer shape of the terminal portion becomes large and the mounting density decreases.
【0004】また、上記抵抗部とコンデンサとを、単一
のチップ基板上に重層して配置することも考えられる
が、この場合には、抵抗部に大きな寄生容量が発生し、
しかも、この寄生容量のバラツキを小さくするのが困難
であるため、均一な製品を製造するのが困難である。In addition, it is conceivable that the resistor and the capacitor are arranged in layers on a single chip substrate. In this case, however, a large parasitic capacitance is generated in the resistor.
In addition, it is difficult to reduce the variation in the parasitic capacitance, so that it is difficult to manufacture a uniform product.
【0005】[0005]
【課題を解決するための手段】そこで、本発明では、単
一のチップ基板上に、抵抗部と容量部とを電極方向にほ
ぼ直交する並設状態に形成したことを特徴とするチップ
型複合電子部品を提供せんとするものである。Therefore, according to the present invention, a chip type composite is characterized in that a resistance portion and a capacitance portion are formed on a single chip substrate in a juxtaposed state substantially orthogonal to the electrode direction. Electronic components will not be provided.
【0006】また、次のような特徴を併せ有するもので
ある。Further, the present invention has the following features.
【0007】上記抵抗部と容量部とを、上記チップ基板
上で並列接続したこと。The resistance part and the capacitance part are connected in parallel on the chip substrate.
【0008】上記抵抗部を、チップ基板上に形成したト
リミング可能の薄膜状抵抗体で構成すると共に、上記容
量部は、チップ基板上で、一方の極板、高誘電性ガラス
被膜、他方の極板の順に重層していること。The resistor portion is formed of a trimmable thin-film resistor formed on a chip substrate, and the capacitor portion is formed on the chip substrate by one of an electrode plate, a high dielectric glass film, and the other electrode. Layered in the order of the boards.
【0009】上記高誘電性ガラス被膜は、高誘電性ガラ
ス被膜形成用ペーストのスクリーン印刷、乾燥定着、焼
成による高誘電性ガラス被膜形成の工程を2回繰返して
形成したこと。The high dielectric glass film is formed by repeating twice the steps of screen printing, drying and fixing, and firing the paste for forming the high dielectric glass film twice.
【0010】容量部の両方の極板をそれぞれ長方形に形
成し、各極板の長手方向を直交させて配置したこと チップ基板上に直列接続した抵抗部と容量部とを複数配
設し、少なくとも上記抵抗部又は容量部のいずれかを、
チップ基板上で併設していること。[0010] Both electrode plates of the capacitance unit are formed in a rectangular shape, and the longitudinal direction of each electrode plate is orthogonally arranged. A plurality of resistance units and capacitance units connected in series on the chip substrate are provided. Either the resistor or the capacitor,
Being installed on the chip substrate.
【0011】[0011]
【発明の実施の形態】本発明では、小型化のために、終
端部で発生する反射を減衰させるための抵抗部と容量部
とを、単一のチップ基板上に並設状態に形成する。DESCRIPTION OF THE PREFERRED EMBODIMENTS In the present invention, for miniaturization, a resistor portion and a capacitor portion for attenuating reflection generated at a terminal portion are formed side by side on a single chip substrate.
【0012】なお、上記抵抗部と容量部とを、単一のチ
ップ基板上に重層して配置することも考えられるが、こ
の場合には、抵抗部に大きな寄生容量が発生し、しか
も、この寄生容量の個体差が大きいため、均一な製品を
製造するのが困難になる。Incidentally, it is conceivable to dispose the resistor section and the capacitor section in a layered manner on a single chip substrate. In this case, however, a large parasitic capacitance occurs in the resistor section. The large individual difference of the parasitic capacitance makes it difficult to manufacture a uniform product.
【0013】また、終端部への接続作業を簡易化するた
めに、上記容量部と抵抗部とを上記基板上で並列接続す
る。Further, in order to simplify the work of connecting to the terminating portion, the capacitance portion and the resistance portion are connected in parallel on the substrate.
【0014】また、抵抗部の抵抗値を規定の値に調整す
るために、抵抗部をトリミング可能の薄膜状抵抗体で形
成する。Further, in order to adjust the resistance value of the resistance portion to a specified value, the resistance portion is formed of a thin film resistor that can be trimmed.
【0015】十分な容量を有する容量部を形成するため
に、チップ基板上に、一方の導体、高誘電性ガラス被
膜、他方の導体の順に重層して、各極板の対向面積を大
きくする。In order to form a capacitance portion having a sufficient capacitance, one conductor, a high-dielectric glass coating, and the other conductor are sequentially laminated on the chip substrate to increase the facing area of each electrode plate.
【0016】高誘電性ガラス被膜にピンホールが発生し
て極板間の短絡が発生するのを防止するために、高誘電
性ガラス被膜形成用ペーストのスクリーン印刷、乾燥定
着、焼成という高誘電性ガラス被膜形成の工程を2回繰
り返す。In order to prevent the occurrence of pinholes in the high dielectric glass film and the occurrence of a short circuit between the electrode plates, the high dielectric glass film forming paste is screen-printed, dried and fixed, and fired. The process of forming a glass film is repeated twice.
【0017】各極板の正確な対向面積を得るために、両
方の極板をそれぞれ長方形に形成し、各極板の長手方向
を直交させて配置して、各極板の位置ずれによる対向面
積の変化を最小にする。In order to obtain an accurate opposing area of each electrode plate, both electrode plates are formed in a rectangular shape, and the longitudinal direction of each electrode plate is arranged orthogonally. Minimize the change in
【0018】[0018]
【実施例】本発明の実施例について図面を参照して説明
する。Embodiments of the present invention will be described with reference to the drawings.
【0019】図1は、本発明に係る第1実施例のチップ
型複合電子部品A1、図2はその等価回路を示しており、
同チップ型複合電子部品A1は、アルミナセラミックスを
素材としたチップ基板11の上面に、容量部12と抵抗部13
とを形成し、これらをチップ基板11上において、電極方
向にほぼ直交する並列状態に配置し、その後、これらを
並列接続した後、外部に接続するための端面電極14,14
に接続している。FIG. 1 shows a chip-type composite electronic component A1 according to a first embodiment of the present invention, and FIG. 2 shows an equivalent circuit thereof.
The chip-type composite electronic component A1 has a capacitance section 12 and a resistance section 13 on an upper surface of a chip substrate 11 made of alumina ceramics.
And these are arranged on the chip substrate 11 in a side-by-side state substantially orthogonal to the electrode direction. After that, these are connected in parallel and then the end face electrodes 14 and 14 for external connection are formed.
Connected to
【0020】次に、図3〜図12を参照して、本発明の
チップ型複合電子部品A1の製造工程及び構造について説
明する。なお、上記チップ型複合電子部品A1の製造に際
し、量産性を高めるために、多数の縦横ブレーク溝15,1
6 を形成した集合基板17の上面にできるだけ多くの工程
を施工し、しかる後、集合基板17を上記縦横ブレーク溝
15,16 に沿って多数のチップ基板11に分割するようにし
ている。Next, the manufacturing process and structure of the chip-type composite electronic component A1 of the present invention will be described with reference to FIGS. When manufacturing the chip-type composite electronic component A1, a large number of vertical and horizontal break grooves 15, 1
6 as many steps as possible on the upper surface of the aggregate substrate 17 on which the aggregate substrate 17 has been formed.
The substrate is divided into a number of chip substrates 11 along the lines 15 and 16.
【0021】まず、図3のハッチングで示すように、集
合基板17上面に、導体形成用ペーストを横ブレーク溝16
を跨いだ状態にスクリーン印刷して乾燥定着させた後、
焼成により上下導体18,19 を形成する。特に、上導体18
の一端部を下方に上下方向に伸延した直方形状に延出さ
せて、容量部12の一方の極板20として形成する。First, as shown by hatching in FIG.
After screen printing and fixing by drying over the
The upper and lower conductors 18, 19 are formed by firing. In particular, the upper conductor 18
Is formed as one of the electrode plates 20 of the capacitance portion 12 by extending one end of the capacitor portion 12 into a rectangular shape extending downward and vertically.
【0022】次に、図4のハッチングで示すように、上
記一方の極板20の上面に高誘電性ガラス被膜形成用ペー
ストをスクリーン印刷して乾燥定着させた後、焼成によ
り高誘電性ガラス被膜22を形成し、更に、上記高誘電性
ガラス被膜22の上面に、再度高誘電性ガラス被膜形成用
ペーストをスクリーン印刷して乾燥定着させた後、焼成
により高誘電性ガラス被膜22を形成するという工程を繰
り返して、高誘電性ガラス被膜22にピンホールが発生す
るのを防止すると共に、高誘電性ガラス被膜22の厚さの
均一化をはかっている。Next, as shown by the hatching in FIG. 4, a paste for forming a high dielectric glass film is screen-printed on the upper surface of the one electrode plate 20 and dried and fixed. After forming the high dielectric glass coating 22, the high dielectric glass coating forming paste is screen printed again and dried and fixed, and then the high dielectric glass coating 22 is formed by firing. The process is repeated to prevent the occurrence of pinholes in the high dielectric glass coating 22, and to make the thickness of the high dielectric glass coating 22 uniform.
【0023】次に、図5のハッチングで示すように、高
誘電性ガラス被膜22とした導体19とにとに跨がって、導
体形成用ペーストを略L字形状にスクリーン印刷し、乾
燥定着、焼成して、前記高誘電性ガラス被膜22の上面
に、容量部12の他方の極板21を左右方向に伸延した直方
形状に形成する。Next, as shown by hatching in FIG. 5, a paste for forming a conductor is screen-printed in a substantially L-shape over the conductor 19 having the high dielectric glass coating 22 and dried and fixed. Then, the other electrode plate 21 of the capacitance portion 12 is formed on the upper surface of the high dielectric glass film 22 in a rectangular shape extending in the left-right direction.
【0024】このように、上記他方の極板21が、上記略
L字形状の一部として左右方向に伸延した直方形状であ
り、前記一方の極板20が上下方向に伸延した直方形状で
あるから、両方の極板20,21 の長手方向が、高誘電性ガ
ラス被膜22を挟んで互いに直交することになり、両極板
20,21 の対向面積の均一化をはかることができ、前記高
誘電性ガラス被膜22の厚さの均一化と相俟って、容量部
12容量の個体差を小さくすることができる。As described above, the other electrode plate 21 has a rectangular shape extending in the left-right direction as a part of the substantially L-shape, and the one electrode plate 20 has a rectangular shape extending in the vertical direction. As a result, the longitudinal directions of the two electrode plates 20 and 21 are orthogonal to each other with the high dielectric glass film 22 interposed therebetween.
20 and 21 can be made uniform, and together with the uniformity of the thickness of the high dielectric glass coating 22, the capacitance
Individual differences of 12 volumes can be reduced.
【0025】次に、図6のハッチングで示すように、上
記他方の極板21の上面に保護ガラス被膜形成用ペースト
をスクリーン印刷して乾燥定着させた後、焼成により第
1保護ガラス被膜23を形成して容量部12とする。Next, as shown by hatching in FIG. 6, a paste for forming a protective glass film is screen-printed on the upper surface of the other electrode plate 21 and dried and fixed, and then the first protective glass film 23 is fired. The capacitor 12 is formed.
【0026】次に、図7のハッチングで示すように、薄
膜状抵抗体形成用ペーストをスクリーン印刷して乾燥定
着させた後、焼成により薄膜状抵抗体24を形成する。Next, as shown by hatching in FIG. 7, a paste for forming a thin film resistor is screen-printed, dried and fixed, and then fired to form a thin film resistor 24.
【0027】次に、図8のハッチングで示すように、レ
ーザートリミングにより、薄膜状抵抗体24の抵抗値を規
定の値に調整して抵抗部13を形成する。図中、25はトリ
ミングによって生じた略L字形状のトリミング溝であ
る。Next, as shown by hatching in FIG. 8, the resistance of the thin-film resistor 24 is adjusted to a specified value by laser trimming to form the resistor portion 13. In the drawing, reference numeral 25 denotes a substantially L-shaped trimming groove formed by trimming.
【0028】次に、図9のハッチングで示すように、上
記抵抗部13と容量部12との上面に保護ガラス被膜形成用
ペーストをスクリーン印刷して乾燥定着させた後、焼成
により第2保護ガラス被膜26を形成する。Next, as shown by the hatching in FIG. 9, a paste for forming a protective glass film is screen-printed on the upper surfaces of the resistor portion 13 and the capacitor portion 12 and dried and fixed. A coating 26 is formed.
【0029】次に、図10のハッチングで示すように、
前記チップ基板11の横ブレーク溝16に接する部分を除く
上面全面に、最外層保護被膜27を形成する。この最外層
保護被膜27は、前記同様に保護ガラス被膜形成用ペース
トをスクリーン印刷して乾燥定着させた後、焼成により
保護ガラス被膜を形成するか、又は、合成樹脂ポリマー
をスクリーン印刷して、同ポリマーの硬化により樹脂性
の最外層保護被膜を形成しても良い。Next, as shown by hatching in FIG.
An outermost protective film 27 is formed on the entire upper surface of the chip substrate 11 except for the portion in contact with the lateral break grooves 16. The outermost protective film 27 is formed by screen-printing a paste for forming a protective glass film and drying and fixing the paste in the same manner as described above, and then forming a protective glass film by baking or screen-printing a synthetic resin polymer. A resinous outermost protective film may be formed by curing the polymer.
【0030】次に、集合基板17を横ブレーク溝16に沿っ
て分割してバー状の集合基板17を形成する。Next, the collective substrate 17 is divided along the lateral break grooves 16 to form a bar-shaped collective substrate 17.
【0031】次に、図11のハッチングで示すように、
バー状の集合基板17の分割面及び同分割面近傍の集合基
板17の上下面に、導体形成用ペーストをスクリーン印刷
して乾燥定着させた後、焼成により端面電極14,14 を形
成する。Next, as shown by hatching in FIG.
After the conductor forming paste is screen-printed and dried and fixed on the divided surface of the bar-shaped aggregate substrate 17 and the upper and lower surfaces of the aggregate substrate 17 in the vicinity of the divided surface, the end surface electrodes 14 and 14 are formed by firing.
【0032】次に、バー状の集合基板17を縦ブレーク溝
15に沿ってチップ状に分割する。Next, the bar-shaped collective substrate 17 is inserted into the vertical break grooves.
Divide into chips along 15
【0033】次に、図12のハッチングで示すように、
上記端面電極14,14 の表面に外部電極28,28 としてのニ
ッケルハンダメッキを形成して、抵抗部13と容量部12と
が、単一のチップ基板11上に並列接続したチップ型複合
電子部品A1を完成させる。Next, as shown by hatching in FIG.
A chip type composite electronic component in which a resistance portion 13 and a capacitance portion 12 are connected in parallel on a single chip substrate 11 by forming nickel solder plating as external electrodes 28, 28 on the surfaces of the end surface electrodes 14, 14. Complete A1.
【0034】図13は、第2実施例のチップ型複合電子
部品A2、図14はその等価回路を示しており、同チップ
型複合電子部品A2は、前記第1実施例と略同様に、チッ
プ基板31の上面に、容量部12と抵抗部13とを形成し、こ
れらの両端部を、容量部端面電極14c,14c と、抵抗部端
面電極14r,14r とに個別に接続している。FIG. 13 shows a chip type composite electronic component A2 according to the second embodiment, and FIG. 14 shows an equivalent circuit thereof. The capacitance section 12 and the resistance section 13 are formed on the upper surface of the substrate 31, and both ends thereof are individually connected to the capacitance section end face electrodes 14c, 14c and the resistance section end face electrodes 14r, 14r.
【0035】また、このチップ型複合電子部品A2に用い
られる集合基板37には、横ブレーク溝16上に略矩形状の
短絡防止孔32を形成して、上記容量部端面電極14c,14c
と抵抗部端面電極14r,14r との表面に、それぞれ容量部
外部電極28c,28c と抵抗部端面電極28r,28r とをメッキ
によって形成する際、これらがブリッジ等によって短絡
するのを防止している。In the collective substrate 37 used for the chip-type composite electronic component A2, a substantially rectangular short-circuit preventing hole 32 is formed on the lateral break groove 16 so as to form the capacitor end face electrodes 14c, 14c.
When the capacitor external electrodes 28c, 28c and the resistive end electrodes 28r, 28r are formed by plating on the surfaces of the resistive end electrodes 14r, 14r, respectively, they are prevented from being short-circuited by a bridge or the like. .
【0036】そして、図15〜図24で示すように、前
記第1実施例と略同様の工程をへてチップ型複合電子部
品A2を完成させるのであるが、第2実施例のチップ型複
合電子部品A2は、容量部12と抵抗部13とを、それぞれ前
記短絡防止孔32を挟んで配置した容量部端面電極14,14
と抵抗部端面電極14,14 とに、上下導体18c,18r,19c,19
r を介して個別的に接続しており、容量部12と抵抗部13
とが、チップ基板31上で接続していない点で第1実施例
とは異なる。Then, as shown in FIGS. 15 to 24, the chip-type composite electronic component A2 is completed through substantially the same steps as in the first embodiment, but the chip-type composite electronic component of the second embodiment is completed. The component A2 has capacitance portion end face electrodes 14, 14 in which the capacitance portion 12 and the resistance portion 13 are disposed with the short-circuit prevention hole 32 interposed therebetween.
And upper and lower conductors 18c, 18r, 19c, 19
r are connected individually, and the capacitance section 12 and the resistance section 13
Are different from the first embodiment in that they are not connected on the chip substrate 31.
【0037】次に、チップ基板11上に直列接続した抵抗
部13と容量部12とを複数配設し、少なくとも上記抵抗部
13又は容量部12のいずれかをチップ基板11上で併設状態
としたものを図25〜図32で示す。Next, a plurality of resistance portions 13 and capacitance portions 12 connected in series on the chip substrate 11 are provided.
FIGS. 25 to 32 show a state in which either the capacitor 13 or the capacitor 12 is provided on the chip substrate 11.
【0038】図25では、それぞれ抵抗部13と容量部12
を直列接続した二つの回路を、互いに独立してチップ基
板11上に配設しており、抵抗部13及び容量部12同志が併
設状態になっている。In FIG. 25, the resistance portion 13 and the capacitance portion 12 are respectively shown.
Are connected on the chip substrate 11 independently of each other, and the resistance section 13 and the capacitance section 12 are provided side by side.
【0039】図26では、それぞれ抵抗部13と容量部12
を直列接続した二つの回路を、回路の両端で並列接続し
てチップ基板11上に配設しており、抵抗部13及び容量部
12同志が併設されている。In FIG. 26, the resistance portion 13 and the capacitance portion 12 are respectively shown.
Are connected in parallel at both ends of the circuit, and are arranged on the chip substrate 11, and the resistor 13 and the capacitor
There are 12 comrades.
【0040】図27では、直列接続した二組の抵抗部13
と容量部12とを、互いに逆順序でチップ基板上に配設
し、各抵抗部13を終端で接続してテブナン終端用として
いる。図28では、直列接続した抵抗部13と容量部12
と、同抵抗部13に併設した容量部12とを接続して、抵抗
部13と容量部12とを併設状態にしており、ディスクドラ
イブ等のインターフェースなどに使用する。In FIG. 27, two sets of resistance units 13 connected in series
And the capacitor unit 12 are arranged on the chip substrate in the reverse order to each other, and the respective resistor units 13 are connected at the terminating ends for the Thevenin terminating. In FIG. 28, a resistor 13 and a capacitor 12 connected in series are connected.
Is connected to the capacitance section 12 attached to the resistance section 13, so that the resistance section 13 and the capacitance section 12 are connected to each other, and used for an interface of a disk drive or the like.
【0041】図29では、一個の抵抗部13に並列接続し
た2個の容量部12を接続しており、上記に個の容量部を
併設状態にしている。In FIG. 29, two capacitance sections 12 connected in parallel to one resistance section 13 are connected, and the above-mentioned capacitance sections are provided side by side.
【0042】上記の他に、図30〜図32に示す接続例
がある。In addition to the above, there are connection examples shown in FIGS.
【0043】[0043]
【発明の効果】本発明によれば次のような効果を得るこ
とができる。According to the present invention, the following effects can be obtained.
【0044】請求項1記載の発明では、単一のチップ基
板上に、抵抗部と容量部とを並設状態に形成したことに
よって、終端部に発生する反射を減衰させるための抵抗
部と容量部とを小さくまとめることができて、実装密度
を大きくすることができ、更に、抵抗部と容量部との間
に発生する寄生容量を最小限に抑制して、終端処理の信
頼性を向上することができる。According to the first aspect of the present invention, since the resistor and the capacitor are formed in parallel on a single chip substrate, the resistor and the capacitor for attenuating the reflection generated at the terminal end are formed. Parts can be reduced, the mounting density can be increased, and the parasitic capacitance generated between the resistance part and the capacitance part can be minimized to improve the reliability of the termination processing. be able to.
【0045】請求項2記載の発明では、上記抵抗部と容
量部とを、上記チップ基板上で並列接続したことによっ
て、終端部や入力部との接続作業を簡易化して、省力化
をはかることができる。According to the second aspect of the present invention, the resistance section and the capacitance section are connected in parallel on the chip substrate, thereby simplifying the connection work with the termination section and the input section, thereby saving power. Can be.
【0046】請求項3記載の発明では、上記抵抗部を、
チップ基板上に形成したトリミング可能の薄膜状抵抗体
で構成すると共に、上記容量部は、チップ基板上で、一
方の導体、高誘電性ガラス被膜、他方の導体の順に重層
していることによって、抵抗部の抵抗値を規定の値に調
整することができて抵抗値の個体差が小さい製品を製造
できると共に、容量部の両極板の対向面積を大きくし
て、反射を減衰させるのに十分な容量を有する容量部を
形成することができる。According to the third aspect of the present invention, the resistance portion is
Along with being composed of a trimmable thin-film resistor formed on a chip substrate, the capacitor portion is formed on the chip substrate by laminating one conductor, a high dielectric glass coating, and the other conductor in this order, The resistance value of the resistance part can be adjusted to a specified value, and a product with small individual difference in resistance value can be manufactured.In addition, the opposing area of both plates of the capacitance part is increased, and it is enough to attenuate reflection. A capacitor portion having a capacitor can be formed.
【0047】請求項4記載の発明では、上記高誘電性ガ
ラス被膜は、高誘電性ガラス被膜形成用ペーストのスク
リーン印刷、乾燥定着、焼成による高誘電性ガラス被膜
形成の工程を2回繰返して形成したことによって、高誘
電性ガラス被膜に生ずるピンホールによる両極板間の短
絡を防止して製品の信頼性を高めると共に、必要な厚さ
の高誘電性ガラス被膜を形成でき、更に、同高誘電性ガ
ラス被膜厚さの個体差を減少させて、個体差の小さい容
量部を形成することができる。According to the fourth aspect of the present invention, the step of forming the high dielectric glass film by screen printing, drying and fixing, and firing the paste for forming the high dielectric glass film is repeated twice. As a result, it is possible to prevent short-circuiting between the two electrode plates due to pinholes generated in the high-dielectric glass film and improve the reliability of the product, and to form a high-dielectric glass film of a required thickness. It is possible to reduce the individual difference in the film thickness of the conductive glass, and to form a capacitance portion having a small individual difference.
【0048】請求項5記載の発明では、両方の極板をそ
れぞれ長方形に形成し、各極板の長手方向を直交させて
配置したことによって、各極板の相対位置にずれが発生
しても、各極板の対向面積の変化を最小に抑制して、正
確な容量の容量部を形成することができる。According to the fifth aspect of the present invention, since both the electrode plates are formed in a rectangular shape and the longitudinal directions of the respective electrode plates are arranged orthogonal to each other, even if the relative positions of the respective electrode plates are displaced from each other. In addition, it is possible to minimize the change in the opposing area of each electrode plate, and to form a capacitance part with an accurate capacitance.
【0049】請求項6記載の発明では、チップ基板上に
直列接続した抵抗部と容量部とを複数配設し、少なくと
も上記抵抗部又は容量部のいずれかを、チップ基板上で
併設していることによって、チップ基板上に抵抗部と容
量部とが混在した回路において、抵抗部と容量部との間
に発生する寄生容量を最小限に抑制することができる。According to the sixth aspect of the present invention, a plurality of resistor portions and capacitor portions connected in series on the chip substrate are provided, and at least one of the resistor portion and the capacitor portion is provided on the chip substrate. Thus, in a circuit in which a resistor section and a capacitor section are mixed on a chip substrate, it is possible to minimize the parasitic capacitance generated between the resistor section and the capacitor section.
【図1】本発明第1実施例のチップ型複合電子部品の斜
視図である。FIG. 1 is a perspective view of a chip-type composite electronic component according to a first embodiment of the present invention.
【図2】同チップ型複合電子部品の等価回路図である。FIG. 2 is an equivalent circuit diagram of the chip-type composite electronic component.
【図3】同上下導体及び一方の極板形成工程を示す説明
図である。FIG. 3 is an explanatory view showing a step of forming the upper and lower conductors and one electrode plate.
【図4】同高誘電性ガラス被膜形成工程を示す説明図で
ある。FIG. 4 is an explanatory view showing a step of forming the high dielectric glass film.
【図5】同他方の極板形成工程を示す説明図である。FIG. 5 is an explanatory view showing the other electrode plate forming step.
【図6】同第1保護ガラス被膜形成工程を示す説明図で
ある。FIG. 6 is an explanatory view showing a first protective glass film forming step.
【図7】同薄膜状抵抗体形成工程を示す説明図である。FIG. 7 is an explanatory view showing the same thin-film resistor forming step.
【図8】同トリミング工程を示す説明図である。FIG. 8 is an explanatory view showing the trimming step.
【図9】同第2保護ガラス被膜形成工程を示す説明図で
ある。FIG. 9 is an explanatory view showing a second protective glass film forming step.
【図10】同最外層保護被膜形成工程を示す説明図であ
る。FIG. 10 is an explanatory view showing the outermost protective film forming step.
【図11】同端面電極形成工程を示す説明図である。FIG. 11 is an explanatory view showing the same end face electrode forming step.
【図12】同外部電極形成工程を示す説明図である。FIG. 12 is an explanatory view showing the external electrode forming step.
【図13】本発明第2実施例のチップ型複合電子部品の
斜視図である。FIG. 13 is a perspective view of a chip-type composite electronic component according to a second embodiment of the present invention.
【図14】同チップ型複合電子部品の等価回路図であ
る。FIG. 14 is an equivalent circuit diagram of the chip-type composite electronic component.
【図15】同上下導体及び一方の極板形成工程を示す説
明図である。FIG. 15 is an explanatory diagram showing a step of forming the upper and lower conductors and one electrode plate.
【図16】同高誘電性ガラス被膜形成工程を示す説明図
である。FIG. 16 is an explanatory view showing the same high dielectric glass film forming step.
【図17】同他方の極板形成工程を示す説明図である。FIG. 17 is an explanatory view showing the other electrode plate forming step.
【図18】同第1保護ガラス被膜形成工程を示す説明図
である。FIG. 18 is an explanatory view showing a first protective glass film forming step.
【図19】同薄膜状抵抗体形成工程を示す説明図であ
る。FIG. 19 is an explanatory view showing the same thin film resistor forming step.
【図20】同トリミング工程を示す説明図である。FIG. 20 is an explanatory view showing the same trimming step.
【図21】同第2保護ガラス被膜形成工程を示す説明図
である。FIG. 21 is an explanatory view showing a second protective glass film forming step.
【図22】同最外層保護被膜形成工程を示す説明図であ
る。FIG. 22 is an explanatory view showing the outermost protective film forming step.
【図23】同端面電極形成工程を示す説明図である。FIG. 23 is an explanatory view showing the same end face electrode forming step.
【図24】同外部電極形成工程を示す説明図である。FIG. 24 is an explanatory diagram showing the external electrode forming step.
【図25】チップ基板上における抵抗部と容量部との他
の接続例を示す説明図である。FIG. 25 is an explanatory diagram showing another example of connection between a resistance part and a capacitance part on a chip substrate.
【図26】チップ基板上における抵抗部と容量部との他
の接続例を示す説明図である。FIG. 26 is an explanatory diagram showing another example of connection between a resistor section and a capacitor section on a chip substrate.
【図27】チップ基板上における抵抗部と容量部との他
の接続例を示す説明図である。FIG. 27 is an explanatory diagram showing another example of connection between a resistor section and a capacitor section on a chip substrate.
【図28】チップ基板上における抵抗部と容量部との他
の接続例を示す説明図である。FIG. 28 is an explanatory diagram showing another example of connection between a resistor section and a capacitor section on a chip substrate.
【図29】チップ基板上における抵抗部と容量部との他
の接続例を示す説明図である。FIG. 29 is an explanatory diagram showing another example of connection between a resistor section and a capacitor section on a chip substrate.
【図30】チップ基板上における抵抗部と容量部との他
の接続例を示す説明図である。FIG. 30 is an explanatory diagram showing another example of connection between a resistor section and a capacitor section on a chip substrate.
【図31】チップ基板上における抵抗部と容量部との他
の接続例を示す説明図である。FIG. 31 is an explanatory diagram showing another example of connection between a resistor section and a capacitor section on a chip substrate.
【図32】チップ基板上における抵抗部と容量部との他
の接続例を示す説明図である。FIG. 32 is an explanatory diagram showing another example of connection between a resistor section and a capacitor section on a chip substrate.
A1 チップ型複合電子部品 11 チップ基板 12 容量部 13 抵抗部 20 一方の極板 21 他方の極板 22 高誘電性ガラス被膜 24 薄膜状抵抗体 A1 Chip-type composite electronic component 11 Chip substrate 12 Capacitance part 13 Resistance part 20 One electrode plate 21 The other electrode plate 22 High dielectric glass coating 24 Thin film resistor
Claims (6)
とを電極方向にほぼ直交する並設状態に形成したことを
特徴とするチップ型複合電子部品。1. A chip-type composite electronic component wherein a resistance portion and a capacitance portion are formed on a single chip substrate in a state of being juxtaposed substantially orthogonal to an electrode direction.
板上で並列接続したことを特徴とする請求項1記載のチ
ップ型複合電子部品。2. The chip-type composite electronic component according to claim 1, wherein said resistance part and said capacitance part are connected in parallel on said chip substrate.
トリミング可能の薄膜状抵抗体で構成すると共に、上記
容量部は、チップ基板上で、一方の極板、高誘電性ガラ
ス被膜、他方の極板の順に重層していることを特徴とす
る請求項1又は2記載のチップ型複合電子部品。3. The resistance part is formed of a trimmable thin film resistor formed on a chip substrate, and the capacitance part is formed on the chip substrate by one of an electrode plate, a high dielectric glass film, and the other. The chip-type composite electronic component according to claim 1, wherein the components are stacked in the order of the electrode plates.
ラス被膜形成用ペーストのスクリーン印刷、乾燥定着、
焼成による高誘電性ガラス被膜形成の工程を2回繰返し
て形成したことを特徴とする請求項3記載のチップ型複
合電子部品。4. The high dielectric glass coating is screen-printed, dried and fixed with a paste for forming a high dielectric glass coating.
4. The chip-type composite electronic component according to claim 3, wherein the step of forming a high dielectric glass film by firing is repeated twice.
形成し、各極板の長手方向を直交させて配置したことを
特徴とする請求項3記載のチップ型複合電子部品。5. The chip-type composite electronic component according to claim 3, wherein both electrode plates of the capacitance unit are each formed in a rectangular shape, and the electrode plates are arranged with their longitudinal directions orthogonal to each other.
量部とを複数配設し、少なくとも上記抵抗部又は容量部
のいずれかを、チップ基板上で併設していることを特徴
とするチップ型複合電子部品。6. A chip comprising: a plurality of resistance parts and a plurality of capacitance parts connected in series on a chip substrate; and at least one of the resistance part and the capacitance part is provided side by side on the chip substrate. Type composite electronic components.
Priority Applications (1)
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JP05779197A JP3833769B2 (en) | 1997-03-12 | 1997-03-12 | Chip-type composite electronic components |
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JP05779197A JP3833769B2 (en) | 1997-03-12 | 1997-03-12 | Chip-type composite electronic components |
Publications (2)
Publication Number | Publication Date |
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JPH10256083A true JPH10256083A (en) | 1998-09-25 |
JP3833769B2 JP3833769B2 (en) | 2006-10-18 |
Family
ID=13065723
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001015309A (en) * | 1999-06-28 | 2001-01-19 | Kooa T & T Kk | Composite electronic component |
WO2014069363A1 (en) * | 2012-11-02 | 2014-05-08 | ローム株式会社 | Chip condenser, circuit assembly, and electronic device |
JP2023015397A (en) * | 2015-04-20 | 2023-01-31 | キョーセラ・エイブイエックス・コンポーネンツ・コーポレーション | Wire-bond transmission line rc circuit |
-
1997
- 1997-03-12 JP JP05779197A patent/JP3833769B2/en not_active Expired - Fee Related
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001015309A (en) * | 1999-06-28 | 2001-01-19 | Kooa T & T Kk | Composite electronic component |
WO2014069363A1 (en) * | 2012-11-02 | 2014-05-08 | ローム株式会社 | Chip condenser, circuit assembly, and electronic device |
US9288908B2 (en) | 2012-11-02 | 2016-03-15 | Rohm Co., Ltd. | Chip capacitor, circuit assembly, and electronic device |
JPWO2014069363A1 (en) * | 2012-11-02 | 2016-09-08 | ローム株式会社 | Chip capacitors, circuit assemblies, and electronics |
US9685273B2 (en) | 2012-11-02 | 2017-06-20 | Rohm Co., Ltd. | Chip capacitor, circuit assembly, and electronic device |
US10026557B2 (en) | 2012-11-02 | 2018-07-17 | Rohm Co., Ltd. | Chip capacitor, circuit assembly, and electronic device |
US10593480B2 (en) | 2012-11-02 | 2020-03-17 | Rohm Co., Ltd. | Chip capacitor, circuit assembly, and electronic device |
JP2023015397A (en) * | 2015-04-20 | 2023-01-31 | キョーセラ・エイブイエックス・コンポーネンツ・コーポレーション | Wire-bond transmission line rc circuit |
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