JPH10247629A - Manufacture of semiconductor wafer, semiconductor wafer and solar cell using the semiconductor wafer - Google Patents

Manufacture of semiconductor wafer, semiconductor wafer and solar cell using the semiconductor wafer

Info

Publication number
JPH10247629A
JPH10247629A JP9067283A JP6728397A JPH10247629A JP H10247629 A JPH10247629 A JP H10247629A JP 9067283 A JP9067283 A JP 9067283A JP 6728397 A JP6728397 A JP 6728397A JP H10247629 A JPH10247629 A JP H10247629A
Authority
JP
Japan
Prior art keywords
silicon
semiconductor wafer
wafer
ingot
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9067283A
Other languages
Japanese (ja)
Inventor
Shigeaki Nakamura
茂昭 中村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
M SETETSUKU KK
Setetsuku Kk M
Original Assignee
M SETETSUKU KK
Setetsuku Kk M
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by M SETETSUKU KK, Setetsuku Kk M filed Critical M SETETSUKU KK
Priority to JP9067283A priority Critical patent/JPH10247629A/en
Publication of JPH10247629A publication Critical patent/JPH10247629A/en
Pending legal-status Critical Current

Links

Classifications

    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy
    • Y02E10/546Polycrystalline silicon PV cells

Abstract

PROBLEM TO BE SOLVED: To dispense with the removal process of impurity diffused layer side surface for a P-N junction isolation in the manufacturing method of a semiconductor wafer by a method wherein an insulating film is formed on the surface of a semiconductor ingot or the surface of a semiconductor block, which is obtained by cut-processing this ingot, and after that, the ingot or the block is cut into the wafer. SOLUTION: A CZ method pulling P-type single crystal silicon ingot is processed by cutting into a silicon block having a prescribed dimension. After that, a surface damaged layer generated by the cutting is etched away using the so-called mixed acid solvent, such as a hydrofluoric acid, a nitric acid and an acetic acid, then, the silicon block is cleaned in pure water and is dried. After that, a silicon nitride film 2 of a thickness of 0.1μm is formed on the surface of a P-type silicon block 1 using an LPCVD device. As the condition for the formation at this time, an SiH2 Cl2 gas and an NH3 gas, for example, are used and a temperature of 800 deg.C is set. A P-type silicon block 3 formed with the film 2 is cut using a wire-saw cutting device.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、半導体ウエハの製造方
法及び半導体ウエハ並びにこの半導体ウエハを用いた太
陽電池に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor wafer, a semiconductor wafer, and a solar cell using the semiconductor wafer.

【0002】[0002]

【従来の技術】シリコン結晶系太陽電池を製造する場
合、通常、単結晶又は多結晶のP型シリコンウエハが基
板として用いられ、該基板にN型不純物拡散層を設けて
PN接合を形成して用いられる。
2. Description of the Related Art In manufacturing a silicon crystal solar cell, a single crystal or polycrystalline P-type silicon wafer is usually used as a substrate, and an N-type impurity diffusion layer is provided on the substrate to form a PN junction. Used.

【0003】上記製造工程において、P型シリコンウエ
ハ(w)の表面側にN型不純物を拡散してPN接合(j)を形
成する時に、ウエハ表面への拡散と同時にウエハの側面
及び場合により裏面側にも拡散してこれらにN型拡散層
(n)が形成されてしまう(図5参照)。このため、表面
側及び裏面側にそれぞれ電極をパターン形成し、太陽電
池として作動させる際、ウエハの側周面での拡散層によ
り表面側と裏面側の電極間がショート又はリーク状態に
なり、太陽電池として満足な動作が得られない。
In the above manufacturing process, when the PN junction (j) is formed by diffusing an N-type impurity into the front side of the P-type silicon wafer (w), the side surface and, if necessary, the back surface of the wafer are simultaneously diffused to the wafer surface. N-type diffusion layer
(n) is formed (see FIG. 5). For this reason, when electrodes are formed on the front side and the back side, respectively, and when operated as a solar cell, a short circuit or a leak state occurs between the electrodes on the front side and the back side due to the diffusion layer on the side peripheral surface of the wafer. Satisfactory operation as a battery cannot be obtained.

【0004】従って、不純物拡散層又は電極パターン形
成後にウエハの側面側又は側面付近での拡散層を切断除
去(C)して接合分離する工程が必要であった(図6参
照)。かかる接合分離方法には機械的研削を用いる方法、
化学薬品やプラズマを用いたエッチング方法、レーザー
加工法や超音波加工法による除去方法等が適用されてい
るが、除去工程の困難さ、均一性、再現性等の問題や、
除去後の接合特性の問題等、解決すべき問題点が多く残
されている。
Therefore, a step of cutting and removing (C) the diffusion layer on or near the side surface of the wafer after the formation of the impurity diffusion layer or the electrode pattern and joining and separation is required (see FIG. 6). Such joining separation method uses a mechanical grinding,
Etching methods using chemicals or plasma, removal methods by laser processing method or ultrasonic processing method, etc. are applied, but problems such as difficulty of removal process, uniformity, reproducibility, etc.,
There are many problems to be solved, such as the problem of bonding characteristics after removal.

【0005】[0005]

【発明が解決しようとする課題】本発明は、従来のよう
なPN接合分離の為の側面不純物拡散層除去工程を必要
としない半導体ウエハの製造方法及び半導体ウエハ並び
にこの半導体ウエハを用いた太陽電池を提供するにあ
る。
SUMMARY OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor wafer, which does not require a step of removing a lateral impurity diffusion layer for separating a PN junction as in the prior art, a semiconductor wafer, and a solar cell using the semiconductor wafer. To provide.

【0006】[0006]

【課題を解決するための手段】かくして本願『請求項
1』にかかる発明によれば、『半導体インゴット又は該
インゴットを切削加工して得られる半導体ブロック(1)
の表面に絶縁膜(2)を形成し、その後ウエハに切断する
ことを特徴とする半導体ウエハの製造方法』が提供され
る。また、本願『請求項4』にかかる発明によれば、
『側周面に絶縁膜(2)が形成されてなる半導体ウエハ
(4)』が提供される。
According to the invention of claim 1 of the present application, there is provided a semiconductor ingot or a semiconductor block (1) obtained by cutting the ingot.
Forming an insulating film (2) on the surface of the semiconductor wafer and then cutting the wafer into wafers ". According to the invention of claim 4 of the present application,
`` Semiconductor wafer with insulating film (2) formed on side peripheral surface
(4)] is provided.

【0007】本発明の製造方法に用いられる半導体イン
ゴットは、本願『請求項2』に示すように『シリコン結
晶系』が好ましい。上記シリコン結晶系としては、単結
晶シリコン又は多結晶シリコンのいずれであってもよ
い。通常、これらのシリコン結晶系はP型又はN型に構
成されて用いられる。
The semiconductor ingot used in the manufacturing method of the present invention is preferably a "silicon crystal type" as described in claim 2 of the present application. The silicon crystal system may be either single crystal silicon or polycrystalline silicon. Usually, these silicon crystal systems are configured and used as P-type or N-type.

【0008】本発明において、絶縁膜形成の対象は、半
導体インゴットであってもよく、またこのインゴットか
ら所定の寸法に切削加工された半導体ブロックであって
もよく、さらに、いわゆるオリエンテーションフラット
が形成されたブロックであってもよい。要するに、ウエ
ハに切断する前段のものであればいずれのものであって
もよい。
In the present invention, the object for forming the insulating film may be a semiconductor ingot, or a semiconductor block cut from the ingot to a predetermined size. Blocks. In short, any material may be used as long as it is in the stage before cutting into wafers.

【0009】上記半導体インゴット又はブロックとして
は、とくに太陽電池作製用の観点からシリコン結晶系が
好ましく、CZ法により得られる単結晶シリコンインゴ
ット、FZ法による単結晶シリコンインゴット、多結晶
シリコンインゴット等が挙げられる。
The above-mentioned semiconductor ingot or block is preferably a silicon crystal system particularly from the viewpoint of solar cell production, and includes a single crystal silicon ingot obtained by the CZ method, a single crystal silicon ingot by the FZ method, and a polycrystalline silicon ingot. Can be

【0010】本発明において絶縁膜(2)は、膜厚が0.05
〜5μmの範囲が適する。0.05μmよりも薄いと不純物
拡散時に拡散マスクとしての機能が不十分であり、また
5μmよりも厚い場合は膜にクラック等が入り欠陥が生
じ易くなって不都合となる。また絶縁膜の種類として
は、半導体インゴットにシリコン結晶系を選択した場
合、窒化シリコン膜、酸窒化シリコン膜、酸化シリコン
膜、シリコン熱酸化膜等が好ましいものとして挙げられ
る。上記窒化シリコン膜の場合は0.1〜0.3μmが、また
シリコン熱酸化膜の場合は0.2〜1μmが、それぞれ、
絶縁膜に要求される作用を満たしかつ形成コストを考慮
した上で最適である。
In the present invention, the insulating film (2) has a thickness of 0.05
A range of 55 μm is suitable. When the thickness is less than 0.05 μm, the function as a diffusion mask at the time of impurity diffusion is insufficient, and when the thickness is more than 5 μm, cracks and the like are liable to be formed in the film, which is disadvantageous. Further, as a type of the insulating film, when a silicon crystal system is selected as the semiconductor ingot, a silicon nitride film, a silicon oxynitride film, a silicon oxide film, a silicon thermal oxide film, and the like are preferable. The thickness of the silicon nitride film is 0.1 to 0.3 μm, and the thickness of the silicon thermal oxide film is 0.2 to 1 μm.
It is optimal in that it satisfies the function required for the insulating film and takes into consideration the formation cost.

【0011】本発明はまた、上記本発明の半導体ウエハ
において、当該分野で公知の手段により、不純物拡散層
を形成してPN接合を設けると共に該ウエハの表裏面に
それぞれ所望の電極形成を行うことにより、太陽電池と
して提供することができる。
According to the present invention, there is provided a semiconductor wafer according to the present invention, wherein an impurity diffusion layer is formed to provide a PN junction and a desired electrode is formed on each of the front and back surfaces of the wafer by means known in the art. Thereby, it can be provided as a solar cell.

【0012】本発明において、インゴット又はブロック
からウエハへの切断には、ワイヤソー切断法による他、
内周刃切断法、レーザによる切断法、放電加工による切
断法等、当該分野で公知の方法をそのまま使用すること
ができる。
In the present invention, the ingot or block is cut into wafers by a wire saw cutting method,
A method known in the art, such as an inner peripheral blade cutting method, a cutting method using a laser, or a cutting method using electric discharge machining, can be used as it is.

【0013】なお、本発明の半導体ウエハは、太陽電池
以外に、ウエハ全面を利用するダイオードデバイス、ト
ランジスタデバイス等にも十分適用できるものである。
The semiconductor wafer of the present invention can be sufficiently applied to a diode device, a transistor device, and the like using the whole surface of the wafer, in addition to the solar cell.

【0014】[0014]

【作用】本発明によれば、ウエハに切断する前段の半導
体インゴット又は半導体ブロック(1)の表面に絶縁膜(2)
が形成されているので、切断した際得られるウエハ(4)
の側周面に絶縁膜(2)が残り、これがウエハ(4)に不純物
拡散層を形成する際にマスクとして機能し、ウエハ(4)
の表裏面間でPN接合が分離されるので、接合分割する
工程が不要となる。また絶縁膜(2)はウエハへの切断時
及び太陽電池その他半導体デバイスへの処理工程時の機
械的保護膜としても機能することとなる。
According to the present invention, an insulating film (2) is formed on the surface of a semiconductor ingot or a semiconductor block (1) at a stage prior to cutting into a wafer.
Is formed, so the wafer obtained when cutting (4)
The insulating film (2) remains on the side peripheral surface of the wafer (4), which functions as a mask when forming an impurity diffusion layer on the wafer (4), and the wafer (4)
Since the PN junction is separated between the front and rear surfaces, the step of dividing the junction becomes unnecessary. In addition, the insulating film (2) also functions as a mechanical protective film at the time of cutting into a wafer and at the time of processing a solar cell and other semiconductor devices.

【0015】[0015]

【実施例】以下、本発明を図示実施例に従って詳述する
が、本発明はこれらに限定されるものではない。 実施例1 図1は本発明におけるP型シリコンブロックの一例の断
面図、図2は図1のP型シリコンブロックから切断され
たP型シリコンウエハの一例の断面図(イ)及び平面図
(ロ)、図3は図2のP型シリコンウエハにN型不純物
拡散層(PN接合)を形成したときの断面図である。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the illustrated embodiments, but the present invention is not limited thereto. Example 1 FIG. 1 is a cross-sectional view of an example of a P-type silicon block according to the present invention, and FIG. 2 is a cross-sectional view (a) and a plan view of an example of a P-type silicon wafer cut from the P-type silicon block of FIG. FIG. 3 is a cross-sectional view when an N-type impurity diffusion layer (PN junction) is formed on the P-type silicon wafer of FIG.

【0016】まず、CZ法引き上げP型単結晶シリコン
インゴットを所定の寸法を有するシリコンブロックに切
削加工した後、切削により生じた表面損傷層をフッ酸、
硝酸、酢酸等のいわゆる混酸液を用いてエッチング除去
し、次いで純水中で洗浄し乾燥させる。その後、上記P
型シリコンブロック(1)の表面上にLPCVD装置を用
いて厚さ0.1μmのシリコン窒化膜(2)を形成する(図1
参照)。このときの形成条件としては例えば、SiH2
l2及びNH3ガスを用い、温度 800℃が挙げられる。
First, a P-type single crystal silicon ingot pulled up by the CZ method is cut into a silicon block having a predetermined size, and the surface damaged layer generated by the cutting is treated with hydrofluoric acid.
It is removed by etching using a so-called mixed acid solution such as nitric acid and acetic acid, and then washed and dried in pure water. Then, the above P
A silicon nitride film (2) having a thickness of 0.1 μm is formed on the surface of the mold type silicon block (1) using an LPCVD apparatus (FIG. 1).
reference). The formation conditions at this time include, for example, SiH 2 C
The temperature is 800 ° C. using l 2 and NH 3 gas.

【0017】上記のようにシリコン窒化膜(2)が形成さ
れたP型シリコンブロック(3)をワイヤソー切断装置を
用いて切断し、図2に示すP型シリコンウエハ(4)を得
た。得られたP型シリコンウエハ(4)は、同図に示すよ
うに、ウエハ周囲の側面上に0.1μmのシリコン窒化膜
(2)を有している。
The P-type silicon block (3) on which the silicon nitride film (2) was formed as described above was cut using a wire saw cutting device to obtain a P-type silicon wafer (4) shown in FIG. The resulting P-type silicon wafer (4) has a 0.1 μm silicon nitride film on the side surface around the wafer as shown in FIG.
(2).

【0018】上記P型シリコンウエハ(4)を基板として
太陽電池(図4参照)を製造する工程は、公知の工程に
よる。すなわち、ウエハ表面の加工層を除去するための
濃いNaOH溶液によるエッチング、表面に凹凸を形成
する(いわゆるテクスチャ状態とする)ための薄いNa
OH溶液によるエッチング、N型不純物拡散によるN型
拡散層(5)の形成(PN接合(6)の形成)、表面及び裏面
側の電極(7)形成を行う工程からなる。
The process of manufacturing a solar cell (see FIG. 4) using the P-type silicon wafer (4) as a substrate is a known process. That is, etching with a concentrated NaOH solution for removing a processing layer on the wafer surface, and thin Na for forming irregularities on the surface (so-called textured state).
It consists of steps of etching with an OH solution, forming an N-type diffusion layer (5) by N-type impurity diffusion (forming a PN junction (6)), and forming electrodes (7) on the front and back surfaces.

【0019】上記の工程において、N型不純物を拡散し
てPN接合(6)を形成する場合、図3に示すように、ウ
エハ(4)の側周面に予めシリコン窒化膜(2)が形成されて
いるので、この窒化膜(2)がN型不純物が拡散するとき
はマスクとして機能し、これが必然的にウエハの表裏間
を分割してこの間の導通を絶縁することとなる。従っ
て、これまではPN接合形成後にウエハ周辺部でPN接
合を分離するための加工工程が必要であったが、本例で
はPN接合分離工程が不必要となる。
In the above process, when the PN junction (6) is formed by diffusing the N-type impurity, as shown in FIG. Therefore, when the N-type impurity diffuses, the nitride film (2) functions as a mask, which inevitably divides the front and back surfaces of the wafer and insulates the conduction therebetween. Therefore, a processing step for separating the PN junction at the peripheral portion of the wafer after the formation of the PN junction has conventionally been required. However, in the present embodiment, the PN junction separation step is unnecessary.

【0020】なお、上記実施例において、シリコンブロ
ック表面上に設ける絶縁膜はLPCVD法による窒化シ
リコン膜としたが、NaOH溶液によるエッチング工程
に耐えかつ不純物拡散時に拡散マスクとして機能し得る
他の種類の材質の薄膜例えば他のCVD法(PECV
D、ATCVD等)による窒化シリコン膜、酸窒化シリ
コン膜、シリコン酸化膜及びシリコン熱酸化膜等も可能
である。
In the above embodiment, the insulating film provided on the surface of the silicon block is a silicon nitride film formed by the LPCVD method. However, other types of insulating films that can withstand the etching process using a NaOH solution and can function as a diffusion mask during impurity diffusion. Thin film of material such as another CVD method (PECV
D, ATCVD, etc.), a silicon nitride film, a silicon oxynitride film, a silicon oxide film, a silicon thermal oxide film, and the like are also possible.

【0021】[0021]

【発明の効果】本発明によれば、PN接合形成時には絶
縁膜がマスクとして機能するので、拡散後のPN接合分
離のための工程が不必要となる。また、シリコンインゴ
ットやシリコンブロックからウエハを切断する時にも、
ウエハの側周面部の機械的保護膜としても作用し、ウエ
ハ側周面部の欠け、チッピング及びクラック等の発生を
防ぐことができる。さらに、ウエハ切断後のあらゆる処
理工程においてもウエハ側周面部の欠け、チッピング及
びクラック等の発生をも効果的に防ぐことができる。
According to the present invention, the insulating film functions as a mask during the formation of the PN junction, so that a step for separating the PN junction after diffusion is not required. Also, when cutting a wafer from a silicon ingot or silicon block,
It also acts as a mechanical protective film on the side peripheral surface of the wafer, and can prevent the occurrence of chipping, cracking, and the like on the peripheral surface of the wafer. Further, chipping, chipping, cracks, and the like of the peripheral surface on the wafer side can be effectively prevented in all processing steps after the wafer is cut.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明におけるP型シリコンブロックの一例の
断面図
FIG. 1 is a sectional view of an example of a P-type silicon block according to the present invention.

【図2】(イ)…図1のP型シリコンブロックから切断
されたP型シリコンウエハの一例の断面図 (ロ)…図1のP型シリコンブロックから切断されたP
型シリコンウエハの一例の平面図
2A is a cross-sectional view of an example of a P-type silicon wafer cut from the P-type silicon block in FIG. 1;
Plan view of an example of a silicon wafer

【図3】図2のP型シリコンウエハにN型不純物拡散層
(PN接合)を形成したときの断面図
3 is a sectional view when an N-type impurity diffusion layer (PN junction) is formed on the P-type silicon wafer of FIG. 2;

【図4】本発明のP型シリコンウエハの一例を用いた太
陽電池の断面概略図
FIG. 4 is a schematic cross-sectional view of a solar cell using an example of a P-type silicon wafer of the present invention.

【図5】従来例のPN接合を形成したウエハの断面図FIG. 5 is a cross-sectional view of a wafer in which a PN junction of a conventional example is formed.

【図6】従来例におけるPN接合分離工程を説明する概
略図
FIG. 6 is a schematic diagram illustrating a PN junction separation step in a conventional example.

【符号の説明】[Explanation of symbols]

(1)…P型シリコンブロック (2)…シリコン窒化膜 (3)…シリコン窒化膜が形成されたP型シリコンブロッ
ク (4)…本発明の一例のP型シリコンウエハ (5)…N型拡散層 (6)…PN接合 (7)…電極
(1) P-type silicon block (2) Silicon nitride film (3) P-type silicon block with silicon nitride film formed (4) P-type silicon wafer as an example of the present invention (5) N-type diffusion Layer (6)… PN junction (7)… Electrode

Claims (7)

【特許請求の範囲】[Claims] 【請求項1】 半導体インゴット又は該インゴッ
トを切削加工して得られる半導体ブロックの表面に絶縁
膜を形成し、その後ウエハに切断することを特徴とする
半導体ウエハの製造方法。
1. A method of manufacturing a semiconductor wafer, comprising: forming an insulating film on a surface of a semiconductor ingot or a semiconductor block obtained by cutting the ingot, and thereafter cutting the wafer into wafers.
【請求項2】 半導体インゴット又はブロックが
シリコン結晶系のものからなり、絶縁膜が窒化シリコン
膜、酸窒化シリコン膜、酸化シリコン膜、シリコン熱酸
化膜から選択される1つである請求項1記載の半導体ウ
エハの製造方法。
2. The semiconductor ingot or block is made of a silicon crystal, and the insulating film is one selected from a silicon nitride film, a silicon oxynitride film, a silicon oxide film, and a silicon thermal oxide film. Semiconductor wafer manufacturing method.
【請求項3】 シリコン結晶系が、単結晶シリコ
ン又は多結晶シリコンである請求項2記載の半導体ウエ
ハの製造方法。
3. The method for manufacturing a semiconductor wafer according to claim 2, wherein the silicon crystal system is single crystal silicon or polycrystalline silicon.
【請求項4】 側周面に絶縁膜が形成されてなる
半導体ウエハ。
4. A semiconductor wafer having an insulating film formed on a side peripheral surface.
【請求項5】 シリコン結晶系からなり、絶縁膜
が窒化シリコン膜、酸窒化シリコン膜、酸化シリコン
膜、シリコン熱酸化膜から選択される1つである請求項
4記載の半導体ウエハ。
5. The semiconductor wafer according to claim 4, comprising a silicon crystal system, wherein the insulating film is one selected from a silicon nitride film, a silicon oxynitride film, a silicon oxide film, and a silicon thermal oxide film.
【請求項6】 シリコン結晶系が、単結晶シリコ
ン又は多結晶シリコンである請求項5記載の半導体ウエ
ハ。
6. The semiconductor wafer according to claim 5, wherein the silicon crystal system is single crystal silicon or polycrystalline silicon.
【請求項7】 請求項4〜6のいずれかに記載の
半導体ウエハの所定面にPN接合が形成され、かつ該ウ
エハの表裏各面に電極が形成されてなる太陽電池。
7. A solar cell, wherein a PN junction is formed on a predetermined surface of the semiconductor wafer according to any one of claims 4 to 6, and electrodes are formed on each of the front and back surfaces of the wafer.
JP9067283A 1997-03-04 1997-03-04 Manufacture of semiconductor wafer, semiconductor wafer and solar cell using the semiconductor wafer Pending JPH10247629A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9067283A JPH10247629A (en) 1997-03-04 1997-03-04 Manufacture of semiconductor wafer, semiconductor wafer and solar cell using the semiconductor wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9067283A JPH10247629A (en) 1997-03-04 1997-03-04 Manufacture of semiconductor wafer, semiconductor wafer and solar cell using the semiconductor wafer

Publications (1)

Publication Number Publication Date
JPH10247629A true JPH10247629A (en) 1998-09-14

Family

ID=13340504

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9067283A Pending JPH10247629A (en) 1997-03-04 1997-03-04 Manufacture of semiconductor wafer, semiconductor wafer and solar cell using the semiconductor wafer

Country Status (1)

Country Link
JP (1) JPH10247629A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7307210B2 (en) 2001-06-13 2007-12-11 Sharp Kabushiki Kaisha Solar cell and method of producing the same
JP2008255143A (en) * 2007-03-31 2008-10-23 Kagawa Univ Silicon fine particles, method for producing the same, solar cell by using the same, and method for producing solar cell
US8592676B2 (en) 2007-06-22 2013-11-26 Empire Technology Development Llc Solar cell and method for manufacturing the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7307210B2 (en) 2001-06-13 2007-12-11 Sharp Kabushiki Kaisha Solar cell and method of producing the same
JP2008255143A (en) * 2007-03-31 2008-10-23 Kagawa Univ Silicon fine particles, method for producing the same, solar cell by using the same, and method for producing solar cell
US8592676B2 (en) 2007-06-22 2013-11-26 Empire Technology Development Llc Solar cell and method for manufacturing the same

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