JPH10242886A - Amplifier circuit and transmitter/receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the reception sensitivity from deteriorating and to reduce the power consumption by increasing the bias potential or current of an amplifier means only when the reception sensitivity deteriorates owing to inter- modulation distortion. SOLUTION: In a receiving and amplifier circuit part 31 provided as the initial stage of a receiving circuit block, a control circuit 33 analyzes a transmission level signal S23 and a reception power level S31 to generate and output a control signal S32 of logical level H when the transmission power level is large and the reception power level is small or a logical level L in other cases to a receiving and amplifier circuit 32. An amplifier 57 inputs a high gate bias potential when the control signal S32 is H and a low gate bias potential when L to the gate of an FET Q11 by a variable gate bias input circuit 64. Consequently, the drain current of the FET Q11 of the amplifier 57 is increased only when the transmission power level is large and the reception power level is small to improve the linearity of the amplifier 57, thereby reducing inter- modulation distortion.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[Table of Contents] The present invention will be described in the following order.

BACKGROUND OF THE INVENTION Prior Art (FIGS. 8 and 9) Problems to be Solved by the Invention Means for Solving the Problems Embodiments of the Invention (1) First Embodiment (FIGS. 1 to 6) (2) Second embodiment (FIG. 7) (3) Other embodiments Advantages of the invention

[0003]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an amplifier circuit and a transmission / reception device, and is suitably applied to, for example, a portable telephone.

[0004]

2. Description of the Related Art Conventionally, in a transmitting / receiving apparatus such as a portable telephone, when transmission and reception are performed simultaneously, intermodulation distortion may occur. The principle of generation of this intermodulation distortion will be described with reference to FIG. First, in the mobile phone 1, the transmission signal S1 amplified by the transmission amplifier circuit 2 is supplied to the antenna 4 via the duplexer 3, and the antenna 4 radiates a radio wave corresponding to the transmission signal S1 into space. You. On the other hand, the reception signal S2 received by the antenna 4 is input to the reception amplification circuit 5 through the duplexer 3, and is amplified by the reception amplification circuit 5, and then is demodulated in the subsequent stage (not shown). Zu).

Here, the duplexer 3 is a circuit for separating the transmission signal S1 and the reception signal S2. However, since the transmission power is much larger than the reception power, the duplexer 3 is not completely separated. The transmission signal S1 may leak into the receiving system. When the transmission signal leaked into the reception system and the reception signal of the interference wave received by the antenna 4 are input to the reception amplification circuit 5, the intermodulation distortion is caused by the nonlinearity of the reception amplification circuit 5. Occurs. If the intermodulation distortion is equal to the frequency of the received signal of the desired signal, it becomes an interference wave and degrades the signal-to-noise ratio (so-called S / N ratio), thus lowering the reception sensitivity of the mobile phone 1. .

As a method of reducing such cross-modulation distortion, a method of improving the degree of separation of the duplexer 3 or improving the linearity of the receiving amplifier circuit 5 is considered.
When these methods are employed, the size of the transistor is increased or the current consumption is increased, so that the power consumption is increased.

[0007] By the way, in order to be able to use a mobile phone driven by a battery for a long time, it is necessary to reduce the power consumption of the mobile phone. Since the above-described reception amplification circuit 5 is activated even during standby, the reception amplification circuit 5
If the power consumption can be reduced, it is considered that the power consumption of the entire mobile phone 1 can be reduced. Therefore, it is desired that the power consumption of the receiving amplifier circuit 5 be reduced as much as possible even when the intermodulation distortion is prevented.

As a means for realizing this, a receiving amplifier circuit that adaptively switches the linearity can be considered. That is,
Since the intermodulation distortion occurs only at the time of transmission, the intermodulation distortion does not occur during non-transmission such as during standby. Therefore, a reception amplifier circuit that switches to high linearity only during transmission and switches to low linearity during non-transmission is considered.

Here, a specific configuration of such a reception amplifier circuit 10 will be described with reference to FIG. The receiving amplifier circuit 10 is roughly formed by an input matching circuit 11, an amplifier 12, and an output matching circuit 13, and includes a receiving signal S1.
1 is supplied to an amplifier 12 via an input matching circuit 11, the received signal S 11 is amplified by the amplifier 12, and a high-frequency signal S 12 as an output thereof is output via an output matching circuit 13. .

First, the amplifier 12 is connected to the input matching circuit 11 via a DC cut-off capacitor C1 for blocking direct current, and receives the received signal S11 via a field effect transistor (hereinafter referred to as an FE) via the DC cut-off capacitor C1.
(Referred to as T). Incidentally, the input matching circuit 11 is an impedance matching circuit, and matches the output impedance of the input matching circuit 11 with the input impedance of the amplifier 12.

A variable gate bias potential input circuit 14 is connected to the gate of the FET Q1. In the variable gate bias potential input circuit 14, resistors R1, R2 and R
3 is connected between the power supply V _CC and the ground line GND, generates a gate bias potential Vg1 from the midpoint of the connection between the resistors R1 and R2, and generates the gate bias potential Vg1 and the resistors R2 and R3.
The gate bias potential Vg2 is generated from the connection middle point. A first input terminal of the gate bias potential switching switch SW1 is connected to a connection point between the resistors R1 and R2, and a second input terminal of the gate bias potential switching switch SW1 is connected to a connection point between the resistors R2 and R3. Is connected.

Gate bias potential switching switch SW1
Is configured to switch the connection state based on a control signal S13 sent from a predetermined control circuit (not shown). That is, at the time of transmission, the connection state is switched to the first input terminal side to select the gate bias potential Vg1,
At the time of non-transmission, the connection state is switched to the second input terminal side to select the gate bias potential Vg2. The output terminal of the gate bias potential switching switch SW1 is connected to the gate of the FET Q1 via a yoke inductor L1 for blocking high frequencies, and the power supply V _CC.
Is connected to the ground line GND via a bypass capacitor C2 for preventing voltage fluctuation of the power supply.

Thus, by the variable gate bias potential input circuit 14, the gate bias potential switching switch SW1 can be switched to the first input terminal side during transmission to input the high gate bias potential Vg1 to the gate of the FET Q1. At the time of transmission, the gate bias potential switching switch SW1 is switched to the second input terminal side, so that the low gate bias potential Vg2 can be input to the gate of the FET Q1.

The source of the FET Q1 is connected to the ground line GND via a matching inductor L2 for blocking high frequencies, and the drain of the FET Q1 is connected to the output matching circuit 13 via a DC cut-off capacitor C3 for blocking direct current. Have been. Further to the drain of the FETQ1 is connected the power supply V _CC via a switch yoke inductor L3 to prevent high frequency, the power supply V _CC is connected to the earth line GND through the bypass wire carrier path Sita C4 to prevent voltage fluctuation ing.

The FET Q1 amplifies the received signal S11 according to the bias potential input to the gate, and outputs the resulting high-frequency signal S12 via the DC cut-off capacitor C3 and the output matching circuit 13. Incidentally, the output matching circuit 13 is also an impedance matching circuit, and matches the input impedance of the output matching circuit 13 with the output impedance of the amplifier 12.

As described above, in the receiving amplifier circuit 10,
By inputting the high gate bias potential Vg1 to the gate of the FET Q1 during transmission, the low gate bias potential Vg
Since the drain current is increased as compared with the non-transmission when 2 is input, the linearity can be improved and the cross modulation distortion can be prevented. Further, since the drain current increases only at the time of transmission, power consumption can be reduced as compared with the case where the drain current increases regardless of the time of transmission or non-transmission.

[0017]

In a portable telephone, when the transmission power is large and the reception power is small, the reception sensitivity is deteriorated due to the cross modulation distortion. However, in the receiving amplifier circuit 10 as described above, even if the cross-modulation distortion does not affect the receiving sensitivity due to the large receiving power, the bias potential input to the gate of the FET Q1 is set to a high gate during transmission. The drain current is increased by switching to the bias potential Vg1. Further, even when the cross-modulation distortion does not affect the reception sensitivity because the transmission power is small, during transmission, the bias potential input to the gate of the FET Q1 is switched to the high gate bias potential Vg1 to reduce the drain current. Is increasing. That is, the reception amplifier circuit 10 does not increase the drain current only when the intermodulation distortion affects the reception sensitivity, but also increases the drain current when the intermodulation distortion does not affect the reception sensitivity. However, there is still an insufficient point in reducing power consumption.

The input and output impedances of the amplifier 12 change in conjunction with the switching of the bias potential input to the gate of the FET Q1. However, the output impedance of the input matching circuit 11 and the input impedance of the output matching circuit 13 are fixed, and if the input and output impedances of the amplifier 12 change as described above, there may be cases where the impedance cannot be matched. As a result, the noise figure of the reception amplifier circuit 10 may increase or the power gain may be out of balance. That is, when either one of the gate bias potentials is input to the gate of the FET Q1, the output impedance of the input matching circuit 11 and the output matching circuit 13 are set to minimize the noise figure.
When the input impedance is selected, the noise figure increases when the gate bias potential is switched, and the receiving sensitivity may be degraded. When either one of the gate bias potentials is input to the gate of the FET Q1, the output impedance of the input matching circuit 11 and the input impedance of the output matching circuit 13 are selected so that the power gain balance is optimized. In addition, when the gate bias potential is switched, the balance of the power gain is lost, which may cause the reception sensitivity to deteriorate.

The present invention has been made in view of the above points, and aims to propose an amplifier circuit and a transmission / reception apparatus that can further reduce power consumption as compared with the related art while preventing deterioration of reception sensitivity. It is.

[0020]

According to the present invention, there is provided a transmitting / receiving apparatus having a transmitting circuit and a receiving circuit, comprising: an amplifying means provided at a first stage of the receiving circuit for amplifying a received signal; Bias potential switching means for switching the bias potential applied to the amplifying means in accordance with a control signal supplied to the amplifying means; And control means for generating a control signal for switching to the bias potential.

As described above, the bias potential is switched from the low bias potential to the high bias potential only when the transmission power level is high and the reception power level is low, so that the reception sensitivity is degraded due to the intermodulation distortion. The current consumption increases only in such a case.

Further, according to the present invention, in an amplifier circuit provided at the first stage of a receiving circuit included in a transmitting / receiving apparatus, an amplifying means for amplifying a received signal and a bias for switching a bias current applied to the amplifying means in accordance with an input control signal Current switching means, and control means for generating a control signal for switching a bias current supplied to the amplifying means from a low bias current to a high bias current when the transmission power level of the transmission / reception device is high and the reception power level is low. It was provided.

As described above, by switching the bias current from the low bias current to the high bias current only when the transmission power level is high and the reception power level is low, the reception sensitivity is degraded due to the intermodulation distortion. The current consumption increases only in such a case.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings.

(1) First Embodiment In FIG. 1, reference numeral 20 denotes a portable telephone according to the first embodiment as a whole, which is roughly divided into transmission circuit blocks (22 to 22).
28), a receiving circuit block (26, 31-39) and a baseband signal processing circuit 2 for processing a baseband signal.
It consists of 1. First, the baseband signal processing circuit section 21 outputs to the modulator 22 a transmission baseband signal S21 generated by performing predetermined signal processing on an audio signal input from a microphone (not shown). The modulator 22 modulates the transmission baseband signal S21 based on, for example, a modulation method such as a four-phase shift keying method, and transmits the resulting transmission intermediate frequency signal S22 to a variable amplifier circuit (hereinafter, referred to as AGC) 23. Output.

The AGC 23 controls the gain on the basis of the transmission power level signal S23 sent from the baseband signal processing circuit 21, thereby transmitting the transmission intermediate frequency signal S22.
Is amplified to a desired level, and the resulting transmission intermediate frequency signal S24 is output to the bandpass filter 24. The bandpass filter 24 removes unnecessary components and noise outside the band from the transmission intermediate frequency signal S24, and outputs the resulting transmission intermediate frequency signal S25 to the mixer 25. Mixer 2
Reference numeral 5 performs frequency conversion by multiplying the transmission intermediate frequency signal S25 by the local frequency signal S26 supplied from the local oscillator 26, and outputs the resulting transmission high frequency signal S27 to the bandpass filter 27.

The band-pass filter 27 removes unnecessary components and noise outside the band from the transmission high-frequency signal S27, and outputs the transmission high-frequency signal S28 obtained as a result to the transmission amplification circuit 28. The transmission amplification circuit 28 amplifies the transmission high-frequency signal S28, and supplies the transmission signal S29 obtained as a result to the antenna 30 via the duplexer 29 which is a signal separation circuit. As a result, the transmission signal S29 is transmitted from the antenna 30.

On the other hand, the reception signal S30 received by the antenna 30 is separated via the duplexer 29 and then received by the reception amplification circuit in the reception amplification circuit 31 provided at the first stage of the reception circuit block. 32.
Here, the control circuit 33 in the reception amplification circuit unit 31 converts the control signal S32 for controlling the reception amplification circuit 32 based on the transmission power level signal S23 and the reception power level signal S31 sent from the baseband signal processing circuit unit 21. Generate
The control signal S32 is output to the reception amplification circuit 32. The reception amplification circuit 32 amplifies the reception signal S30 with a bias potential according to the control signal S32, and outputs a reception high-frequency signal S33 obtained as a result to the mixer.

The mixer 34 receives the high frequency signal S3 from the local frequency signal S34 supplied from the local oscillator 26.
The frequency conversion is performed by multiplying the signal by 3 and the resultant received intermediate frequency signal S35 is output to the amplifier circuit 35. The amplification circuit 35 amplifies the reception intermediate frequency signal S35,
The resulting reception intermediate frequency signal S36 is converted to a SAW (Sur
face Acoustic Wave) Output to the filter 36. SAW
The filter 36 removes unnecessary components and noise outside the band from the received intermediate frequency signal S36, and outputs the resulting received intermediate frequency signal S37 to the AGC 37.

The AGC 37 controls the gain on the basis of the received power level signal S31 sent from the baseband signal processing circuit 21 to thereby receive the intermediate frequency signal S37.
Is amplified to a desired level, and the resulting received intermediate frequency signal S38 is output to the bandpass filter 38. The bandpass filter 38 removes unnecessary components and noise outside the band from the received intermediate frequency signal S38, and outputs the resulting received intermediate frequency signal S39 to the demodulator 39. Demodulator 3
9 demodulates the reception intermediate frequency signal S39 based on a demodulation method such as a synchronous detection method, and converts the reception baseband signal S40 obtained as a result to the baseband signal processing circuit unit 21.
Output to

The baseband signal processing circuit 21 reproduces an audio signal by subjecting the received baseband signal S40 to predetermined signal processing, and outputs this to a speaker (not shown). The baseband signal processing circuit unit 21 generates a transmission power level signal S23 based on the data indicating the transmission power level included in the reception baseband signal S40, and converts the transmission power level signal S23 into the AGC 23 and the reception amplifier circuit unit 31. To the control circuit 33. Further, the baseband signal processing circuit section 21 receives the reception baseband signal S4
0, the received power level signal S31 indicating the power level of the received signal is generated, and the received power level signal S31
The signal is output to the control circuit 33 in the GC 37 and the reception amplification circuit unit 31.

Here, the above-described reception amplification circuit section 31 will be specifically described with reference to FIG. First, the control circuit 33
Transmits the transmission power level signal S23 transmitted from the baseband signal processing circuit unit 21 to the transmission power information signal generator 51.
And a reception power level signal S31 sent from the baseband signal processing circuit section 21 to a reception power information signal generator 52. Transmission power information signal generator 5
1 generates an analog signal of the voltage level indicated by the transmission power level signal S23, and outputs this to the comparator 53 as the transmission power level voltage _VTX . The comparator 53 compares the transmission power level voltage V _TX with a predetermined transmission threshold voltage v _TX, and as a result, when the transmission power level voltage V _TX is higher than the transmission threshold voltage v _TX , the transmission power of the logic level “H” Comparison signal S5
1 to the AND circuit 54 to output the transmission power level voltage V _TX
Is smaller than the transmission threshold voltage v _TX , a logical-level “L” transmission power comparison signal S 51 is output to the AND circuit 54.

The reception power information signal generator 52 generates an analog signal of the voltage level indicated by the reception power level signal S31, and uses this analog signal as the reception power level voltage V _RX.
5 is output. The comparator 55 compares the reception power level voltage V _RX with a predetermined reception threshold voltage v _RX . As a result, if the reception power level voltage V _RX is smaller than the reception threshold voltage v _RX , the reception power of the logic level “H” is output. The comparison signal S52 is output to the AND circuit 54, and when the reception power level voltage V _RX is higher than the reception threshold voltage v _RX , the reception power comparison signal S52 at the logical level “L” is output to the AND circuit 54.

The AND circuit 54 outputs a transmission power comparison signal S51.
And a logical product of the received power comparison signal S52 and the resulting control signal S32 is output to the reception amplifier circuit 32. In this case, if both the transmission power comparison signal S51 and the reception power comparison signal S52 are at the logic level “H”,
The control signal S32 of the logic level “H” is received by the reception amplification circuit 32.
If either or both of the transmission power comparison signal S51 and the reception power comparison signal S52 are at the logic level “L”, the control signal S32 of the logic level “L” is output to the reception amplification circuit 32.

The receiving amplifier circuit 32 is a variable input matching circuit 5
6, an amplifier 57 and a variable output matching circuit 58, and the control signal S32 is transmitted to the variable input matching circuit 5
6, an amplifier 57 and a variable output matching circuit 58. The amplifier 57 is supplied with a predetermined potential from a power supply 59, and switches the bias potential based on a control signal S32. That is, when the control signal S32 of the logic level “H” is input, the bias voltage is switched to the high bias potential, and when the control signal S32 of the logic level “L” is input, the bias voltage is switched to the low bias potential. Incidentally, since the input and output impedances of the amplifier 57 change in conjunction with the switching of the bias potential, a variable input matching circuit 56 is provided at the input stage of the amplifier 57.
Is provided, and a variable output matching circuit 58 is provided at the output stage of the amplifier 57.

The variable input matching circuit 56 is an impedance matching circuit that changes the output impedance based on the control signal S32,
7 is matched with the input impedance. Similarly, the variable output matching circuit 58 is also an impedance matching circuit, and changes the input impedance based on the control signal S32 to change the input impedance and the amplifier 5.
7 is matched with the output impedance. Thus, the reception amplification circuit 32 inputs the reception signal S30 to the amplifier 57 via the variable input matching circuit 56, amplifies the reception signal S30 by the amplifier 57, and converts the resulting reception high frequency signal S33 to a variable output matching circuit. 58
Output via.

Here, a specific configuration of the reception amplification circuit section 31 will be described with reference to FIG. In this case, the control circuit 3
The comparators 53 and 55 in 3 are constituted by differential amplifiers 61 and 62. In the differential amplifier 61, a transmission power level voltage V _TX transmitted from the transmission power information signal generator 51 is input to a non-inverting input terminal, and a predetermined reference voltage v _TX is input to an inverting input terminal. On the other hand, the differential amplifier 6
2, the reception power information signal generator 5 is connected to the inverting input terminal.
2, the received power level voltage V _RX transmitted from
A predetermined reference voltage v _RX is input to the non-inverting input terminal.

The receiving amplifier circuit 32 applies the control signal S32 to the varactor diode bias potential switching switch SW11 of the variable input matching circuit 56, the gate bias potential switching switch SW12 of the amplifier 57, and the variable output matching circuit 5 described later.
8 varactor diode bias potential switching switch.

First, the variable input matching circuit 56 converts the input received signal S30 into a DC cut-off capacitor C11 for blocking direct current, a matching inductor L11 for finely adjusting the output impedance of the variable input matching circuit 56, and an amplifier 57. FE via DC cut capacitor C12
Input to the gate of TQ11. Matching inductor L11
The connection point of the DC cut capacitor C12 and the DC cut capacitor C12 is connected to the ground line GND via a varactor diode V1 whose capacitance changes according to the bias potential, and the ground line GND via a matching capacitor C13 for fine adjustment of the output impedance. It is connected to the.

The variable varactor diode bias potential input circuit 63 is connected to the varactor diode V1. In the variable varactor diode bias potential input circuit 63, a series circuit of the resistors R11, R12 and R13 is connected between the power supply _VCC and the ground line GND, and the varactor diode bias potential Vi1 is supplied from the middle point of connection between the resistors R11 and R12. Occurs and the resistances R12 and R12
13 to the varactor diode bias potential V
i2. Resistors R11 and R
12 is connected to the first input terminal of the varactor diode bias potential switching switch SW11, and the connection middle point of the resistors R12 and R13 is connected to the second input terminal of the varactor diode bias potential switching switch SW11. It is connected.

The varactor diode bias potential switching switch SW11 switches the connection state based on a control signal S32 sent from the control circuit 33. That is, the varactor diode bias potential switching switch SW11 outputs the control signal S3 of the logic level “H”.
When 2 is input, the connection state is switched to the first input terminal side to select the varactor diode bias potential Vi1, and when the control signal S32 of the logic level “L” is input, the connection state is changed to the second input terminal. And the varactor diode bias potential Vi2 is selected. On the other hand, the output terminal of the varactor diode bias potential changeover switch SW11 is connected to the varactor diode V1 via the switch yoke inductor L12 to prevent high frequency, via a bypass wire carrier path Sita C14 to prevent the voltage fluctuation of the power source V _CC Earth line G
Connected to ND.

Thus, the variable varactor diode bias potential input circuit 63 outputs the logic level "H" control signal S3.
2 is input, the varactor diode bias potential switching switch SW11 is switched to the first input terminal side to input the high varactor diode bias potential Vi1 to the varactor diode V1, and the control signal of the logic level "L" When S32 is input, the varactor diode bias potential switching switch SW11 is switched to the second
And the low varactor diode bias potential Vi2 can be input to the varactor diode V1.

Subsequently, in the amplifier 57, the FET Q1
The variable gate bias potential input circuit 64 is connected to one gate. This variable gate bias potential input circuit 6
4 is a circuit in which a series circuit of resistors R14, R15 and R16 is connected between the power supply _Vcc and the ground line GND,
From the middle point of connection between R14 and R15 to the gate bias potential Vg
11, and a gate bias potential Vg12 is generated from the midpoint of connection between the resistors R15 and R16. A first input terminal of the gate bias potential switching switch SW12 is connected to a connection point between the resistors R14 and R15, and a second input terminal of the gate bias potential switching switch SW12 is connected to a connection point between the resistors R15 and R16. Is connected.

Gate bias potential switching switch SW12
The connection state is switched based on a control signal S32 sent from the control circuit 33. That is, when the control signal S32 of the logic level "H" is input, the gate bias potential switching switch SW12 switches the connection state to the first input terminal side, selects the gate bias potential Vg11, and selects the logic level "L". Control signal S
When 32 is input, the connection state is switched to the second input terminal side to select the gate bias potential Vg12. On the other hand, the output terminal of the gate bias potential switching switch SW12 is connected to the gate of the FET Q11 via a yoke inductor L13 for blocking high frequency, and via a bypass capacitor C15 for preventing voltage fluctuation of the power supply V _CC. It is connected to the ground line GND.

Thus, when the control signal S32 of the logic level "H" is input, the variable gate bias potential input circuit 64 switches the gate bias potential switching switch SW12.
To the first input terminal side to input the high gate bias potential Vg11 to the gate of the FET Q11. When the control signal S32 of the logic level "L" is input, the gate bias potential switching switch SW12 is turned on. 2 to the low gate bias potential V
g12 can be input to the gate of FET Q11.

The source of the FET Q11 is connected to the ground line GND via a matching inductor L14 for blocking high frequencies.
The drain of the FET Q11 is connected to a variable output matching circuit 58 via a DC cut-off capacitor C16 for blocking direct current. Further FET Q1
1 is connected to a power supply V _CC via a yoke inductor L15 for blocking high frequencies.
_The ground line GND is connected to _CC via a bypass capacitor C17 for preventing voltage fluctuation.

Next, as shown in FIG. 4, the input terminal of the variable output matching circuit 58 is connected to the output terminal via a matching inductor L16 for finely adjusting the input impedance of the variable output matching circuit 58. , And outputs the received high-frequency signal S33 input from the amplifier 57 via the matching inductor L16. The input side of the matching inductor L16 is connected to the ground line GND via a matching capacitor C18 for finely adjusting the input impedance, a DC cut capacitor C19, and a varactor diode V2 whose capacitance changes according to the bias potential. They are sequentially connected to the ground line GND.

The variable varactor diode bias potential input circuit 65 is connected to the varactor diode V2. In the variable varactor diode bias potential input circuit 65, a series circuit of the resistors R17, R18 and R19 is connected between the power supply V _CC and the ground line GND, and the varactor diode bias potential Vo1 is supplied from the connection point between the resistors R17 and R18. Occurs, and the resistors R18 and R
19 to the varactor diode bias potential V
o2. Resistance R17 and R
18 is connected to the first input terminal of the varactor diode bias potential switching switch SW13, and the connection middle point of the resistors R18 and R19 is connected to the second input terminal of the varactor diode bias potential switching switch SW13. It is connected.

The varactor diode bias potential switching switch SW13 switches the connection state based on a control signal S33 sent from the control circuit 33. That is, the varactor diode bias potential switching switch SW13 outputs the control signal S3 of the logic level “H”.
When 2 is input, the connection state is switched to the first input terminal side to select the varactor diode bias potential Vo1, and when the control signal S32 of the logic level “L” is input, the connection state is changed to the second input terminal side. And the varactor diode bias potential Vo2 is selected. On the other hand, an output terminal of the varactor diode bias potential switching switch SW13 is connected to a varactor diode V2 via a yoke inductor L17 for blocking a high frequency and via a bypass capacitor C20 for preventing a voltage fluctuation of the power supply V _CC. Earth line G
Connected to ND.

Thus, the variable varactor diode bias potential input circuit 65 outputs the control signal S3 of the logic level "H".
2 is input, the varactor diode bias potential switching switch SW13 is switched to the first input terminal side, so that the high varactor diode bias potential Vo1 can be input to the varactor diode V2, and the control signal of logic level "L" can be input. When S32 is input, the varactor diode bias potential switching switch SW13 is switched to the second
, The low varactor diode bias potential Vo2 can be input to the varactor diode V2.

In the above-described configuration, the control circuit 33 analyzes the transmission power level signal S23 and the reception power level signal S31, and when the transmission power level is high and the reception power level is low, the control circuit 33 changes the logic level to "H". A control signal S32 is generated, and a control signal S32 of a logic level "L" is generated for a combination except when the transmission power level is high and the reception power level is low, and the control signal S32 is converted to an amplifier 57, a variable input matching circuit. 56 and a variable output matching circuit 58.

The amplifier 57 inputs the control signal S32 to the gate bias potential switching switch SW12, and when the input control signal S32 is at the logical level "H", that is, when the transmission power level is high and the reception power level is low. Input the high gate bias potential Vg11 to the gate of the FET Q11, and when the control signal S32 is at the logic level "L", that is, except when the transmission power level is high and the reception power level is low, the low gate bias potential Vg11
g12 is input to the gate of the FET Q11. Accordingly, when the transmission power level is high and the reception power level is low, the linearity of the amplifier 57 can be improved by increasing the drain current of the FET Q11, and the intermodulation distortion can be reduced.

In practice, as shown in FIG. 5, when the high gate bias potential Vg11 is input to the gate of the FET Q11 when the transmission power level is high and the reception power level is low, the input voltage is lower than when the low gate bias potential Vg12 is input. As a result, the drain current increases from i2 to i1, so that intermodulation distortion can be reduced.

In this case, the high gate bias potential Vg is obtained only when the transmission power level at which the reception sensitivity is deteriorated due to the intermodulation distortion is large and the reception power level is small.
11 is input to the gate of the FET Q11, the drain current can be increased only when the reception sensitivity is deteriorated due to the intermodulation distortion, and thus the drain current is constantly increased during transmission as in the conventional case. In this case, the current consumption can be reduced as compared with the case where the power consumption is reduced, so that the power consumption can be reduced as a whole.

The variable input matching circuit 56 controls the control signal S3
2 is a varactor diode bias potential switching switch SW
11, when the input control signal S32 is at the logic level "H", the high varactor diode bias potential Vi1 is input to the varactor diode V1, and the control signal S32 is input.
When 32 is at the logic level "L", the low varactor diode bias potential Vi2 is input to the varactor diode V1. Thus, when the transmission power level is high and the reception power level is low, the varactor diode V1
Can be increased, and the capacitance of the varactor diode V1 can be reduced except when the transmission power level is high and the reception power level is low. Therefore, the variable input matching circuit 56 and the amplifier 57 can be matched by causing the output impedance of the variable input matching circuit 56 to follow the change in the input impedance of the amplifier 57.

Here, the relationship between the input impedance of the amplifier 57 and the output impedance of the variable input matching circuit 56 will be described with reference to FIG. First, consider the case where the control signal S32 of the logic level “H” is input to the amplifier 57 and the variable input matching circuit 56. In this case, the amplifier 57 inputs a high gate bias potential Vg11 to the gate of the FET Q11 to increase the drain current.
7 changes to Δopt1. On the other hand, when the variable input matching circuit 56 inputs the high varactor diode bias potential Vi1 to the varactor diode V1, the capacitance increases, and the output impedance of the variable input matching circuit 56 changes to Γ1. Therefore, the output impedance Γ1 of the variable input matching circuit 56 and the input impedance Γopt1 of the amplifier 57 can be matched, and it is possible to prevent an increase in noise figure and an imbalance in power gain, thereby preventing deterioration of reception sensitivity. .

In this state, when the control signal S32 of the logic level "L" is input, the amplifier 57 inputs the low gate bias potential Vg12 to the gate of the FET Q11, whereby the drain current decreases, and the input impedance changes from Γopt1 to Γopt1. Changes to Γopt2. On the other hand, the variable input matching circuit 56 reduces the capacitance by inputting the low varactor diode bias potential Vi2 to the varactor diode V1 and reduces the output impedance from Γ1 to Γ2.
Changes to Accordingly, the output impedance Γ2 of the variable input matching circuit 56 and the input impedance Γopt2 of the amplifier 57
Can be matched.

Similarly, the variable output matching circuit 58 controls the control signal S
32 is a varactor diode bias potential switching switch S
When the input control signal S32 is at the logic level "H", the high varactor diode bias potential Vo1 is input to the varactor diode V2. When the control signal S32 is at the logic level "L", the low varactor diode bias is applied. The potential Vo2 is input to the varactor diode V2. Thus, when the transmission power level is high and the reception power level is low, the varactor diode V
2 can be increased, and the capacitance of the varactor diode V2 can be reduced except when the transmission power level is high and the reception power level is low. Accordingly, the input impedance of the variable output matching circuit 58 is made to follow the change in the output impedance of the amplifier 57, and
And can be matched.

According to the above configuration, the high gate bias potential Vg11 is input to the gate of the FET Q11 only when the transmission power level is high and the reception power level is low. Since the drain current increases only when the sensitivity is deteriorated, the power consumption can be further reduced as compared with the related art while preventing the reception sensitivity from being deteriorated.

(2) Second Embodiment FIG. 7 in which parts corresponding to those in FIG.
9 shows a reception amplification circuit unit 70 according to the embodiment, and has the same configuration as the reception amplification circuit unit 31 according to the first embodiment, except for the configuration of the amplifier 72 in the reception amplification circuit 71.

The amplifier 72 is connected to the variable input matching circuit 56, and converts the received signal S30 into a DC cut capacitor C.
The signal is input to the gate of the FET Q21 via the line 31. FET
The connection point of the resistors R31 and R32 connected in series between the power supply _Vcc and the ground line GND is connected to the gate of Q21 via a inductor y31 that blocks high frequencies. Is connected to the ground line GND via a bypass capacitor C32 for preventing voltage fluctuation of the power supply V _CC . On the other hand, the source of the FET Q21 is connected to the ground line GND via a matching inductor L32 for blocking a high frequency.

A variable bias current input circuit 73 comprising a current mirror type constant current source is connected to the drain of the FET Q21.
Is connected. This variable bias current input circuit 73
The ratio of Emitsutasaizu "10: 1" includes a pair of transistors Tr1 and Tr2 which are selected, these emitters of the transistors Tr1 and Tr2 are commonly connected to the power supply V _CC, also bases are commonly connected In addition, these bases are commonly connected to the collector of the transistor Tr2. The collector of the transistor Tr2 is connected to the input terminal of the bias current switching switch SW21, and the first output terminal of the bias current switching switch SW21 is connected to the ground line GND via the resistor R33.
, And a second output terminal is connected to the ground line GND via a resistor R34 having a larger value than the resistor R33.
It is connected to the. On the other hand, the collector of the transistor Tr1 is connected to the drain of the FET Q21 via a high-frequency inductor L33 that blocks high frequency. This FE
The drain of TQ21 is connected to a variable output matching circuit 58 via a DC cut-off capacitor C33 for blocking direct current.

The bias current switch SW 21 switches the connection state based on a control signal S 32 sent from the control circuit 33. That is, the bias current switching switch SW21 outputs the logic level "H".
When the control signal S32 is input, the connection state is changed to the first state.
By selecting a switched resistor R33 to the output terminal side of the high control current I ₁ determined by connexion to the resistor R33 flows through the transistor Tr2, when the control signal S32 of the logic level "L" is input, the connection by switching the state to the second output terminal side selects a resistor R34, determined connexion by the relevant resistor R34, and low control current I ₂ of lower value than the high control current I ₁ flows through the transistor Tr2 It has been made like that.

Thus, the variable bias current input circuit 73
When the control signal S32 of the logic level "H" is input, by switching the connection state of the bias current switching switch SW21 to the first output terminal side, high control current I ₁ of the 10 times higher bias current the I ₁₁ transistor Tr
1 and supplies the same as the drain current of the FET Q21. When the control signal S32 of the logic level "L" is input, the connection state of the bias current switching switch SW21 is switched to the second output terminal side. passing a low control current I filed a low bias current I ₁₂ of lower value than the high bias current I ₁₁ at 10 times the ₂ transistors Tr1, and supplies it as the drain current of the FET Q21.

In the above configuration, the control circuit 33 analyzes the transmission power level signal S23 and the reception power level signal S31, and when the transmission power level is high and the reception power level is low, the control circuit 33 changes the logic level to "H". A control signal S32 is generated, and a control signal S32 of a logic level "L" is generated for a combination except when the transmission power level is high and the reception power level is low, and the control signal S32 is converted to an amplifier 72, a variable input matching circuit. 56 and a variable output matching circuit 58.

The amplifier 72 inputs the control signal S32 to the bias current switching switch SW21. When the input control signal S32 is at the logical level "H", that is, when the transmission power level is high and the reception power level is low, ,
The high bias current I ₁₁ is input to the drain of the FET Q21, when the control signal S32 is at logical level "L", i.e. a large transmission power levels, and in addition if the received power level is low, a low bias current I ₁₂ FET Q21 Input to the drain of. Thereby, when the transmission power level is high and the reception power level is low, the FET Q21
, The linearity of the amplifier 57 can be improved, and intermodulation distortion can be reduced.

[0067] By this, the transmission power level of deterioration by connexion reception sensitivity intermodulation distortion is large and has a high bias current I ₁₁ only if the received power level is small so that the input to the drain of the FET Q21, The drain current can be increased only when the reception sensitivity is degraded due to the cross-modulation distortion, and thus the current consumption can be reduced as compared with the conventional case where the drain current is constantly increased during transmission. The power consumption can be reduced as a whole.

In the amplifier 72, the FET Q2
The first embodiment is configured such that a variable bias current input circuit 73 including a current mirror type constant current source is connected to the drain of the FET 1 and a bias current is input to the drain of the FET Q21 by the variable bias current input circuit 73. There is a special effect when the drain current can be determined more accurately than when a bias potential is input to the gate of the FET Q11 as in the example.

In the amplifier 72, a variable bias current input circuit 73 composed of a current mirror type constant current source is connected to the drain of the FET Q21, and the bias current is controlled based on the control signal S32 input to the variable bias current input circuit 73. Since the connection state of the switching switch SW21 is switched, the current flowing through the transistor Tr1 can be controlled only by changing the control current flowing through the transistor Tr2. Therefore, the bias current supplied to the drain of the FET Q21 can be easily reduced. Can be controlled.

[0070] According to the above configuration, by the transmission power level is large and has a high bias current I ₁₁ only if the received power level is small so that the input to the drain of the FET Q21, by connexion received intermodulation distortion Since the drain current increases only when the sensitivity is deteriorated, the power consumption can be further reduced as compared with the related art while preventing the reception sensitivity from being deteriorated.

Further, by connecting a current mirror type constant current source to the drain of the FET Q21 and inputting a bias current to the drain of the FET Q21 by the current mirror type constant current source, a bias potential is applied to the gate of the FET Q11. The drain current can be determined more accurately than when inputting.

(3) Other Embodiments In the above-described embodiment, the case where the output impedance of the variable input matching circuit 56 and the input impedance of the variable output matching circuit 58 are changed based on the control signal S32 will be described. However, the present invention is not limited to this,
If the increase in the noise figure and the imbalance in power gain that occur when the input and output impedances of the amplifiers 57 and 72 change do not affect the receiving sensitivity,
The output impedance of the input matching circuit may be fixed so that only the input impedance of the output matching circuit can be changed, or the input impedance of the output matching circuit may be fixed and only the output impedance of the input matching circuit may be changed You may be made to be able to make it.

In the above embodiment, the comparator 53 compares the transmission power level voltage V _TX with a predetermined transmission threshold voltage v _TX, and the comparator 53 compares the reception power level voltage V _RX with a predetermined reception threshold voltage v _RX. The differential amplifiers 61 and 6
2 has been described, but the present invention is not limited to this. For example, various other comparators may be applied, such as a shutter trigger circuit.

In the above embodiment, the reception signal S
FETs Q11 and Q2
1 has been described, but the present invention is not limited to this, and various other amplifying elements such as bipolar transistors may be applied as long as they are low-noise amplifying elements. .

In the above embodiment, the case where the output impedance of the variable input matching circuit 56 is determined using the varactor diode V1, the matching inductor L11 and the matching capacitor C13 has been described. Not limited to this, the matching inductor L11 and the matching capacitor C13 finely adjust the output impedance.
If the output impedance can be determined only by
The variable input matching circuit 56 may be configured by excluding the matching inductor L11 and the matching capacitor C13.

In the above-described embodiment, the case where the input impedance of the variable output matching circuit 58 is determined using the varactor diode V2, the matching inductor L16 and the matching capacitor C18 has been described. Not limited to this, the matching inductor L16 and the matching capacitor C18 finely adjust the input impedance.
If the input impedance can be determined only by
The variable output matching circuit 58 may be configured by excluding the matching inductor L16 and the matching capacitor C18.

In the above embodiment, the FET Q1
1, the sources of Q21 are matched inductors L14, L32
Has been described above, the present invention is not limited to this. The source of the FET may be directly connected to the ground line GND.

In the second embodiment, the case where the bias current input to the drain of the FET Q21 is switched by the current mirror type constant current source has been described. However, the present invention is not limited to this. As long as the bias current input to the drain can be switched, various other constant current sources such as an FET constant current source may be applied.

In the above embodiment, the case where the bias potential input to the gate of the FET Q11 is switched by using the variable gate bias potential input circuit 64 has been described. However, the present invention is not limited to this, and the control circuit 3
Any bias potential switching means that switches the bias potential in accordance with the control signal S32 input from the control signal S3 may be used.

Further, in the above-described embodiment, the case where the bias current input to the drain of the FET Q21 is switched by using the variable bias current input circuit 73 has been described. Any means may be used as the bias current switching means for switching the bias current in accordance with the control signal S32 input from the controller.

In the above embodiment, the case where the bias potentials input to the varactor diodes V1 and V2 are switched by using the variable varactor diode bias potential input circuits 63 and 65 has been described. The present invention is not limited to this, and any bias potential switching means that switches the bias potential according to the control signal S32 input from the control circuit 33 may be used.

In the above embodiment, the case where the present invention is applied to the mobile phone 20 has been described. However, the present invention is not limited to this, and for example, a PHS (Personal Ha
The present invention may be applied to a wireless communication terminal device having various other transmitting and receiving functions, such as an ndyphne system (simplified mobile phone device).

Further, in the above-described embodiment, a case has been described in which the present invention is applied to a wireless communication terminal apparatus. However, the present invention is not limited to this, and for example, the present invention is applied via a wired transmission path such as a coaxial cable. The present invention may be applied to various other transmitting / receiving devices, such as a transmitting / receiving device for transmitting / receiving data.

[0084]

As described above, according to the present invention, when the transmission power level is high and the reception power level is low,
By switching the bias potential from the low bias potential to the high bias potential, the current consumption increases only when the reception sensitivity is deteriorated due to the intermodulation distortion.
Thus, it is possible to further reduce the power consumption as compared with the related art while preventing the deterioration of the receiving sensitivity.

Further, according to the present invention, when the transmission power level is high and the reception power level is low, the bias current is switched from a low bias current to a high bias current. Since the current consumption increases only when the sensitivity is deteriorated, the power consumption can be further reduced as compared with the related art while preventing the deterioration of the reception sensitivity.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a mobile phone according to the present invention.

FIG. 2 is a block diagram showing a configuration of a reception amplification circuit unit.

FIG. 3 is a connection diagram illustrating a configuration of a reception amplification circuit unit.

FIG. 4 is a connection diagram illustrating a configuration of a variable output matching circuit.

FIG. 5 is a schematic diagram illustrating a relationship between a drain current and intermodulation distortion.

FIG. 6 is a schematic diagram illustrating a relationship between an input impedance of an amplifier and an output impedance of a variable input matching circuit.

FIG. 7 is a connection diagram showing a second embodiment of the reception amplification circuit unit.

FIG. 8 is a block diagram showing an antenna peripheral circuit of the mobile phone.

FIG. 9 is a connection diagram showing a configuration of a conventional reception amplifier circuit.

[Explanation of symbols]

1, 20… mobile phone, 3, 29… duplexer,
4, 30 antenna, 5, 10, 32, 71 reception amplification circuit, 12, 57, 72 amplifier, 21 baseband signal processing circuit section, 31, 70 reception amplification circuit section, 33 ... Control circuit, 53, 55 ... Comparator, 54 ...
... AND circuit, 56 ... variable input matching circuit, 58 ... variable output matching circuit, 61, 62 ... differential amplifier, 63, 6
5 ... Variable varactor diode bias potential input circuit
64: Variable gate bias potential input circuit; 73: Variable bias current input circuit.

Claims (22)

[Claims] An amplifying circuit provided at a first stage of a receiving circuit included in a transmitting / receiving device, an amplifying means for amplifying a received signal, and a first bias for switching a bias potential applied to the amplifying means according to an input control signal Potential switching means, and generating the control signal for switching the bias potential applied to the amplifying means from a low bias potential to a high bias potential when the transmission power level of the transmission / reception device is high and the reception power level is low. An amplifier circuit comprising control means. 2. An input impedance matching means provided at an input stage of the amplifying means for impedance matching with an input impedance of the amplifying means, and the input impedance matching means according to a control signal generated by the control means. 2. The amplifier circuit according to claim 1, further comprising: a second bias potential switching unit that changes an output impedance of the input impedance matching unit by switching a bias potential applied to the amplifier. 3. The input impedance matching means comprises a varactor diode.
2. The amplifier circuit according to 1. 4. An output impedance matching means provided at an output stage of the amplifying means for impedance matching with an output impedance of the amplifying means, and the output impedance matching means in response to a control signal generated by the control means. 3. The amplifier circuit according to claim 1, further comprising: third bias potential switching means for changing an input impedance of said output impedance matching means by switching a bias potential applied to said amplifier. 5. The output impedance matching means comprises a varactor diode.
2. The amplifier circuit according to 1. 6. An amplifying circuit provided at the first stage of a receiving circuit included in a transmitting / receiving device, comprising: amplifying means for amplifying a received signal; and bias current switching means for switching a bias current applied to said amplifying means in accordance with an input control signal. Control means for generating the control signal for switching the bias current to be supplied to the amplifying means from a low bias current to a high bias current when the transmission power level of the transmitting / receiving device is high and the reception power level is low; An amplifier circuit comprising: 7. The amplifier circuit according to claim 6, wherein said bias current switching means comprises a current mirror type constant current source, and switches said bias current supplied to said amplification means. 8. An input impedance matching means provided at an input stage of the amplifying means for matching impedance with an input impedance of the amplifying means, and the input impedance matching means according to a control signal generated by the control means. 7. The amplifier circuit according to claim 6, further comprising: first bias potential switching means for changing an output impedance of said input impedance matching means by switching a bias potential applied to said amplifier. 9. The input impedance matching means comprises a varactor diode.
2. The amplifier circuit according to 1. 10. An output impedance matching means provided at an output stage of said amplifying means for impedance matching with an output impedance of said amplifying means, and said output impedance matching means in response to a control signal generated by said control means. 7. An amplifier circuit according to claim 6, further comprising a second bias potential switching means for changing an input impedance of said output impedance matching means by switching a bias potential applied to said amplifier. 11. The output impedance matching means comprises a varactor diode.
The amplifier circuit according to 0. 12. A transmission / reception device having a transmission circuit and a reception circuit, comprising: amplification means provided at the first stage of the reception circuit for amplifying a reception signal; and a bias potential applied to the amplification means according to an input control signal. A first bias potential switching means for switching, and the bias potential switching means for switching the bias potential applied to the amplifying means from a low bias potential to a high bias potential when the transmission power level of the transmission / reception device is high and the reception power level is low. And a control unit for generating a control signal. 13. An input impedance matching means provided at an input stage of said amplifying means for impedance matching with an input impedance of said amplifying means, and said input impedance matching means in response to a control signal generated by said control means. 13. The transmission / reception apparatus according to claim 12, further comprising: a second bias potential switching unit that changes an output impedance of the input impedance matching unit by switching a bias potential applied to the input / output unit. 14. The input impedance matching means comprises a varactor diode.
4. The transmitting / receiving device according to 3. 15. An output impedance matching means provided at an output stage of the amplifying means for impedance matching with an output impedance of the amplifying means, and the output impedance matching means in response to a control signal generated by the control means. 13. The transmission / reception apparatus according to claim 12, further comprising: third bias potential switching means for changing an input impedance of said output impedance matching means by switching a bias potential applied to said output impedance matching means. 16. The output impedance matching means comprises a varactor diode.
6. The transmission / reception device according to 5. 17. An amplifying circuit provided at a first stage of a receiving circuit included in a transmitting / receiving device, an amplifying means for amplifying a received signal, and a bias current switching means for switching a bias current given to said amplifying means in accordance with an input control signal. Control means for generating the control signal for switching the bias current to be supplied to the amplifying means from a low bias current to a high bias current when the transmission power level of the transmitting / receiving device is high and the reception power level is low; A transmission / reception device comprising: 18. The transmitting / receiving apparatus according to claim 17, wherein said bias current switching means comprises a current mirror type constant current source, and switches said bias current supplied to said amplification means. 19. An input impedance matching means provided at an input stage of the amplifying means for impedance matching with an input impedance of the amplifying means, and the input impedance matching means according to a control signal generated by the control means. 18. The transmission / reception apparatus according to claim 17, further comprising: a first bias potential switching unit that changes an output impedance of the input impedance matching unit by switching a bias potential applied to the input / output unit. 20. The apparatus according to claim 1, wherein said input impedance matching means comprises a varactor diode.
10. The transmission / reception device according to 9. 21. An output impedance matching means provided at an output stage of said amplifying means for impedance matching with an output impedance of said amplifying means, and said output impedance matching means in response to a control signal generated by said control means. 18. The transmission / reception apparatus according to claim 17, further comprising: a second bias potential switching unit that changes an input impedance of the output impedance matching unit by switching a bias potential applied to the output impedance matching unit. 22. The output impedance matching means comprises a varactor diode.
2. The transmitting / receiving device according to claim 1.