JPH10242825A - Output circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a peak current and to decrease a noise voltage without being attended with increase in the number of transistors(TRs) and increase in current consumption. SOLUTION: When an input voltage transits to a high level, a gate voltage Vg11 of a TR 11 is raised up to a 1st intermediate level by a TR 16 of an inverting drive circuit 14 to reduce a driving force or the TR 16, and an output voltage at an output terminal 13 goes to a high level, then a TR 18 is conductive to mask the TR 16 and the gate voltage Vg11 is reduced completely to a low level thereby making the TR 11 completely conductive. On the contrary, when the input voltage transits to a low level, the similar operation is made by the other inverting drive circuit 19.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output circuit used in a semiconductor integrated circuit, and more particularly to a method of reducing a peak value of a current without deteriorating a current driving capability to prevent a system malfunction due to noise. The present invention relates to a technique for relaxing the limit on the number of circuits that can be operated simultaneously.

[0002]

2. Description of the Related Art The number of semiconductor output circuits for external interfaces and semiconductor output circuits for internal bus lines has increased from 32 to 64 or more due to the enhancement of functions of MOS-LSIs and the speeding up of systems. For this reason, the number of simultaneous operations of the semiconductor output circuit has been greatly increased. Therefore, when the semiconductor output circuits operate simultaneously, the voltage of the power supply line in the chip temporarily decreases or the voltage of the GND line temporarily increases due to the charge and discharge.

The voltage fluctuation is represented by the product (L · di / dt) of the time change of the charging / discharging current and the inductance L of the power supply line including the bonding wire. The output voltage of an adjacent output circuit fluctuates due to this voltage fluctuation (hereinafter, this fluctuating voltage is referred to as “noise voltage”), and a malfunction occurs in an LSI to which the output signal is input.

In general, a method of reducing the noise voltage by suppressing a peak current at the time of charging and discharging a load is employed. The peak current is reduced by slowing the rising / rising operation of the output circuit.

FIG. 4 shows a conventional output circuit. This is described in Japanese Patent Application No. 63-97630.
51 is a pMOS transistor, 52 is an nMOS transistor, and their drains are commonly connected to a signal output terminal 53, and these constitute a CMOS output stage. 5
Reference numeral 4 denotes an inversion drive circuit for driving the transistor 51, which is composed of a pMOS transistor 55 and nMOS transistors 56 to 58. Reference numeral 59 denotes an inversion drive circuit for driving the transistor 52.
It is composed of transistors 60 to 62 and an nMOS transistor 63. 64 and 65 are delay circuits for delaying the input signal by Δt. 66 is an input terminal for the voltage Vin;
7 is a power supply terminal of the voltage VDD1, and 68 is a power supply terminal of the voltage VDD2.

In this circuit, when the voltage Vin at the input terminal 66 goes high, the transistor 56 of the inversion drive circuit 54 turns on, and the gate voltage Vg of the output transistor 51 is turned on.
51 falls to Vg51 = Vth57. Vth57 is a threshold voltage of the transistor 57.

The driving force of the output transistor 51 is weakened by setting the gate voltage Vg51 to a value higher than the ground potential GND, and the transition time when raising the voltage of the output terminal 53 to a high level is gradual. become. Therefore, the peak value of the charging current from the power supply voltage VDD1 is also reduced.

Thereafter, when the time Δt has elapsed, the output voltage of the delay circuit 64 goes high, and the inversion drive circuit 54
Transistor 58 is turned on, and both ends of the transistor 57 are short-circuited.
g51 drops to the ground potential GND, and the output transistor 5
The driving force for holding the drain voltage (output voltage) 1 at the power supply voltage VDD1 is equivalent to a circuit that does not use the inversion drive circuit 54 or the delay circuit 64.

On the other hand, when the voltage Vin at the input terminal 66 goes low, the transistor 61 of the inversion drive circuit 59 turns on, and the gate voltage Vg52 of the output transistor 52 rises to Vg52 = VDD2-Vth60. Vth60 is a threshold voltage of the transistor 60.

The driving force of the output transistor 52 is weakened by setting the gate voltage Vg52 to a value lower than the power supply voltage VDD2, so that the transition time when the voltage of the output terminal 53 is lowered to a low level is gradual. become. Therefore, the peak value of the discharge current to the ground GND is also reduced.

Thereafter, when the time Δt has elapsed, the output voltage of the delay circuit 65 goes low, and the inversion drive circuit 59
Is turned on to short-circuit both ends of the transistor 60, so that the gate voltage V
g52 rises to the voltage VDD2 and the output transistor 52
The driving force for holding the drain voltage (output voltage) of the transistor at the potential of the ground GND is equivalent to that of the circuit that does not use the inversion drive circuit 59 or the delay circuit 65.

As described above, when a high-level voltage is input to the input terminal 66, the voltage at the output terminal 53 rises slowly in two steps, and when a low-level signal is input to the input terminal 66, the output terminal 53 increases. The falling of the voltage of
By performing the operation slowly and stepwise, the peak current at the time of charging and discharging is suppressed to reduce the noise voltage.

That is, in the above-described circuit, the delay circuits 64 and 65 having a fixed delay time Δt are provided, during which time the driving force of the output transistors 51 and 52 is reduced to reduce the peak current flowing through the power supply line or ground. I am holding it down.

[0014]

However, the delay circuit 6
Nos. 4 and 65 cannot obtain a sufficient delay time if they are composed of a small number of gates of about two to four stages.
There is a problem that the peak current cannot be reduced as much as the noise voltage appearing at the output terminal 53 is reduced. Conversely, if the delay circuit is configured with multiple stages of gates, the above problem can be solved, but another problem occurs in that the power consumption and area of the output circuit are significantly increased.

The present invention has been made in view of the above points, and an object of the present invention is to provide a low-noise type transistor that requires a small number of transistors and can exhibit a sufficient noise voltage reduction effect. The purpose is to provide an output circuit.

[0016]

According to a first aspect of the present invention, there is provided a CMOS output stage comprising a first CMOS circuit comprising a pMOS transistor and an nMOS transistor whose drains are commonly connected to an output terminal, and the potential of an input terminal is low. First means for fixing the gate potential of the pMOS transistor to a first intermediate potential that intermediately drives the pMOS transistor and gradually raises the potential of the output terminal when the level changes from a high level to a high level; , The high level potential of the output terminal is fed back,
A second means for fixing the gate potential of the MOS transistor from the first intermediate potential to the low level; and n when the potential of the input terminal changes from the high level to the low level.
Third means for fixing the gate potential of the MOS transistor to a second intermediate potential for driving the nMOS transistor intermediately and gradually lowering the potential of the output terminal; A fourth means for fixing the gate potential of the nMOS transistor from the second intermediate potential to a high level,
It was constituted to have.

In a second aspect based on the first aspect, the first means includes a second CMOS circuit and the second CMOS circuit.
A first diode that raises a low-level output potential of the S circuit by a predetermined value from a normal low level,
The second means comprises a first transistor which is turned on by a low level potential of the output terminal to short-circuit both ends of the first diode, and wherein the third means comprises a third CMOS circuit and A second diode for lowering the high-level output potential of the third CMOS circuit by a predetermined value from a normal high level, and turning on the fourth means by the high-level potential of the output terminal. And a second transistor for short-circuiting both ends of the second diode.

[0018]

FIG. 1 is a circuit diagram showing a configuration of an output circuit according to an embodiment of the present invention. 11 is a pMOS transistor, 12 is an nMOS transistor, and their drains are commonly connected to a signal output terminal 13, and these constitute a CMOS output stage. 14 is a transistor 11
, And includes a pMOS transistor 15 and nMOS transistors 16 to 18. Reference numeral 19 denotes an inversion drive circuit for driving the transistor 12, and the pMOS transistors 20 to 2
2. It is composed of an nMOS transistor 23. 2
4 is a signal input terminal, 25 is a power supply terminal of the voltage VDD1, 2
Reference numeral 6 denotes a power supply terminal for the voltage VDD2.

In the inversion drive circuit 14, the transistors 15 and 17 constitute a CMOS circuit in which the transistor 16 is connected between their drains.
6 is when the output voltage of the CMOS circuit is at a low level.
Transistor 1 functions as a level shift diode for raising the potential to an intermediate potential higher than the normal low level.
Numeral 8 functions as feedback for turning on when the voltage Vout of the output terminal 13 is at a high level and short-circuiting the source and drain of the transistor 16. This feedback transistor 18
Has a channel width set to be narrower than that of other transistors, thereby reducing the overall area.

In the inversion driving circuit 19, the transistors 20 and 23 constitute a CMOS circuit in which the transistor 21 is connected between the drains thereof. When the output voltage of the CMOS circuit is at a high level, the transistor 21 operates normally. The transistor 22 functions as a diode for level shift that lowers the voltage to an intermediate potential lower than the high level of the transistor 21. The transistor 22 is turned on when the voltage Vout of the output terminal 13 is at the low level, and is used as a feedback for short-circuiting the source and drain of the transistor 21. Function. The overall area of the feedback transistor 22 is also reduced by setting the channel width of the feedback transistor 22 narrower than that of the other transistors.

Next, the operation will be described. (1) When the input voltage Vin applied to the input terminal 24 rises from GND to VDD2: At this time, the transistor 17 of the inversion drive circuit 14 is turned on, but the level shift transistor connected to its drain side 1
6 (the threshold voltage is Vth16), the gate voltage Vg11 of the output transistor 11 becomes an intermediate potential such as Vg11 = Vth16, and does not become the complete ground potential GND, so that the driving force of the output transistor 11 is low. The charging from the output terminal 13 to the load (not shown) is performed slowly.

As described above, when the output voltage Vout of the output terminal 13 increases and the output voltage Vout exceeds the threshold voltage (Vth18) of the transistor 18, the transistor 18 is turned on, and the output transistor 11 is turned on. The gate voltage Vg11 drops to the ground potential GND and is completely turned on. As a result, the output voltage Vout rises and is fixed at the power supply voltage VDD1. In the other inversion drive circuit 19, the transistor 23 is turned on and the output transistor 12 is turned off.

(2) Input voltage V applied to input terminal 24
When in falls from VDD2 to GND: At this time, the transistor 20 of the inversion drive circuit 19 is turned on, but the transistor 21 for level shift (the threshold voltage is Vth21) connected to its drain side. Since the gate voltage Vg12 of the output transistor 12 becomes an intermediate potential such as Vg12 = VDD2−Vth21 and does not become complete VDD2, the driving force of the output transistor 12 is kept low.
Discharge from the load to the output terminal 13 is performed slowly.

As described above, when the output voltage Vout of the output terminal 13 falls and the output voltage Vout falls below the threshold voltage (Vth22) of the transistor 22, the transistor 22 turns on and the output transistor 12 The gate voltage Vg12 rises to the power supply potential VDD2, and is completely turned on. As a result, the output voltage V
out falls and is fixed to the ground potential GND. In the other inversion drive circuit 14, the transistor 15 is turned on and the output transistor 11 is turned off.

As described above, in the output circuit of this embodiment, the rise / fall time of the output voltage can be made slower without providing a delay circuit, and the noise voltage can be reduced. FIG. 2 shows waveforms of the above operation.

FIG. 3 shows a CMOS circuit for driving a load connected to the output terminal with a capacitance of 15 pF.
The peak current flowing from the power supply VDD1 of the output stage and the current consumed by the power supply VDD2 of the inversion drive circuit are shown. This figure 3
Now, the output circuit of the present invention shown in FIG.
A first conventional output circuit (not shown) without noise countermeasures, in which each drive circuit for an OS transistor and an nMOS transistor is composed of two inverters, and a second low-noise type circuit shown in FIG. The conventional output circuit is compared.

According to the output circuit of the present invention, the peak current value can be reduced by about 30% or more as compared with the first conventional output circuit, and the second conventional output circuit is provided with low noise countermeasures. , The peak current can be reduced by about 20%. Moreover, as is clear from the comparison between the circuit configurations of FIGS. 1 and 4, the output circuit of the present invention has a smaller number of transistors (10/18) than the second conventional output circuit (the inverter 64 and the inverter 64). 65 was calculated on the assumption that the number of transistors was two.) As a result, the current consumption of the output circuit (power supply V
DD2) can be reduced by about 20%. In the second conventional output circuit, the peak current value can be reduced to the same extent as the output circuit of the present invention by increasing the number of gate stages of the delay circuits 64 and 65 to increase the delay. In the method, current consumption increases.

Although the output circuit alone has been described above, it goes without saying that a bidirectional circuit, a tri-state buffer, and the like including such an output circuit can be configured by the same technical idea.

[0029]

As described above, according to the present invention, the gate of the transistor in the CMOS output stage is driven in two stages by using the second and fourth means for feeding back the output signal.
In addition to reducing the peak current of the output circuit and the noise voltage, there is a great advantage that the number of transistors can be reduced and the current consumption can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an output circuit according to one embodiment of the present invention.

FIG. 2 is a signal waveform diagram when the output circuit of FIG. 1 operates.

FIG. 3 is an explanatory diagram of a characteristic comparison.

FIG. 4 is a circuit diagram of a conventional output circuit.

[Explanation of symbols]

11, 12: output transistors constituting a CMOS output stage, 13: output terminal, 14: inversion drive circuit, 15, 1
7: transistor constituting second CMOS circuit, 1
6: a transistor forming a first diode for level shift, 18: a transistor for feedback, 19: an inversion drive circuit, 20, 23: a transistor for forming a third CMOS circuit, 21: a second for level shift , 22: a feedback transistor.

Claims (2)

[Claims] A pM having a drain commonly connected to an output terminal.
A CMOS output stage comprising a first CMOS circuit comprising an OS transistor and an nMOS transistor; and when the potential of the input terminal changes from a low level to a high level, the gate potential of the pMOS transistor is set to an intermediate value between the pMOS transistor and A first means for driving and fixing the potential of the output terminal to a first intermediate potential that gradually rises, and a high-level potential of the output terminal being fed back, thereby setting the gate potential of the pMOS transistor to the first potential. 1
A second means for fixing the potential of the nMOS transistor to a low level from an intermediate potential of the nMOS transistor when the potential of the input terminal transits from a high level to a low level; A third means for fixing the potential of the terminal to a second intermediate potential that gradually falls, and a low-level potential of the output terminal being fed back, so that the gate potential of the nMOS transistor is reduced to the second potential.
A fourth means for fixing the intermediate potential to a high level from the intermediate potential of the output circuit. 2. The output circuit according to claim 1, wherein said first means comprises a second CMOS circuit and said second C circuit.
A first diode that raises a low-level output potential of the MOS circuit by a predetermined value from a normal low level, wherein the second means is turned on by a low-level potential of the output terminal, and A first transistor for short-circuiting both ends of the diode, wherein the third means includes a third CMOS circuit and the third C
A second diode for lowering a high-level output potential of the MOS circuit by a predetermined value from a normal high level, wherein the fourth means is turned on by a high-level potential of the output terminal, and An output circuit, comprising: a second transistor for short-circuiting both ends of the diode.