JPH10242472A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain both high speed operation and low power consumption by defining the difference of threshold in an on/off state and the threshold itself through the heavily doped region and the lightly doped region, having a heavily doped region formed beneath a channel and a lightly doped region formed at the channel part. SOLUTION: In both NMOS transistor T1a and PMOS transistor T2a, the part far below a channel is doped heavily in order to increase the difference between ON and OFF thresholds while the part immediately under the channel is doped lightly in order to lower the turn ON threshold. In a left side NMOS transistor T1a, double structure of a central thin part 5 and a thinner outer part 5a is employed in an LDD region in order to reduce the junction capacity with respect to the substrate and the difference of threshold is increased by depositing a thick gate oxide. Since turn ON threshold can be decreased along with the difference of threshold, the junction capacitance is also decreased and high speed operation can be realized while reducing power consumption.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a semiconductor device. More specifically, the present invention relates to a semiconductor device having a dual gate transistor.

[0002]

2. Description of the Related Art With the development of LSIs for use in media devices, it has become increasingly important to develop LSIs for portable devices which have a higher processing capability and can be operated for a long time with a battery.

In order to extend the use time of portable information equipment, which is expected to increase rapidly in the future, the LSI
It is important to reduce the power consumption without reducing the operation speed. The power consumption of the LSI is proportional to the square of the power supply voltage. Therefore, the most effective way to reduce power consumption is to reduce the operating voltage of the LSI. For low-voltage operation, it is necessary to keep a threshold voltage as a voltage necessary for turning on a transistor low. However, if the threshold voltage is too low, there is a problem that a leakage current due to a sub-threshold leak increases. For this reason,
Conventionally, the threshold voltage has to be set higher,
Operating voltage could only be reduced to about 1V.

In order to solve this problem, the substrate potential control S
OI technology has been proposed (Reference 1: T. Fuse et a
l, "A 0.5V SOI CMSO Pass-Gate Logic," ISSCC Digest o
f Technical Papers, pp.88-89, Feb., 1996.). More specifically, in general, a transistor has a property that the threshold voltage decreases as the substrate potential increases and increases as the substrate potential decreases. Utilizing this property, a substrate potential control SOI technology for separating a substrate for each transistor and controlling a voltage has been proposed. As a result, the threshold voltage of each transistor, which was conventionally constant, can be dynamically controlled. As a result, when the transistor is to be turned on, the threshold voltage is lowered to about 0 V to operate the circuit at high speed, and when the transistor is to be cut off, the threshold voltage is increased to about 0.2 V to sufficiently effectively leak. The current is cut off. As a result, it has become possible to provide a device that can realize the same high-speed operation as the conventional device with a low power supply voltage of about 0.5 V.

However, the conventional design method using this technique has a problem that the specifications cannot be satisfied for any of the N-channel transistor and the P-channel transistor. This will be described in more detail with reference to FIGS.

FIGS. 5 and 6 show a gate length of 0.25 μm,
This assumes a dual-gate CMOS transistor having an OI film thickness of 0.1 μm.

FIG. 5 is a well-known dual-gate CMOS transistor based on the SOI technology, and therefore detailed description is omitted.
1. The right side is the PMOS transistor T2. More specifically, an SOI layer is formed on a Si substrate 1 via an SiO ₂ layer 2,
That is, an element formation layer including the semiconductor layers of the P-type region and the N-type region is formed. This layer includes element isolation layers 3, 3,
Are divided into a plurality of element forming regions. The left side in the figure is a P-type region, and the right side is an N-type region. NMOS and PMOS transistors T1, T1,
T2 is formed. Focusing on the transistor T1, the surface portion of the semiconductor layer sandwiched between the element isolation regions 3 and 3 is used as a channel, and has source / drain layers 4 and 4 made of N ⁺ on both sides of the channel. Have LDD layers 5 and 5 of N ⁻ . In addition, a high-concentration impurity region 6 is commonly provided in the channel layer. On the surface side of such a semiconductor layer, a gate oxide film 8 is formed.
, A gate 9 as an N ⁺ silicon gate is formed. The thickness t of the gate oxide film 8 is about 20 angstroms. LDD side walls 10, 1 on both sides of these
0 is arranged. The above configuration is the same for the PMOS transistor T2 except for the difference in conductivity type.

FIG. 6A shows a profile immediately below the channel of the NMOS transistor T1. Generally, to dynamically control the threshold value, the difference ΔV _T (= | V _TON ) between the threshold value when the transistor is turned on (V _TON ) and the threshold value when the transistor is turned off (V _TOFF ) is used. -V
_TOFF |) is desirably as large as possible, such as 0.2-0.3V. This characteristic does not need to be considered in a conventional transistor that does not need to dynamically control the threshold. As shown in FIG. 6A, in order to increase the difference ΔV _T between the threshold values, the deep region 6 below the channel is changed to a dense impurity region (5 × 10 ¹⁷ cm ⁻³ :()).
Then, the boron concentration on the surface is also 4 × 10 ¹⁷ cm ⁻³ ()
And the off-side threshold V _TOFF is 0.5V
As described above, the ON-side threshold value V _TON is also close to 0.5 V, and the transistor does not operate at high speed even at the time of ON. On the other hand, in order to operate the transistor at a high speed when it is turned on, the threshold value V _TOFF on the off side is set to 0.1 to 0.2V.
The surface concentration of boron is 4 × 10 ¹⁶ cm
^-3 (), the density of the deep region 6 becomes 5 × 10 ¹⁶
cm ⁻³ (), which is too thin, and the threshold difference ΔV _T becomes 0.1 V or less, which makes it impossible to reduce the leakage current at the time of off.

In other words, in the conventional NMOS transistor, the specification of the NMOS transistor is such that the threshold difference ΔV _T = 0.2 to 0.3 V and the threshold value V _TON = 0.1 to 0.2 V at the time of ON. There was a problem that I was not satisfied.
The above problem is caused not only by the NMOS transistor T1 but also by the P
This is a problem common to the MOS transistor T2.

Further, if the impurity concentration in the deep region below the channel is made higher than that of the conventional one in order to dynamically control the threshold value, another new problem occurs in the NMOS transistor. .

The problem will be described with reference to an impurity profile immediately below LDDN ^- 10 shown in FIG. The density of the dark region 6 under the channel is set to 5 × 10 ¹⁷ cm ⁻³
(), The surface concentration is 4 × 10 ¹⁷ cm
^-3 (), which is the n ^- layer (LDDN ^- 5)
The high concentration is also obtained at the joint portion in contact with. As a result, this has a large junction capacitance at a junction that has not been taken into consideration in a conventional transistor that does not dynamically control the threshold value, and causes a new problem of suppressing high-speed operation.

[0012]

As described above, as described above,
The NMOS and PMOS transistors in the conventional semiconductor device must simultaneously satisfy the two conditions of increasing the threshold difference ΔV _T between the ON and OFF states and simultaneously decreasing the threshold value V _TON during the ON state. It was difficult in practice.

The present invention has been made in view of the above, and an object of the present invention is to consider dynamically controlling a threshold value.
In a semiconductor device having a dual-gate transistor in which a channel is to be formed on the surface, it is possible to achieve both high-speed operation and low power consumption by solving the above problems.

[0014]

According to a first aspect of the present invention, there is provided a semiconductor device comprising: an NMOS;
The transistor and the PMOS transistor are formed as dual gate transistors, and these NMSO
And each of the PMOS transistors have a high concentration region formed below the channel by doping with impurities,
A low-concentration region formed in the channel portion by counter-doping of impurities, wherein the high-concentration and low-concentration regions define the difference between the thresholds at ON and OFF and the threshold itself. Is done.

According to a second semiconductor device of the present invention, in the first semiconductor device, the NMOS transistor has source / drain regions at both ends of a channel, respectively.
Each of the pair of source / drain regions has an LDD region extending inward so as to oppose each other along the channel. Each of the LDD regions has a double structure, and has a junction depth on the center side. And a second region with a shallow junction and a low impurity concentration.

According to a third aspect of the present invention, in the first or second semiconductor device, the NMOS and the PMO are provided.
The gate insulating film included in each of the S transistors is configured to have a maximum applied electric field strength of 2 MV / cm or less.

According to a fourth aspect of the present invention, there is provided a semiconductor device comprising:
In any one of the third semiconductor devices, an SOI substrate is used as the semiconductor substrate to separate the NMOS and PMOS transistors.

A fifth semiconductor device according to the present invention comprises
In any one of the fourth semiconductor devices, the gate length of each of the NMOS and PMOS transistors may be 0.2 to 0.2.
0.3 μm, the gate insulating film thickness is 50 to 80 Å, the SOI film thickness is around 0.1 μm,
The high concentration region in the NMOS transistor is B
Alternatively, the counter doping is performed by BF _{2 with} a concentration of about 5 × 10 ¹⁷ cm ⁻³ , and the first and second regions of the LDD region are formed by As and P. It is configured as

According to a sixth aspect of the present invention, there is provided a semiconductor device comprising:
In any one of the fifth semiconductor devices, a gate length of the NMOS and PMOS transistors is 0.05 to
0.1 μm, the gate insulating film thickness is 30 to 35 Å, the SOI film thickness is around 0.1 μm,
The high concentration region in the NMOS transistor is B
Alternatively, the counter doping is performed by BF _{2 with} a concentration of about 2 × 10 ¹⁸ cm ⁻³ , and the first and second regions of the LDD region are formed by As and P. It is configured as

According to a seventh aspect of the present invention, there is provided a semiconductor device comprising:
In any one of the third semiconductor devices, a bulk type substrate is used as the semiconductor device to separate the NMOS and PMS transistors.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Prior to the description of the embodiments of the present invention, the outline of the present invention will be described as follows.

In the present invention, the threshold difference Δ
By separately performing ion implantation for increasing V _T and ion implantation for lowering threshold V _T , it is possible to optimize each of them. The junction capacity with the substrate is reduced by adopting a double structure in which the side is dark and the outside is thin, and the threshold is increased by making the gate insulating film thicker than that of the conventional system having a fixed threshold. thereby achieving an increase in the difference ΔV _T. This can increase the and threshold difference [Delta] V _T of lowering the threshold at the time of off, the junction capacitance can be reduced, it is obtained by enabling compatibility speed operation and low power consumption.

FIG. 1 is a sectional view showing a first embodiment of the present invention.

In this embodiment, the power supply voltage is 0.5 V
(0.8 V or less), gate length 0.25 (0.2-0.
3) A semiconductor device having a thickness of 50 μm and a gate insulating film of 50 to 80 Å is assumed. This device is intended to obtain a transistor having a longer gate length for a lower power supply voltage than a conventional transistor which does not dynamically control the threshold voltage.

In this embodiment, a CMOS having a dual gate structure and an SOI film having a thickness of 0.1 μm is formed similarly to the conventional one.
An SOI transistor is used. The gate insulating film 8
The thickness t of a is 50 to 80 angstroms as described above, the conventional 0.5 V operation, and the gate length is about 0.05 μm.
m about 20 Å of the transistor (Reference 2: B. Davari "CMOS Technology scaling
0.1μm and beyond "IEDM 96 Digest of Tech. Papers
(pp. 555-559.), not to increase the conductance gm, but to realize high-speed performance by increasing the threshold difference ΔV _T between ON and OFF. is there. The maximum electric field intensity applied to this gate insulating film is 2 MV / cm or less. Also,
In the present embodiment, in order to increase as much as possible the difference [Delta] V _T threshold, NMOS and PMOS transistors T1
In both a and T2a, the surface channel method is used.

As described above, the semiconductor device of FIG.
Similar to the semiconductor device of FIG. 5, it is a dual gate type using SOI. One of the differences from the device of FIG.
In the OS transistor T1a, the LDD region has a double structure of a thin portion (5) on the center side and a thinner portion (5A) on the outside, so that a high-speed operation in a semiconductor device that dynamically controls a threshold value is achieved. This is to achieve compatibility between operation and low power consumption, and has one feature here. Another difference is that NMOS
In any of the transistor T1a and the PMOS transistor T2a, the portion far below the channel is made sufficiently dense to increase the threshold difference between ON and OFF, and the portion directly below the channel is lowered to lower the threshold V _TON at which the transistor turns ON. In addition, it is sufficiently thin, which also has one feature. Other parts, that is, the NMOS transistor T
1A other part and right side PMOS transistor T2a
5 is not so different from that of FIG. 5. Therefore, the following description will be made focusing on the left side NMOS transistor T1A.

The method of manufacturing the NMOS transistor T1A is substantially the same as that of the conventional SOI type transistor, so that the detailed description is omitted, but it is simply as follows.

By ion implantation into a region sandwiched between the pair of device isolation regions 3 and 3, a region far below the channel portion is formed.
A P-type sufficiently dense high concentration region 6 is formed.

Next, As or the like is counter-implanted immediately below the channel in order to make the surface portion, that is, the channel portion, have a sufficiently low concentration.

Thereafter, a gate oxide film layer and an N ⁺ polysilicon gate layer are formed in the same manner as in the prior art, and a gate oxide film 8 and an N ⁺ polysilicon gate 9 are formed by etching.

[0031] Then, ion implantation (or diffusion) and thin by heat treatment first LDDN ^- forming a layer 5 ^- dark entered layers 5a and therein the second LDDN.

Thereafter, an insulating film is entirely deposited and etched to form LDD side walls 10, 10 and ion implantation is performed using these side walls 10, 10 as a mask, and N ⁺ source / drain layers 4 are formed by heat treatment. , 4 are formed.

The NMOS transistor T1a of the present embodiment
Is simply configured as above, but below
A more detailed description will be given focusing on the characteristic portions of the present invention with reference to the profile diagrams of FIGS. FIG. 2A is a profile diagram of the transistor T1a just below the channel, and FIG.
It is a profile figure under DDN- ¹ area (5, 5A).

In this embodiment, as described above, NM
Threshold difference ΔV required for OS transistor T1a
_T = 0.2 to 0.3 V, threshold value V _TON = 0.
In order to realize 1 to 0.2 V, a counter implanter of As is newly introduced just below the channel. By this arrangement it is adopted, to increase the difference [Delta] V _T threshold, the ion implantation of B or BF ₂ ^2, deep in the channel portion, 5 × 10 ¹⁷ cm ^-3 (Fig. 2 (A) ( a)) while achieving a boron concentration region 6A which is sufficiently high, the surface is set to 4 × 10 ¹⁶ cm ^-3 ((b) in FIG. 2A) to lower the threshold V _TON at the time of ON. It was possible to obtain a light concentration region. That is, FIG.
In (A), the dashed line is 5 × 1 well below the channel.
The profile of B (or BF ₂ ) implanted to obtain a high concentration of 0 ¹⁷ cm ^-3 is shown, and the dashed line indicates that the region immediately below the channel is implanted to obtain a thin concentration of 4 × 10 ^-6 cm ^-3 . The profile of As-implanted As is shown, and the thick solid line shows the resultant composite profile obtained as a result. The use of B (or BF ₂ ) and As to obtain an impurity profile as shown in FIG. 2A is the same for the PMOS transistor T2a on the right side of FIG.

Next, the NMSO transistor T1a of FIG.
A profile by ion implantation (or diffusion) for forming the LDD regions 5 and 5A having the double structure described above will be described.

[0036] As previously mentioned, LDDN ^- in order to reduce the large junction capacitance beneath, LDDN ^- 5 with As as in the conventional to make dense the surface concentration 5 × 10 ¹⁹ cm ^-3, and the junction In addition to being implanted so that the depth becomes shallow, prior to this, P is introduced so as to have a slightly thinner surface concentration of 1 × 10 ¹⁸ cm ^-3 and a deeper junction.
^- make a 5A. As a result, the impurity concentration at the junction can be considerably reduced as compared with the conventional one, whereby the junction capacitance can be significantly reduced, and a high-speed operation which cannot be realized in the conventional example can be realized for the first time.

A second embodiment of the present invention is shown in FIG.
FIG. 4 shows the impurity profile.

In the second embodiment, the power supply voltage is 0.5 V
(0.6 V or less) and a transistor having a gate length of 0.05 to 0.1 μm. In the present embodiment, a dual gate structure is adopted as in the conventional example.
It is applied to a 1 μm thick CMOS SOI transistor.

Conventional S without dynamically controlling the threshold voltage
In the OI transistor, in order to maximize the features of the SOI transistor, when the gate length is scaled, the SOI film thickness is reduced to 40 Å or less. However, when the threshold is dynamically controlled, it is inherently desirable to increase the body film thickness (SOI film thickness) so that the threshold can be controlled by the body voltage. Therefore, in this embodiment, the SOI film thickness is increased to 0.1 μm. Thickness is also desirable from the viewpoint of reducing the resistance in the body. On the other hand, the thickness of the gate insulating film is increased to 30 to 35 angstroms, which is about 20 angstroms, which is the thickness of the conventional case where the threshold value is not dynamically controlled, so that the conductance gm is increased. Rather, an attempt is made to realize high-speed performance by increasing the threshold difference ΔV _T between ON and OFF. Also, the threshold difference ΔV
_In order to make _T as large as possible, NMOS and PMO
The surface channel method is used in each of the S transistors T1b and T2b.

In this embodiment, the NMOS transistor T
1b required on / off threshold difference ΔV _T = 0.
In order to realize 2 to 0.3 V and V _TON = 0.1 to 0.2 V, a counter implanter of As is newly introduced just below the channel similarly to the first embodiment. Thereby,
To increase the difference [Delta] V _T threshold, B or B
The F ₂ ² deep in the depth direction of the channel portion, 2 × 10
^A sufficiently high boron concentration of ¹⁸ cm ^-3 can be realized, and the surface has a surface area of 2 × 10 ¹⁷ c in order to lower the ON threshold voltage V _TON.
A sufficiently low concentration of m ^-3 can be realized.

FIGS. 4A and 4B show profiles associated with the implantation of each impurity described above. FIG.
As in (A) and (B), (A) shows the profile just below the channel, and (B) shows the profile just below the LDDN ^- region. It can be seen from the profile of FIG. 4 that in the second embodiment, the concentration below the channel is higher than that in the first embodiment. this is,
In the second embodiment, the thickness t of the gate insulating film 8b
No. 1 by 30 to 50 angstroms.

The process described above is based on the above-described NMOS.
PMOS transistor T as well as transistor T1b
2b.

On the other hand, LDDN ^- in order to reduce the large junction capacitance beneath, similarly to the first embodiment, LDDN ^-
The surface concentration of 5 × 10 ¹⁹ cm ⁻³ by the conventional As is not only high and the bonding depth is shallow, but also the surface concentration by P is newly slightly reduced to 4 × 10 ¹⁸ cm ⁻³ and the bonding depth is deep. Introduce implantation. As a result, the impurity concentration at the junction can be considerably reduced as compared with the conventional one. For this reason, the junction capacitance can be significantly reduced. As a result, high-speed operation, which could not be realized in the conventional example, has become possible for the first time.

The embodiment of the present invention is not limited to the above two examples. The present invention uses ST instead of SOI structure.
It is also possible to apply to a triple well type bulk substrate using I separation. Further, other ion species of the same conductivity type may be used as the implanted impurity ions instead of B (boron). The same applies to As (arsenic) and P (phosphorus). Further, it is possible to use further optimized values for the gate length, the power supply voltage impurity concentration, the gate insulating film thickness, and the SOI film thickness. Within such a range, various modifications can be made without departing from the spirit of the present patent.

According to the present invention, both low power consumption and high speed can be achieved for the first time. For example, the power supply voltage is 0.5
V, compared with the case where the present invention is applied to an LSI having a gate length of 0.25 μm.
The on-state drain current can be made to flow about 10 times with the PMOS and the PMOS. As a result, it is possible to improve the operation characteristics by about 5 times or more without increasing the power consumption as compared with the conventional technology.

[0046]

According to the present invention, counter doping is employed for ion doping to form a high concentration region below the channel, so that a high concentration region can be formed below the channel and a low concentration region can be formed on the channel surface. Can form
As a result, the threshold difference between ON and OFF can be increased, and further power consumption can be reduced.
In addition, the threshold value itself can be reduced by the counter doping on the surface, the power consumption can be reduced by lowering the voltage, and the speed can be increased by flowing a large current due to the thick gate oxide film. And SO
The adoption of the I-transistor structure and the double LDD structure makes it possible to reduce the parasitic capacitance and increase the speed. In addition, the dual-gate CMOS structure makes the NMOS transistor
Both MOS transistors are surface channel type and can flow a large current due to high conductance, which can also increase the speed. For example, even for a high frequency signal of 200 to 500 MHz, a low power supply operation type and low power consumption can be achieved. The product can be provided as a device that operates at a high speed.

[Brief description of the drawings]

FIG. 1 is a sectional view of an apparatus according to a first embodiment of the present invention.

FIG. 2 shows impurity profiles below the NMOS channel and below the LDDN ⁻ in the device of FIG. 1;

FIG. 3 is a sectional view of an apparatus according to a second embodiment of the present invention.

FIG. 4 shows impurity profiles below the NMOS channel and below the LDDN ⁻ in the device of FIG. 3;

FIG. 5 is a cross-sectional view of a device using a conventional SOI dual gate transistor.

FIG. 6 shows the device below FIG.
DN ^- lower impurity profile.

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Mamoru Terauchi 1 Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Prefecture Inside the Toshiba R & D Center (72) Inventor Tomoaki Shino Komukai, Sai-ku, Kawasaki-shi, Kanagawa Toshiba 1 Inside Toshiba R & D Center

Claims (7)

[Claims] 1. A semiconductor device comprising: a semiconductor substrate;
A MOS transistor and a PMOS transistor are formed as dual gate transistors,
Each of the MSO and PMOS transistors has a high-concentration region formed below the channel by doping with impurities and a low-concentration region formed in the channel portion by counter-doping of impurities. A semiconductor device in which a difference between a threshold value at the time of on / off and a threshold value itself is defined by a region. 2. The NMOS transistor has a source / drain region at both ends of a channel, and each of the pair of source / drain regions has an LDD region extending inward so as to be opposed along the channel. Each LDD region is configured as a double structure,
2. The semiconductor device according to claim 1, further comprising a first region having a shallow junction depth and a high impurity concentration on the center side and a second region having a deep junction depth and a low impurity concentration on the outer side. 3. Semiconductor device. 3. The semiconductor device according to claim 1, wherein the gate insulating films of the NMOS and PMOS transistors have an applied maximum electric field strength of 2 MV / cm or less. 4. An SOI substrate is used as said semiconductor substrate to separate said NMOS and PMOS transistors.
The semiconductor device according to claim 1. 5. The NMOS and PMOS transistors have a gate length of 0.2 to 0.3 μm, a gate insulating film thickness of 50 to 80 Å, an SOI film thickness of about 0.1 μm, The high concentration area is B
Alternatively, the counter doping is performed by BF _{2 with} a concentration of about 5 × 10 ¹⁷ cm ⁻³ , and the first and second regions of the LDD region are formed by As and P. The semiconductor device according to claim 1, wherein: 6. The NMOS and PMOS transistors have a gate length of 0.05 to 0.1 μm, a gate insulating film thickness of 30 to 35 Å, an SOI film thickness of about 0.1 μm, The high concentration area is B
Alternatively, the counter doping is performed by BF _{2 with} a concentration of about 2 × 10 ¹⁸ cm ⁻³ , and the first and second regions of the LDD region are formed by As and P. The semiconductor device according to claim 1, wherein: 7. The semiconductor device according to claim 1, wherein a bulk-type substrate is used as said semiconductor device for separating said NMOS and PMOS transistors.