JPH10240616A - Microcomputer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To extend the entire memory space to be more than (n-th power of 2) bytes in the case of being provided with (n) address buses and to make a user able to develop software without being conscious of a bank. SOLUTION: This microcomputer 1 incorporates a CPUa 2, a CPUb 2, a CPUc 4, a CPUd 5 and a swap control circuit 9 for controlling the execution order of the respective CPUs 2-5. In this case, by program bank address selection signals 11 outputted from the swap control circuit 9 corresponding to the CPU to perform execution and address signals from the selected CPU, the memory space in a ROM 7 to be accessed is decided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a microcomputer having n internal address buses, and can expand the entire memory space to 2 @ n bytes or more without increasing the bus width of instruction fetch addresses. It relates to a microcomputer.

[0002]

2. Description of the Related Art In recent years, as the functions and performance of devices have become higher and the processing speed has increased, the program memory area, that is, the ROM space, mounted on a microcomputer for controlling devices has been required to have a larger capacity. ing. However, a central processing unit (hereinafter referred to as a CPU) having n address bus widths cannot access beyond the ROM space of 2 n bytes.

Conventionally, there is a bank switching method as a method of accessing a ROM space exceeding 2 n bytes. This method will be described below with reference to FIG. In the following example, a CPU having 16 address bus widths will be described as an example.

Reference numeral 31 denotes a CPU having an address bus width of 16 bits. The CPU 31 is connected to an internal bus 32 composed of a 16-bit address bus and an 8-bit data bus. 33 is R
OM. A bank switching control circuit 34 is connected between the ROM 33 and the internal bus 32. A bank switching control signal 35 is output from the bank switching control circuit 34 and is input to the ROM 33. Also, internal bus 32
And the bank switching control signal 35 are connected to an external memory expansion interface bus 36. These are installed on the microcomputer 30.

In the bank switching method, the ROM space is increased to 16
It is divided into the maximum value that can be accessed by the bit address bus, that is, 64 kbytes, and this is used as one bank. And ROM beyond 64K bytes
When accessing the space, the bank switching control signal 35
By acting as an address bus for the 17th bit and above,
Access to a ROM space of more than 64 Kbytes is realized.

[0006]

However, in the above-mentioned conventional configuration, since the control of bank switching is performed by software, when a ROM space of more than 64 Kbytes is used in software development, which bank is currently in use? You must always be aware of the bank, such as which bank to access. Therefore, there is a problem that it is difficult to easily develop software.

[0007] The present invention solves such a problem. For example, without considering a bank in software development, for example,
It is an object of the present invention to provide a microcomputer that can easily develop software exceeding a memory space of 64 Kbytes if the address bus is a CPU having a 16-bit width.

[0008]

In order to achieve the above object, a microcomputer according to the present invention comprises n internal address buses, a plurality of central processing units for fetching 2n byte or word instructions. And a storage device storing an instruction program, wherein the microcomputer has a built-in swap control circuit for controlling the execution order of the plurality of central processing units. By combining the output program bank address selection signal and an address signal sent for each central processing unit, an address space in the storage device accessed corresponding to each central processing unit is determined. And With this configuration, a function equivalent to the bank switching control conventionally performed by software is realized by hardware.

An instruction decoder for decoding an output of the central processing unit selected by the swap control circuit is provided, and a dedicated register group for writing an instruction program of the storage device is provided in each central processing unit. Further, at least the swap control circuit, the storage device, and the instruction decoder are shared by a plurality of central processing units by time division control. With such a configuration, a plurality of tasks can be processed in parallel.

Further, the program bank address selection signal output from the swap control circuit is automatically switched corresponding to each central processing unit.
With such a configuration, there is no need to be aware of the bank in software development.

[0011]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a microcomputer according to an embodiment of the present invention. 1 is a microcomputer, 2 is a CPUa, 3 is a CPUb, 4 is a CPUc, 5 is a CPUd, and CPUa2, CPUb
3, CPUc4 and CPUd5 have the same structure. In this embodiment, a CPU having 16 address bus widths will be described as an example.

CPUa2, CPUb3, CPUc4, C
PUd5 is connected by an internal bus 6 consisting of a 16-bit width address bus and an 8-bit width data bus. Further, the internal bus 6 has a ROM 7 as a storage device,
An external memory expansion interface bus 8 for externally expanding a memory is connected. 9 is CPU2-5
Is a swap control circuit for controlling the execution order of. From the swap control circuit 9, the CPU swap control signal 10
The PU and the program bank address selection signal 11 are output to the ROM 7 and the external memory expansion interface bus 8.

The operation of the one-chip microcomputer 1 composed of at least the above components will be described with reference to FIGS.

In FIG. 1, CPUa2, CPUb3, C
PUc4 and CPUd5 are CPs from the swap control circuit 9.
The execution order is controlled by the U swap control signal 10. For example, the execution order of each of the CPUs 2 to 5 is changed in a certain time cycle from CPUa2 → CPUb3 → CPUc4 → C
Control is performed so that PUd5 → CPUa2 is repeated.

Here, the program bank address selection signal 11 is sequentially and automatically switched according to the execution CPU. The program bank address selection signal 11 is a 2-bit data signal, which is “00” during execution of the CPUa2,
"01" during execution of CPUb3, "10" during execution of CPUc4, and "11" during execution of CPUd5.
Is output.

FIG. 2 is an explanatory diagram showing the relationship between each CPU and an accessible ROM space. An independent ROM space 12 having a capacity of 64 Kbytes is allocated to the CPUa2, and the ROM addresses of the ROM space 12 are # 0000 to # 0000.
FFFF. Similarly, the ROM space 13 allocated to the CPU b3 has ROM addresses # 10000 to # 1F.
FFF. Similarly, a ROM space 14 and a ROM space 15 are respectively allocated to the CPUs c4 and d5, and the ROM addresses are # 2000 to # 2F, respectively.
FFF, # 30000 to # 3FFFF.

Here, as shown in FIG.
5. Since the internal bus 6 has only an address bus width of 16 bits, the accessible ROM space is address # 00.
It is 64 kbytes from 00 to #FFFF. Here, program bank address selection signal 11 having 2-bit data
Separately from the internal bus 6, the CPU couples the program bank address selection signal 11 to the most significant 16-bit address signal sent each time, that is, the program bank address selection signal 11 is used as the most significant two bits of the ROM address. By using this, it can be used as address data having an address bus width of 18 bits.

As a result, if the address bus width is 18 bits, #
ROM addresses from 0000 to # 3FFFF can be accessed, and a 256-Kbyte ROM space can be used. As described above, the program bank address selection signal 11 is automatically and sequentially switched in accordance with the execution CPU, so that each of the CPUs 2 to 5 can access the allocated ROM space exceeding 64 Kbytes.

Further, the internal bus 6 and the program bank address selection signal 11 are connected to the external memory expansion interface bus 8, so that an external memory of up to 256 Kbytes can be connected outside the one-chip microcomputer 1.

FIG. 3 is a block diagram showing the execution control of the CPU, where 16, 17, 18, and 19 indicate instruction queues for prefetching instructions, 20, 21, 22, and 23 indicate instruction registers.
The 16 register 20 is unique to the CPUa2. Similarly,
The instruction queue 17 and the instruction register 21 are specific to the CPU b3, the instruction queue 18 and the instruction register 22 are specific to the CPU c4, and the instruction queue 19 and the instruction register 23 are specific to the CPU d5.

When the swap control circuit 9 selects CPUa2 as the CPU to execute, the instruction queue 16
7, the program stored in # 0000 to #FFFF is stored.
Various arithmetic processes are performed by Ua2, and the results are output as CPU control signals via the instruction decoder 24.
At this time, the C to be executed next in the swap control circuit 9 is
Select CPUb3 as PU. When the CPU b3 is selected, the program stored in # 10000 to # 1FFFF in the ROM 7 is stored in the instruction queue 17 of the CPU b3.
Various arithmetic processing is performed by 3, and the results are output as CPU control signals via the instruction decoder 24. At this time, the swap control circuit 9 selects the CPU c4 as the CPU to be executed next. Hereinafter, the swap control circuit 9
The same applies when CPUd5 is selected as PUc4.

As described above, according to the present embodiment, since a function equivalent to the conventional bank switching control by software is realized by hardware, it is possible to easily exceed 64 Kbytes without being aware of the bank in software development. Software development can be performed. By sharing hardware such as the ROM 7, the swap control circuit 9, and the instruction decoder 24 in a time-sharing manner for each CPU, a plurality of tasks can be processed in parallel.

In this embodiment, the number of CPUs is 4, the address bus width is 16 bits, and the data bus width is 8 bits. However, even if the CPU has any bus width and any number of CPUs, It goes without saying that the program bank address selection signal 11 operates as the upper bit of the address bus according to the number.

[0025]

As described above, the present invention provides a plurality of CPUs.
By providing a swap control circuit, a function equivalent to the conventional bank switching control is realized by hardware. For example, a CPU having an address bus width of 16 bits without being aware of banks in software development. Then, you can easily develop software of more than 64K bytes.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a microcomputer according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing a relationship of a ROM space corresponding to each CPU in FIG. 1;

FIG. 3 is a block diagram illustrating execution control of a CPU.

FIG. 4 is a block diagram showing a configuration of a conventional microcomputer.

[Explanation of symbols]

1, 30: microcomputer, 2: CPUa, 3
... CPUb, 4 ... CPUc, 5 ... CPUd, 6,
32: Internal bus, 7, 33: ROM, 8, 36: External memory expansion interface bus, 9: Swap control circuit, 10: CPU swap control signal, 11: Program bank address selection signal, 12, 13, 14, 15 ... ROM space, 16, 17, 18, 19 ... Instruction queue, 20, 21, 22, 23
... instruction register, 31 ... bank switching control circuit, 35
... Bank switching control signal.

Claims (3)

[Claims] 1. A microcomputer comprising: n internal address buses; a plurality of central processing units for retrieving instructions of 2 n bytes or words; and a storage device for storing instruction programs. A swap control circuit for controlling the execution order of the central processing units, a program bank address selection signal output from the swap control circuit corresponding to the central processing unit to be executed, and sent to each central processing unit. A microcomputer for determining an address space in the storage device to be accessed corresponding to each central processing unit by combining with an address signal. 2. An instruction decoder for decoding an output of a central processing unit selected by the swap control circuit, and a dedicated register group for writing an instruction program of the storage device is provided in each central processing unit. 2. The microcomputer according to claim 1, wherein at least the swap control circuit, the storage device, and the instruction decoder are shared with a plurality of central processing units by time division control. 3. The microcomputer according to claim 1, wherein the program bank address selection signal output from the swap control circuit is automatically switched corresponding to each central processing unit.