JPH1022837A - Data transfer device and method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the data transfer device and method, which can simplify the circuit constitution that is needed for change of the data transfer speed and also can suppress increase of the power consumption. SOLUTION: A parallel/serial converter 34 has plural shift registers 50A to 50H which operate, based on the operation clocks according to a 1st speed slower than the data transfer speed. The registers 50A to 50H collectively store the transfer data, in parallel to each other, as the bit width data according to the data transfer speed. A DS encoder consists of a data selector 35A and a strobe selector 35B. The selector 35A successively selects and outputs the outputs Q of registers 50A to 50H, in response to the data transfer speed. Then the selector 35B successively selects and outputs the outputs Q and the inverted outputs XQ registers 50A to 50H, in response to the data transfer speed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interface circuit in a data processing device, and more particularly, to an interface circuit in a data processing device compliant with IEEE1394 which is a serial interface standard.

In recent years, with the increase in multimedia, there has been a demand for an increase in the amount of data transferred between a personal computer and peripheral devices and an increase in transfer speed. Especially,
Digital video cameras that handle large amounts of audio and image data,
An interface circuit for connecting a peripheral device such as a digital VTR or a color page printer to a personal computer is one of serial interfaces, IEEE13.
94 have received attention.

[0003]

2. Description of the Related Art Conventionally, data transfer by the IEEE1394 protocol is a serial method.
Shows part of the protocol controller. The link layer processing circuit 71 is connected to a micro processing unit (MPU) via an MPU interface (not shown),
Inputs n-bit width parallel data and a header. The header is data that is added to the head of the data to constitute a packet, and is set with information on the destination of the packet, information on the number of bytes of the data constituting the packet, and the like.

The link layer processing circuit 71 includes a packet generation circuit 72 and a transfer FIFO memory (hereinafter, simply referred to as FIFO) 73. The operation clock CLK10 is supplied to the packet generation circuit 72 and the transfer FIFO 73. The packet generation circuit 72 outputs the operation clock CLK1
It operates based on 0, and generates a transmission packet consisting of n-bit data by adding a header to the beginning of the data supplied from the MPU and adding error correction code data to the end of the data. The packet generation circuit 72 outputs the generated transmission packet to the transfer FIFO 73. The transfer FIFO 73 has an operation clock CLK1.
Based on 0, writing or reading of n-bit width packet data is performed.

The physical layer processing circuit 74 is an IEEE1394 (not shown)
Peripheral devices (digital VTR, color page printer, or
Digital video camera). The physical layer processing circuit 74 inputs a transmission packet from the link layer processing circuit 71. The physical layer processing circuit 74 includes a parallel-serial converter 75 and a DS encoder 76. The operation clock CLK11 is supplied to the parallel-serial converter 75 and the DS encoder 76. Operation clock C
LK11 has a frequency which is n times as high as the operation clock CLK10. The parallel-serial converter 75 operates based on the operation clock CLK11, and converts parallel data having an n-bit width into serial data having a 1-bit width.

[0006] The DS encoder 76 has an operation clock CLK.
11, serial data DATA output from the parallel-serial converter 75 is sequentially input, and based on the data DATA, the strobe data S shown in FIG.
Generate TRB. The DS encoder 76 converts the serial data DATA and the strobe data STRB based on the operation clock CLK11 into an IEEE1394 interface and
Transfer to peripheral devices via IEEE1394 bus cable.

FIG. 14 shows details of the DS encoder 76. The DS encoder 76 includes two data flip-flops (hereinafter, referred to as DFFs) 77 and 78 and two exclusive OR circuits (EOR circuits) 79 and 80. D
The serial terminal DATA output from the parallel-serial converter 75 is input to the data terminal D of the FF 77, and the operation clock (transfer clock) CLK11 is input to the clock terminal CK. The DFF 77 latches the serial data DATA every time the rising edge of the operation clock CLK11 is input, and outputs the data from the output terminal Q as data DATA.

The EOR circuit 79 has a serial data DATA
And the data DATA of the DFF 77, and outputs a signal based on the levels of both signals. EOR circuit 80
Receives the output signal of the EOR circuit 79 and the inverted output signal of the DFF 78, and outputs a signal based on the level of both signals.

An output signal of the EOR circuit 80 is input to a data terminal D of the DFF 78, and an operation clock (transfer clock) CLK11 is input to a clock terminal CK. The DFF 78 latches the output signal of the EOR circuit 80 every time the rising edge of the operation clock CLK11 is input, and outputs it from the output terminal Q as strobe data STRB.

Therefore, as shown in FIG. 15, the level of the strobe data STRB coincides with the level of the data DATA alternately every one cycle of the operation clock CLK11, and alternately repeats.

Therefore, the peripheral device at the transmission destination can generate the signal DATA @ STRB having a frequency half that of the transfer clock CLK11 by taking the exclusive OR of the serial data DATA and the strobe data STRB. it can. That is, the transfer clock CLK11 in the transmission source device can be reproduced.

As described above, the operation clock CLK11 of the physical layer processing circuit 74 needs to have a frequency n times as high as the operation clock CLK10 of the link layer processing circuit 71.
High-speed operations are required for parallel-serial conversion and DS encoding. The IEEE1394 protocol defines a plurality of transfer speeds. To change the transfer speed, the frequency of the operation clock CLK10 is changed to change the packet generation circuit 72, the transfer FIFO 73, and the parallel-serial converter 75. , And the DS encoder 76 need to be operated.

[0013]

However, the conventional parallel-serial converter 75 has an operation clock CLK1.
Since the operation is performed based on the operation clock CLK11 having n times the frequency of 0, it is difficult to set the timing for switching the frequency of the operation clock CLK10, and there is a problem that a circuit therefor becomes complicated.

In the conventional IEEE1394 protocol controller, a link layer processing circuit 71 and a physical layer processing circuit 74
Changes the data transfer speed by changing the frequencies of the operation clocks CLK10 and CLK11. As the frequency of the operation clock CLK10 increases, the packet generation circuit 7 in the link layer processing circuit 71
2. The power consumption of the transfer FIFO 73 increases, and the power consumption of the parallel-serial converter 75 in the physical layer processing circuit 74 increases as the frequency of the operation clock CLK11 increases.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to simplify a circuit configuration for changing a data transfer rate and to suppress an increase in power consumption. To provide a data transfer device and a data transfer method.

[0016]

In order to achieve the above object, the present invention is directed to a parallel-serial for converting parallel transfer data into serial data in synchronization with a transfer clock corresponding to a transfer speed. A converter and a parallel
In a data transfer device including: an encoder that generates strobe data for reproducing a transfer clock based on serial data output from a serial converter and outputs the serial data and the strobe data, a parallel-serial converter includes: A plurality of registers operating at a first speed lower than the transfer speed and storing the transfer data in parallel as bit width data corresponding to the transfer speed collectively, wherein the plurality of registers are complementary output signals. And a data selector for sequentially selecting and outputting the outputs of the plurality of registers according to the transfer speed, and sequentially selecting and outputting the outputs and inverted outputs of the plurality of registers according to the transfer speed. A strobe selector.

According to a second aspect of the present invention, there is provided a transfer data storage means which operates at a second speed lower than the first speed and outputs transfer data as data having a bit width corresponding to the transfer speed. .

According to a third aspect of the present invention, the parallel data is converted into serial data in synchronization with a transfer clock, and strobe data for reproducing the transfer clock is generated based on the serial data. In the data transfer method that transfers data, the parallel data is converted into data having a bit width corresponding to the transfer speed, and the converted data is stored collectively in a plurality of registers operating at a speed lower than the transfer speed. Then, serial data and strobe data are transferred by sequentially selecting the output of each register based on the transfer speed.

(Operation) According to the first and third aspects of the present invention, even if the transfer speed for operating the parallel-serial converter at the first speed lower than the transfer speed is changed, the power consumption of the parallel-serial converter is changed. Is suppressed. Further, a circuit configuration for switching the transfer speed is simplified.

According to the second aspect of the present invention, the power consumption of the transfer data storage means increases even if the transfer speed for operating at the second speed lower than the first speed changes. Is suppressed.

[0021]

FIG. 1 is a block diagram showing an embodiment of the present invention.
This will be described with reference to FIG. FIG. 1 shows a system configuration based on IEEE1394 which is one of serial interfaces. In FIG. 1, a personal computer (hereinafter, referred to as a personal computer)
Digital V as external peripheral device
The TR 2, a color page printer 3 also as a peripheral device, and a digital video camera 4 as a peripheral device are connected to each other via an IEEE1394 bus cable (hereinafter, referred to as an IEEE1394 bus) 5. PC 1,
The digital VTR 2, the color page printer 3, and the digital video camera 4 each include an IEEE 1394 protocol controller for enabling data transfer conforming to IEEE 1394.

FIG. 2 is a block circuit showing the configuration of a system based on IEEE1394 provided in the personal computer 1. The personal computer 1 is a protocol controller for IEEE1394 (hereinafter, referred to as “protocol controller”).
IPC) 11, a microprocessing unit (hereinafter referred to as MPU) 12 as an internal device, and
Two first and second DMAs (DirectMe as internal devices)
mory Access) controllers 13 and 14.
The IPC 11, the MPU 12, the first DMA controller (hereinafter, referred to as a first DMAC) 13, and the second DMA controller (hereinafter, referred to as a second DMAC) 14 are each formed by a one-chip semiconductor integrated circuit device (LSI).

The IPC 11 comprises an MPU 12, a first DMAC
13 and the second DMAC 14. The IPC 11 is connected to the digital VTR 2, the color page printer 3, and the IEEE 1394 protocol controller (IPC) provided in the digital video camera 4 via the IEEE 1394 bus 5.

FIG. 3 shows a block circuit for explaining the IPC 11. The IPC 11 includes a physical layer processing circuit 20,
Link layer processing circuit 21, first and second transmission packet processing circuits 22a and 22b, first and second reception packet processing circuits 23a and 23b, and first to fourth storage memories (first to fourth FIFO) 24a including FIFOs. To 24d, control internal register 25, first and second 1394 interface (hereinafter, referred to as first and second 1394 I / F) 2
6a, 26b, an isochronous data transmission interface (hereinafter, referred to as Isoc transmission I / F) 27a, an isochronous data reception interface (hereinafter, referred to as Isoc reception I / F) 28a, and an asynchronous data transmission interface (hereinafter, referred to as I / F) Asyn transmission I / F) 2
7b, an asynchronous data receiving interface (hereinafter referred to as Asyn receiving I / F) 28b, and an MP
A U interface (hereinafter, referred to as MPUI / F) 29 is provided.

The first 1394 I / F 26a includes the IE
A packet in the isochronous transfer (Isoc transfer) mode (hereinafter referred to as an Isoc packet) and an asynchronous transfer between the physical layer processing circuit 20 and the IPC of the digital VTR 2 are connected to the digital VTR 2 via the EE1394 bus 5. Exchanges packets in the (Asyn transfer) mode (hereinafter referred to as Asyn packets). The second one
The I / F 26b for 394 is connected to the color page printer 3 via the IEEE1394 bus 5, and is connected between the physical layer processing circuit 20 and the IPC of the color page printer 3.
Exchanges Isoc packets in the oc transfer mode and Asyn packets in the Asyn transfer mode.

The Isoc transmission I / F 27a is connected to the first DM
The first DAMC 13 is connected to the AC 13 and transfers the transfer data (Isoc packet) to be transmitted in the Isoc transfer mode to the first FIFO 24a. Isoc receiving I / F 28a is
Connected to the first DMAC 13 and a second FIFO 24b
Transfer data received in the Isoc transfer mode (Is
oc packet) to the first DMAC 13.

The Asyn transmission I / F 27b is connected to the second DM
The transfer data (Asyn packet) to be transmitted in the Asyn transfer mode from the second DMAC 14 is connected to the AC 14 and passed to the third FIFO 24c. The Asyn receiving I / F 28b is
Connected to the second DMAC 14 and a fourth FIFO 24d
Transfer data received in Asyn transfer mode (As
yn packet 32) to the second DMAC 14. MPUI
/ F29 is connected to the MPU 12, and the MPU 12
And various kinds of command data and the like between the control internal register 25 and the control internal register 25.

The physical layer processing circuit 20 includes first and second 1
The Isoc packet and the Asyn packet received by the 394 I / Fs 26 a and 26 b are input and output to the link layer processing circuit 21. The physical layer processing circuit 20 is a link layer processing circuit 2
From step 1, an Isoc packet for transmission and an Asyn packet for transmission are input. Then, the physical layer processing circuit 20 converts the Isoc packet and the Asyn packet into the first or second 1394 I / O packet.
Digital VT of the transmission destination via the / Fs 26a and 26b
R2, the color page printer 3, or the digital video camera 4.

The link layer processing circuit 21 receives the Isoc packet and the Asyn packet received from the physical layer processing circuit 20. The link layer processing circuit 21 includes an Isoc packet and an Asyn packet.
It is determined whether the packet is addressed to itself (the personal computer 1) based on the contents of the header added to the head of the packet. If the packet is addressed to itself, the Isoc packet and Asyn packet are sent to the first or second received packet processing circuit 23a, 23b.

The link layer processing circuit 21 determines whether the received packet addressed to itself is an Isoc packet or an Asyn packet based on the contents of the header added to the packet. Then, the link layer processing circuit 21 determines that the received packet
In the case of a packet, the Isoc packet is supplied to the first received packet processing circuit 23a. If the received packet is an Asyn packet, the link layer processing circuit 21 supplies the Asyn packet to the second received packet processing circuit 23b.

The link layer processing circuit 21 is supplied with an Isoc packet for transmission from the first transmission packet processing circuit 22a and an Asyn packet for transmission from the second transmission packet processing circuit 22b.

The first received packet processing circuit 23a is supplied with the Isoc packet received from the link layer processing circuit 21. The first received packet processing circuit 23a receives the received Isoc
Perform error correction check processing on the packet. That is, in the present embodiment, processing for error correction is separately performed on the header and data of the Isoc packet.
The first received packet processing circuit 23a performs the error correction processing
An Isoc packet is supplied to the second FIFO 24b.

The second FIFO 24b inputs a reliable Isoc packet that has been subjected to error correction processing, and receives the next Isoc packet in the order of input.
Output to the Isoc receiving I / F 28a. I / F for Isoc reception
28a passes the Isoc packet including the header and the data to the first DMAC 13 as described above.

The second received packet processing circuit 23b is supplied with the Asyn packet received from the link layer processing circuit 21. The second received packet processing circuit 23b receives the received Asyn
Perform error correction check processing on the packet. Then, in the same manner as described above, the process for error correction is separately performed on the header and data of the Asyn packet. Second
The reception packet processing circuit 23b outputs the error-corrected Asyn
The packet is supplied to the fourth FIFO 24d.

The fourth FIFO 24d inputs a reliable Asyn packet that has been subjected to error correction processing,
Output to the Asyn receiving I / F 28b. Asyn receiving I / F
28b passes the Asyn packet including the header and the data to the second DMAC 14 as described above.

The first FIFO 24a stores the Isoc transmission I
A transmission Isoc packet for transmission in the Isoc transfer mode from the first DMAC 13 via the / F27a is input, and the first transmission packet processing circuit 22a is input in the order of input.
To supply. The first transmission packet processing circuit 22a generates an error correction code for the sequentially input Isoc packets. That is, in the present embodiment, processing for generating and adding an error correction code separately to the header and data of the Isoc packet is performed. First transmission packet processing circuit 22
a supplies the link layer processing circuit 21 with an Isoc packet in which an error correction code generated for each of the header and the Isoc data is added.

The third FIFO 24c stores the Asyn transmission I
A transmission Asyn packet for transmission in the Asyn transfer mode is input from the second DMAC 14 via the / F 27b, and the second transmission packet processing circuit 22b is input in the order of input.
To supply. The second transmission packet processing circuit 22b generates an error correction code for the sequentially input Asyn packets. Then, similarly to the above, a process of separately generating and adding an error correction code is performed for the header and data of the Asyn packet. Second transmission packet processing circuit 22b
Supplies the link layer processing circuit 21 with an Asyn packet in which the generated error correction code is added to the header and the Asyn data.

The control internal register 25 has an MPUI /
It is provided between F29 and the link processing circuit 21.
The control internal register 25 includes the MPU 12 and the IPC 11
And control data such as various commands performed between them are temporarily stored. The control data from the MPU 12 input via the MPU I / F 29 is transmitted to the link layer processing circuit 2
1 and the control operation for the transfer control process
Cause C11 to execute. Further, control data from the link layer processing circuit 21 is read out by the MPU 12 and causes the MPU 12 to execute a control operation for a transfer control process.

Next, the physical layer processing circuit 20 and the link layer processing circuit 21 will be described with reference to FIG. Physical layer processing circuit 2
0 includes a parallel-serial converter 34, a DS encoder 35, and a transfer rate control circuit 36.

The transfer rate control circuit 36 receives the internal clock CLK1 having a predetermined frequency (400 MHz in this embodiment) and also receives the transfer rate control signals SP1 and SP2. The IEEE1394 protocol defines three types of transfer speeds of 100 Mbps (megabits / second), 200 Mbps, and 400 Mbps. When the transfer speed control signal SP1 is at an active level, the transfer speed is 100 Mbps.
s, the transfer rate is 200 Mbps when the transfer rate control signal SP2 is at the active level, and the transfer rate is 400 Mbps when neither of the transfer rate control signals SP1 and SP2 is at the active level.

The transfer speed control circuit 36 operates according to the internal clock CL.
Operation clock CLK obtained by dividing the frequency of K1 by 1 / n
2 and an operation clock CLK3 obtained by dividing the frequency of the internal clock CLK1 by 1 / m. In this embodiment, the operation clock CLK2 is a signal obtained by dividing the frequency of the internal clock CLK1 by 1/32.
The operation clock CLK3 is a signal obtained by dividing the frequency of the internal clock CLK1 by ８.

As shown in FIG. 8, the transfer rate control circuit 36
Is an 8-bit cyclic counter 60 and a signal mask circuit 6
1 is provided. “10000111” is set as the initial value of the cyclic counter 60 when the transfer rate control signal SP1 is at the active level, and “10000” when the transfer rate control signal SP2 is at the active level.
001 ”is set, and the transfer rate control signals SP1, SP2
Are not active levels, "1000
0000 ”is set. The cyclic counter 60 sequentially shifts to the right each time a pulse of the internal clock CLK1 is input, and outputs output signals Q1 to Q8.

The signal mask circuit 61 includes a cyclic counter 60
And the transfer rate control signals SP1 and SP2. The signal mask circuit 61 selects selection signals S1 to S8 corresponding to the signals Q1 to Q8 based on the levels of the transfer speed control signals SP1 and SP2.
Is output. Transfer speed control signal SP1
Is at the active level, the signal mask circuit 61 masks the signals Q2 to Q4, Q6 to Q8, and
5 is output as the selection signals S1 and S5. When the transfer speed control signal SP2 is at the active level, the signal masking circuit 61 masks the signals Q2, Q4, Q6, and Q8, and switches the signals Q1, Q3, Q5, and Q7 to the selection signals S1 and S7.
3, S5 and S7 are output. Further, when neither of the transfer rate control signals SP1 and SP2 is at the active level, the signal mask circuit 61 outputs the signals Q1 to Q8 as selection signals S1 to S8.

The parallel-serial converter 34 is supplied with the operation clock CLK3 from the transfer speed control circuit 36 in the physical layer processing circuit 20, and also with the transfer speed control signals SP1 and SP2. 34 operates at a first speed lower than the transfer speed based on the operation clock CLK3.

As shown in FIG. 6, the parallel-serial converter 34 is composed of eight 4-bit shift registers 50.
A to 50H and selectors 51A to 51H. The operation clock CL is applied to each of the shift registers 50A to 50H.
When K3 is input, each of the shift registers 50A to 50H outputs an output signal Q and an inverted output signal XQ from the last register. The selectors 51A to 51H receive the output signals Q of the shift registers 50A to 50H and the inverted output signal XQ, and select either the output signal Q or the inverted output signal XQ based on the levels of the transfer speed control signals SP1 and SP2. Output.

As shown in FIG. 6, the DS encoder 35 comprises a data selector 35A and a strobe selector 35B. The data selector 35A includes switches 52A to 52H for inputting the output signals Q of the shift registers 50A to 50H of the parallel-serial converter 34, respectively.
And two buffers 53. Switches 52A to 52H
Are input with the selection signals S1 to S8, and the switches 52A to 52H are turned on when the corresponding selection signals S1 to S8 become H level, and the corresponding shift registers 50A to 50H
The output signal Q of 50H is output to the buffer 53. The buffer 53 outputs a signal input through the turned-on switches 52A to 52H as a data signal DATA.

The strobe selector 35B includes switches 54A to 54H for inputting the output signals of the selectors 51A to 51H of the parallel-serial converter 34, and one buffer 55. The selection signals S1 to S8 are also input to the switches 54A to 54H.
When the corresponding selection signals S1 to S8 attain the H level, the signals .about.54H turn on and output the output signals of the corresponding selectors 51A to 51H to the buffer 55. The buffer 55 outputs a signal input via the switches 54A to 54H that have been turned on, as a strobe data signal STRB.

The link layer processing circuit 21 includes a transfer FIFO 32 as transfer data storage means and a selector 33. The transmission FIFO 32 is supplied with a transmission packet composed of n-bit (32 bits in this embodiment) data from the first transmission packet processing circuit 22a. The transfer FIFO 32 is supplied with the operation clock CLK2 from the transfer speed control circuit 36 in the physical layer processing circuit 20, and also with the transfer speed control signals SP1 and SP2.
, The parallel-to-serial converter 34 operates at a second speed lower than the first speed, which is the operating speed of the converter.

As shown in FIG. 5, the transfer FIFO 32 comprises a RAM cell array 40, a write pointer 42 and a read pointer 43. Since the packet in the IEEE1394 protocol is in units of 32 bits, the RAM cell array 40 stores a plurality of storage areas 4 each having a 32-bit configuration.
1 is provided. Each storage area 41 is composed of four banks 40A, 40B, 40C and 40D in 8-bit units.

Therefore, when writing data to the RAM cell array 40, the write clock WCK (= CLK
2), the write pointer 42 is incremented by one address, and the four banks 40A, 40B, 40
The word lines C and 40D are activated at the same time, and data is written to each storage area 41 in 32-bit units.

The read pointer 43 is a bank pointer 44
It has. The read pointer 43 is supplied with the read clock RCK (= CLK2) and also with the transfer speed control signals SP1 and SP2.

The bank pointer 44 is a 2-bit counter. When the transfer speed control signal SP1 is at the active level, the bank pointer 44 reads the read clock RCK.
Every time (= CLK2) is input, 0-3 are counted,
When the counter value is 3, a carry signal is output. When the transfer speed control signal SP2 is at the active level, the bank pointer 44 repeatedly counts 0 and 2 each time the read clock RCK (= CLK2) is input, and outputs a carry signal when the counter value is 2. Transfer speed control signal S
If neither P1 nor SP2 is at the active level, the bank pointer 44 does not operate and always outputs a carry signal.

When the carry signal is output from the bank pointer 44, the read pointer 43 is incremented by one address every time the read clock RCK (= CLK2) is input.

Therefore, at the time of reading data from the RAM cell array 40, the word lines of the four banks 40A, 40B, 40C, and 40D are activated at the same time based on the read clock RCK. Data is read, but the transfer rate control signal SP
The number of lines output from the sense amplifier unit changes based on 1, SP2. That is, when the transfer speed control signal SP1 is at the active level, the data of the bank corresponding to the counter value of the bank pointer 44 is output to eight output terminals D0 to D7 among the output terminals D0 to D31. When the transfer speed control signal SP2 is at the active level, the data of the bank corresponding to the counter value of the bank pointer 44 is output to the eight output terminals D0 to D7, and the counter value of the bank pointer 44 is output to the output terminals D8 to D15. The data of the bank corresponding to the value obtained by adding 1 is output. If neither of the transfer speed control signals SP1 and SP2 is at the active level, the output terminals D0 to D7
The data of the bank 40A is output to the output terminals D8 to D15, the data of the bank 40C is output to the output terminals D16 to D23, and the data of the bank 40D is output to the output terminals D24 to D31. That is, assuming that the most significant bit of data is D0, at each transfer speed,
The portion where data exists from the upper bit and the bit width exceeds is 0.

The selector 33 receives data output from the transfer FIFO 32 and also receives transfer rate control signals SP1 and SP2. When the transfer speed control signal SP1 is at the active level, the selector 3
7 loads the data output from the output terminals D0, D2, D4, and D6 of the transfer FIFO 32 into the shift register 50A in parallel as shown in FIG. 7A, and outputs the output terminals D1, D3, D5, and D7. Is loaded in parallel into the shift register 50E.

When the transfer speed control signal SP2 is at the active level, the selector 33 outputs the output terminals D0, D4, D4 of the transfer FIFO 32 as shown in FIG.
8, the data output from D12
A, and the output terminals D1, D5, D9,
The data output from D13 is loaded in parallel into shift register 50C, and output terminals D2, D6, D10, D
14 are loaded in parallel into the shift register 50E, and output terminals D3, D7, D11, D1
5 is loaded in parallel into the shift register 50G.

When neither of the transfer speed control signals SP1 and SP2 is at the active level, the selector 33 outputs the data from the output terminals D0, D8, D16 and D24 of the transfer FIFO 32 as shown in FIG. The data is loaded in parallel to the shift register 50A, and the output terminal D
, D9, D17, and D25 are loaded in parallel into the shift register 50B, and the output terminal D
2, the data output from D10, D18, and D26 are loaded in parallel to the shift register 50C, and the output terminal D
3, the data output from D11, D19, and D27 are loaded in parallel into the shift register 50D. The selector 33 loads the data output from the output terminals D4, D12, D20, and D28 into the shift register 50E in parallel, and loads the data output from the output terminals D5, D13, D21, and D29 into the shift register 50F in parallel. Then, the data output from the output terminals D6, D14, D22, and D30 are loaded in parallel to the shift register 50G, and the data output from the output terminals D7, D15, D23, and D31 are loaded in parallel to the shift register 50H. .

Next, the transmission operation of the link layer processing circuit 21 and the physical layer processing circuit 20 in the IPC 11 configured as described above will be described with reference to FIGS. Now, the personal computer 1 is on the transmission side, and the transfer data (Isoc packet) to be transmitted in the Isoc transfer mode from the first DMAC 13 is
It is passed to the first transmission packet processing circuit 22a via the Isoc transmission I / F 27a and the first FIFO 24a. For the transmission Isoc packet, an error correction code is separately generated and added to the header and data of the Isoc packet by the first transmission packet processing circuit 22a. An Isoc packet obtained by adding the generated error correction code to the header and the Isoc data is supplied to the link layer processing circuit 21 and stored in the transfer FIFO 32.

At this time, it is assumed that the transfer speed control signal SP2 is at the active level and the transfer speed is 200 Mbps. Then, every time the read clock RCK is input, the banks 40A and 40B are transmitted from the transfer FIFO 32.
16 bits of data and 16 bits of banks 40C and 40D.
Bit data is output alternately. At this time, the selector 33 outputs the output terminals D0 and D0 of the transfer FIFO 32.
The data output from D4, D8, and D12 are loaded in parallel into the shift register 50A, and output terminals D1, D2
5, D9, and D13 are loaded in parallel to the shift register 50C, and output terminals D2 and D13.
6, D10 and D14 are loaded in parallel into the shift register 50E and output terminals D3 and D14.
The data output from 7, D11 and D15 is loaded in parallel into the shift register 50G.

Every time the operation clock CLK3 is input,
The data in the shift registers 50A, 50C, 50E, 50G is shifted. Since the transfer rate control signal SP2 is at the active level, the selectors 51A and 51E select and output the output signals Q of the shift registers 50A and 50E, respectively, and the selectors 51C and 51G output the inverted output signals XQ of the shift registers 50C and 51G, respectively. Select and output.

Since the transfer speed control signal SP2 is at the active level, the transfer speed control circuit 36
Only 1, S3, S5, and S7 are output. Selection signal S
As the signals 1, S3, S5, and S7 sequentially go to the H level, the switches 52A and 52 in the data selector 35A are switched.
C, 52E, and 52G are sequentially turned on, and output signals Q of the corresponding shift registers 50A, 50C, 50E, and 50G are output as data signals DATA via the buffer 53. On the other hand, as the selection signals S1, S3, S5, and S7 sequentially become H level, the switches 54A, 54C, 54E, and 54G in the strobe selector 35B are sequentially turned on, and the output signal Q of the shift register 50A and the output signal Q of the shift register 50C. Inverted output signal XQ, output signal Q of shift register 50E, inverted output signal XQ of shift register 50G
Is the strobe data signal STRB via the buffer 55.
Is output as That is, the shift registers 50A,
During the shift operation of 50C, 50E, and 50G,
A 4-bit data signal DA is output from the data selector 35A.
TA is output, and a 4-bit strobe data signal STRB is output from the strobe selector 35B.

It is assumed that the transfer speed control signal SP1 is at the active level and the transfer speed is 100 Mbps. Then, every time the read clock RCK is input, the banks 40A, 40B,
8-bit data of 40C and 40D are sequentially output.
At this time, the data output from the output terminals D0, D2, D6, and D8 of the transfer FIFO 32 by the selector 33 is loaded in parallel to the shift register 50A, and the data output from the output terminals D1, D3, D5, and D7 are shifted. The data is loaded into the register 50E in parallel.

Every time the operation clock CLK3 is input,
The data in the shift registers 50A and 50E is shifted. Since the transfer speed control signal SP1 is at the active level, the selector 51A selects and outputs the output signal Q of the shift register 50A, and the selector 51E selects and outputs the inverted output signal XQ of the shift register 50E.

Since the transfer speed control signal SP1 is at the active level, the transfer speed control circuit 36
Only S1 and S5 are output. As the selection signals S1 and S5 alternately go to the H level, the switches 52A and 52E in the data selector 35A are alternately turned on, and the output signals Q of the corresponding shift registers 50A and 50E are transmitted via the buffer 53 to the data signal DATA. Is output as On the other hand, as the selection signals S1 and S5 alternately go to the H level, the switch 54 in the strobe selector 35B
A and 54E are turned on alternately, and the output signal Q of the shift register 50A and the inverted output signal XQ of the shift register 50E are output as the strobe data signal STRB via the buffer 55. That is, the shift registers 50A, 5A
During the shift operation of 0E, the data selector 35
A outputs a 2-bit data signal DATA, and the strobe selector 35B outputs a 2-bit strobe data signal STRB.

Further, transfer rate control signals SP1 and SP2
Are not active levels and the transfer speed is 400
Mbps. Then, the read clock RCK
Is input from the transfer FIFO 32 to the bank 4
32-bit data of 0A to 40D is output. At this time, the data output from the output terminals D0, D8, D16, and D24 of the transfer FIFO 32 by the selector 33 are loaded in parallel to the shift register 50A, and the data output from the output terminals D1, D9, D17, and D25 are shifted. The data loaded in parallel to the register 50B, the data output from the output terminals D2, D10, D18, and D26 are loaded in parallel to the shift register 50C, and the data output from the output terminals D3, D11, D19, and D27 are transferred to the shift register 50D. Are loaded in parallel.

Every time the operation clock CLK3 is input,
The data in the shift registers 50A to 50H is shifted. Since neither of the transfer rate control signals SP1 and SP2 is at the active level, the selectors 51A, 51C, 51
E and 51G are shift registers 50A and 50C, respectively.
The output signals Q of 50E and 50G are selected and output, and the selectors 51B, 51D, 51F and 51H select and output inverted output signals XQ of the shift registers 50B, 50D, 50F and 50H, respectively. Transfer speed control signals SP1, S
Since none of P2 is at the active level, the transfer rate control circuit 36 outputs the selection signals S1 to S8.
As the selection signals S1 to S8 sequentially become H level, the switches 52A to 52H in the data selector 35A are sequentially turned on, and the output signals Q of the corresponding shift registers 50A to 50H are transmitted through the buffer 53 to the data signal DATA.
Is output as On the other hand, the selection signals S1 to S8 sequentially become H
The switches 54A to 54H in the strobe selector 35B are sequentially turned on as the level becomes higher, and the output signal Q of the shift register 50A, the inverted output signal XQ of the shift register 50B, the output signal Q of the shift register 50C, and the inverted of the shift register 50D. Output signal XQ, output signal Q of shift register 50E, inverted output signal XQ of shift register 50F, output signal Q of shift register 50G, and inverted output signal XQ of shift register 50H are output as strobe data signal STRB via buffer 55. You. That is, during the shift operation of shift registers 50A to 50H, 8-bit data signal DATA is output from data selector 35A, and 8-bit strobe data signal ST is output from strobe selector 35B.
RB is output.

The present embodiment is configured as described above, and has the following effects. (1) In the present embodiment, the parallel-serial converter 34 is composed of eight shift registers 50A to 50H and eight selectors 51A to 51H, and is output from the transfer FIFO 32 according to the data transfer speed. And the shift register 50A-
Data to be transferred was loaded by switching the number of 50H. Then, the transfer speed is switched by changing the speed at which the selection signals S1 to S8 output from the transfer speed control circuit 36 are switched. Therefore, the transfer FIFO 32 is operated based on the operating clock CLK2 having a frequency that is 1/32 of the frequency of the internal clock CLK1 corresponding to the maximum transfer rate, and the parallel-serial converter 34 is operated for eight minutes of the frequency of the internal clock CLK1. The operation is performed based on the operation clock CLK3 having the frequency of 1 and only the DS encoder 35 can be operated at the data transfer speed. Therefore, not only does the circuit configuration for switching the data transfer rate not become complicated, the power consumption of the transfer FIFO 32 and the parallel-serial converter 34 can be kept constant, and an increase in power consumption can be suppressed. .

The present invention can be arbitrarily changed and embodied as follows. (1) In the above embodiment, the parallel-serial converter 34
Is provided with eight shift registers 50A to 50H, but the number of shift registers may be arbitrarily changed.
In this case, the bit width of the parallel data output from the transfer FIFO 32 is changed by the parallel-serial converter 3.
4 may be changed according to the number of shift registers.

[0069]

As described in detail above, the present invention can simplify the circuit configuration for changing the data transfer rate and can suppress an increase in power consumption.

[Brief description of the drawings]

FIG. 1 is a system configuration diagram using an IEEE1394 bus according to an embodiment;

FIG. 2 is a block diagram for explaining a configuration inside a personal computer;

FIG. 3 is a block diagram for explaining a protocol controller for IEEE1394.

FIG. 4 is a block diagram showing a part of a link layer processing circuit and a physical layer processing circuit;

FIG. 5 is a block diagram showing a transfer FIFO.

FIG. 6 is a block diagram showing a parallel-serial converter and a DS encoder.

FIG. 7 is an explanatory diagram showing data loading to a parallel-serial converter.

FIG. 8 is a block diagram illustrating a transfer rate control unit.

FIG. 9 is a waveform chart showing processing of a DS encoder.

FIG. 10 is a time chart showing the timing of data transfer.

FIG. 11 is a time chart showing the timing of data transfer.

FIG. 12 is a time chart showing data transfer timing;

FIG. 13 is a block diagram showing a conventional link layer processing circuit and physical layer processing circuit.

FIG. 14 is a block diagram showing a conventional DS encoder.

FIG. 15 is a waveform chart showing processing of a conventional DS encoder.

[Explanation of symbols]

 32 transfer FIFO as transfer data storage means 34 parallel-serial converter 35 DS encoder 35A data selector 35B strobe selector 50A to 50H shift register

Claims (3)

[Claims] 1. A parallel-serial converter for converting parallel transfer data into serial data in synchronization with a transfer clock corresponding to a transfer speed, and transferring based on serial data output from the parallel-serial converter. A data transfer device comprising: an encoder that generates strobe data for reproducing a clock and outputs the serial data and the strobe data; wherein the parallel-serial converter operates at a first speed lower than a transfer speed And a plurality of registers for collectively storing the transfer data in parallel as bit width data corresponding to a transfer speed, wherein the plurality of registers output complementary output signals; and A data selector for sequentially selecting and outputting the outputs of a plurality of registers according to the transfer speed; A data transfer apparatus and a strobe selector for sequentially selecting and outputting in response an output and the inverted output of the plurality of registers in transfer speed. 2. The apparatus according to claim 1, further comprising a transfer data storage unit that operates at a second speed lower than the first speed and outputs the transfer data as data having a bit width corresponding to the transfer speed. A data transfer device according to claim 1. 3. Converting parallel data into serial data in synchronization with a transfer clock, generating strobe data for reproducing a transfer clock based on the serial data, and transferring the serial data and the strobe data. In the data transfer method, the parallel data is converted into data having a bit width corresponding to a transfer speed, and the converted data is stored collectively in a plurality of registers operating at a speed lower than the transfer speed. A data transfer method in which serial data and strobe data are transferred by sequentially selecting the outputs based on the transfer speed.