JPH1022808A - Signal transmission circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce power consumption of a signal transmission circuit by preventing the flow of a steady state current, despite the change in polarity of an output signal of an output circuit. SOLUTION: A signal transmission circuit is composed of an output circuit 1 and an input circuit 5 and is terminated to a power supply, via a terminating resistance. Then the circuit 5, composed of a MOS resistance 8 which functions as a terminating resistance, and a differential input circuit 6 which inputs the output signal of the circuit 1 and a reference signal and also outputs a switch signal to switch every MOS terminating resistance to the power supply side or the ground potential side, according to a power supply or ground potential level of the output signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a signal transmission circuit, and more particularly to a signal transmission circuit used as an input / output circuit for transmitting a signal at high speed.

[0002]

2. Description of the Related Art With the advance of LSI manufacturing technology, a high-performance microprocessor (Micro Processor Unit; hereinafter, simply referred to as MPU) whose operating frequency exceeds 100 MHz has been developed. This type of MPU is used in various information processing devices such as personal computers. When such an MPU that operates at a high speed is incorporated in the information processing device, the MPU and the memory are used to perform high-speed signal transmission. It is also necessary to increase the speed of the interface (input / output circuit) connected between them.

This interface is composed of an output circuit and an input circuit each composed of an LSI, and a TTL (Transistor Tran) adapted to a conventional 5 V power supply voltage.
Sistor Logic) has been widely adopted, but the operating frequency of this TTL is limited to approximately 50 MHz. This is because the signal amplitude increases with the use of the power supply voltage of 5V. For this reason, there is a demand for an interface that can operate at a lower power supply voltage.

From such a viewpoint, for example, “Journal of the Institute of Electronics, Information and Communication Engineers”, Vol. 76, no. 7, 1993 7
In each of P721 to P725, the output circuit (driver) is configured by an open-drain NMOS (N-channel MOS transistor), and the input circuit (receiver) is differentially supplied with a reference potential (Vref) of 0.8 V. GTL (Gunning Trans) composed of input amplifier
An interface consisting of the server Logic (ceiver Logic) is shown. In this interface, input / output terminals between the output circuit and the input circuit are terminated to a 1.2 V power supply (VTT) via a 50Ω termination resistor. This allows operation with a power supply voltage of 1.2V.

[0005] Alternatively, in this document, an output circuit is constituted by a push-pull circuit of two PMOSs and two NMOSs, and an input circuit is constituted by a differential input amplifier to which a reference potential of 1.5 V is applied. CTT (Center Tapp)
ed Termination) is also shown. In this interface, the input / output terminals are terminated to a 1.5V power supply via a 50Ω termination resistor. This interface is a circuit originally developed with an LSI having a power supply voltage of 3.3 V or 3.0 V, and terminated at an intermediate potential of 1.5 V. The change of the signal is on the output side, and the standard is VTT ± 0.4V. for that reason,
The power supply voltage must be at least 1.9 V or more, and therefore, it can be operated with the power supply voltage of 1.9 V or more.

Further, for example, "Nikkei Electronics", published by Nikkei BP, 1992.6.8 (no. 55)
6), P133 to P140 similarly show an interface composed of GTL or CTT.

As described above, by terminating the input / output terminals to a low power supply via the terminating resistor, reflection of signals is prevented, and an interface operable at a lower power supply voltage can be realized.

FIG. 5 shows, as an example, an interface composed of a GTL in which an output circuit is constituted by an NMOS push-pull circuit and an input circuit is constituted by a differential input amplifier.
1 shows a conventional example of a so-called terminal type NMOS push-pull input / output circuit. NMOS is preferably used because of its superior driving capability as compared with PMOS.

In the output circuit 1, a push-pull circuit is constituted by a pair of NMOS transistors (hereinafter simply referred to as NMOS) 2, 3. One NMOS 2 is connected to a 1.2V power supply (VTT). The inverter 4 is connected to the gate of the NMOS 3 on the other side (ground potential VSS side). The input circuit 5 includes a differential input circuit 6 to which a reference potential (Vref) of 0.8 V is applied and to which an output signal from the output circuit 1 is input. The input / output terminal is connected to a power supply (V
TT).

[0010]

In an interface of the type in which an input / output terminal is terminated to a power supply via a terminating resistor as in the prior art, when the output signal of the output circuit changes to the opposite polarity, the terminating resistor is switched from the power supply side. , A steady-state current flows toward the ground potential side of the output circuit, which causes a problem of increased power consumption.

That is, in FIG. 5, when the output signal of the output circuit 1 changes from the power supply level [H (high) level] to the ground potential level [L (low) level], the power supply (V
A steady current flows from the TT) side to the ground potential (VSS) side of the output circuit 1 via the terminating resistor 7 as indicated by an arrow. For this reason, power consumption increases.

It is an object of the present invention to provide a technique capable of reducing a power consumption by preventing a steady current from flowing even when the polarity of an output signal of an output circuit changes.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0014]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, typical ones are briefly described as follows.

(1) A signal transmission circuit according to the present invention is a signal transmission circuit composed of an output circuit and an input circuit and terminated to a power supply via a terminating resistor, wherein the input circuit operates as the terminating resistor. It includes a MOS resistor and a differential input circuit for switching the MOS resistor to a power supply side or a ground potential side.

(2) The signal transmission circuit according to the present invention is a signal transmission circuit composed of an output circuit and an input circuit and terminated to a power supply via a terminating resistor, wherein the input circuit operates as the terminating resistor. A differential resistor for inputting a MOS resistor, an output signal of the output circuit and a reference signal, and outputting a switching signal for switching the MOS resistor to a power supply side or a ground potential side depending on whether the output signal is a power supply level or a ground potential level, respectively; And an input circuit.

According to the above-mentioned means (1), the signal transmission circuit of the present invention comprises an output circuit and an input circuit, and the input circuit of the signal transmission circuit terminated to a power supply via a terminating resistor has the terminal It includes a MOS terminating resistor that operates as a resistor, and a differential input circuit that switches the MOS terminating resistor to a power supply side or a ground potential side. Thereby, when the output signal of the output circuit changes from the power supply level to the ground potential level, the level of the output signal of the output circuit and the level of the input signal of the input circuit become the same level. Therefore, even if the polarity of the output signal of the output circuit changes, it is possible to reduce the power consumption by preventing the steady current from flowing.

According to the above-mentioned means (2), the signal transmission circuit of the present invention comprises an output circuit and an input circuit, and the input circuit of the signal transmission circuit terminated to the power supply via a terminating resistor is provided with the terminal A switching signal for inputting a MOS resistor operating as a resistor, an output signal of the output circuit and a reference signal, and switching the MOS terminating resistor to a power supply side or a ground potential side, respectively, depending on whether the output signal is a power supply level or a ground potential level And a differential input circuit for outputting the same. Thereby, when the output signal of the output circuit changes from the power supply level to the ground potential level, the level of the output signal of the output circuit and the level of the input signal of the input circuit become the same level. Therefore, even if the polarity of the output signal of the output circuit changes, it is possible to reduce the power consumption by preventing the steady current from flowing.

Hereinafter, the present invention will be described in detail with reference to the drawings and embodiments.

In all the drawings for explaining the embodiments, parts having identical functions are given same symbols and their repeated explanation is omitted.

[0021]

FIG. 1 is a circuit diagram showing a signal transmission circuit according to an embodiment of the present invention.

The output circuit 1 of the signal transmission circuit, which is connected between the MPU and the memory and operates as an interface (input / output circuit), has a push-pull circuit composed of a pair of NMOSs 2 and 3, and one of the NMOSs 2 has A power supply (VTT) of 1.2 V is connected, and an inverter 4 is connected to the gate of the NMOS 3 on the other side (ground potential VSS side). The output circuit 1 has a power supply level (1.2 V; hereinafter, referred to as an H level) according to the GTL standard.
Or a ground potential level (approximately 0.4 V; hereinafter, referred to as L level), and the output signal has an amplitude of approximately 0.8 V (1.2 V to 0.4 V). Becomes In order to satisfy such a standard, the on-resistance of the NMOS 3 is designed to be 25Ω or less.

The input circuit 5 operates as a terminating resistor.
An OS resistor 8; a differential input circuit 6 for switching the MOS resistor 8 to a power supply side or a ground potential side;
2 is comprised. Here, the MOS resistance 8 is 1.2
N comprising an NMOS 9 connected to a power supply (VTT) of V and an NMOS 10 connected to an inverter 11 at a gate.
It is composed of a MOS push-pull circuit. The differential input circuit 6 receives the output signal of the output circuit 1 and has a first level (0.8 V) lower than the H level (1.2 V) of the output signal of the output circuit 1. The reference signal (Vref1) and the first level (0.8
V), two types of reference signals of a second reference signal (Vref2) having a second level (0.4 V) lower than V. Further, the delay circuit 12 performs timing adjustment when switching between the first and second reference signals based on the output signal of the differential input circuit 6.

The first level (0.8 V) of the first reference signal (Vref1) determines whether the output signal of the output circuit 1 is at the H level (1.2 V) or the L level (0.4 V). Threshold is set. Therefore, the threshold value is selected to be 0.8 V, which is an intermediate value between 1.2 V and 0.4 V. When the output signal is higher than 0.8 V, the threshold is set to the H level. The following cases are identified as L level.

The second level (0.4 V) of the second reference signal (Vref 2) falls to the H level or the L level when the output signal of the output circuit 1 drops to the ground potential (0 V) and rises from this level. Is set to a threshold value to identify Therefore, this threshold value is selected to be 0.4 V which is an intermediate value of the amplitude of 0.8 V, and the output signal becomes 0.4 V.
When the output signal is equal to or higher than V, it is identified as H level, and when the output signal is equal to or less than 0.4 V, it is identified as L level.

By setting the two types of reference signals Vref1 and Vref2 having different levels in this way, when the output signal changes, it can be determined whether the H level or the L level occurs without a time delay. Has become. That is, in the Fall direction in which the output signal changes from H level to L level, the first
Of the H level or the L level is determined by the reference signal Vref1, and in the rise (Rise) direction in which the output signal changes from the L level to the H level, whether the level is the H level or the L level is determined by the second reference signal Vref2. The identification is intended to be performed. As a result, it is possible to contribute to speeding up of signal transmission.

The differential input circuit 6 compares the output signal of the output circuit 1 with the first or second reference signal depending on whether the output signal of the output circuit 1 is at the H level or the L level. To a power supply side or a ground potential side. For example, when the output signal is at the H level, the differential input circuit 6 outputs the H level signal to the MO after comparing with the first reference signal Vref1.
The MOS resistor 8 is switched to the power supply side by outputting to the S resistor 8 and turning on the NMOS 9. On the other hand, when the output signal is at the L level, the differential input circuit 6 outputs the L level signal to the MOS resistor 8 after comparing with the first reference signal Vref1, and turns on the NMOS 10 to thereby turn the MOS resistor 8 on. To the ground potential side. First
Switching between the second reference signal Vref1 and the second reference signal Vref2 is performed by an output signal of the differential input circuit 6.

Next, the operation of the signal transmission circuit according to the embodiment of the present invention will be described.

(1) When output signal of output circuit is at H level As shown in FIG. 2, when an H level signal is input to the NMOS push-pull circuit constituting the output circuit 1, the NMOS
2 turns on and NMOS 3 turns off. As a result, the output circuit 1 outputs an H-level signal as shown at the timing t1 in FIG. This output signal is directly input to the input circuit 5.
Is input to Thus, the differential input circuit 6 compares the output signal with the first reference signal Vref1, and then outputs the H level signal to the MOS resistor 8 as a switching signal.

As a result, N constituting the MOS resistor 8
The NMOS 9 of the MOS push-pull circuit is turned on, and the NMO
Since S10 is turned off, the MOS resistor 8 is switched to the power supply side. Therefore, since the level of the output signal of the output circuit 1 and the level of the input signal of the input circuit 5 are the same H level, no steady current flows.

(2) When the output signal of the output circuit changes to L level As shown in FIG. 3, when the signal input to the NMOS push-pull circuit constituting the output circuit 1 changes from H level to L level, NMOS2 turns off and NMOS3 turns on. Accordingly, the output signal of the output circuit 1 changes in the fall direction, and a signal whose level decreases after the timing t2 in FIG. 4 is output. This output signal is directly input to the input circuit 5. The output signal is the timing t shown in FIG.
3 and then change to the L level, and at timing t4, 0.4 V
Down to As a result, the differential input circuit 6 compares the output signal with the first reference signal Vref1, and then outputs the L level signal to the MOS resistor 8 as a switching signal.

As a result, N constituting the MOS resistor 8
The NMOS 9 of the MOS push-pull circuit is turned off and the NMO
Since S10 is turned on, the MOS resistor 8 is connected to the ground potential VSS.
(0V) side. Therefore, since the level of the output signal of the output circuit 1 and the level of the input signal of the input circuit 5 are the same L level, no steady current flows.

At this time, the level of the output signal drops to 0 V at the timing t5 in FIG. 4 because the NMOS 10 drops to the ground potential. This output signal is directly input to the input circuit 5. Then, the output signal changes in the rise direction.

The output signal which rises at the timing t6 reaches 0.4 V at the timing t7. This allows
After comparing the output signal with the second reference signal Vref2, the differential input circuit 6 outputs the H level signal to the MOS resistor 8 as a switching signal.

As a result, N constituting the MOS resistor 8
The NMOS 9 of the MOS push-pull circuit is turned on, and the NMO
Since S10 is turned off, the MOS resistor 8 is switched to the power supply side. Therefore, since the level of the output signal of the output circuit 1 and the level of the input signal of the input circuit 5 are the same H level, no steady current flows.

The output signal level further increases and reaches 0.8 V at timing t8 and then reaches 1.2V power supply level at timing t9, but the output signal level of the output circuit 1 and the input signal 5 H which is the same as the level of the input signal
Since it is kept at the level, no steady current flows.

In such a series of operations, after the level of the output signal changes from H to L, the delay circuit 12
Switching from Vref1 to Vref2 is performed at the timing of t5, and after the level of the output signal changes from L to H,
A timing operation is performed such that switching from Vref2 to Vref1 is performed at the timing of t9.

As described above, the differential input circuit 6 of the input circuit 5
Types of reference signals Vre having different levels
f1 and Vref2 are set, and in the fall direction in which the output signal changes from the H level to the L level, whether the output signal changes from the L level to the H level is determined by the first reference signal Vref1. In the changing rise direction, the second reference signal Vr
By performing the discrimination between the H level and the L level based on ef2, the discrimination between the H level and the L level can be performed without a time delay when the output signal changes, so that the speed of signal transmission is increased. Will be able to do it.

According to the signal transmission circuit of the above embodiment, the following effects can be obtained.

(1) The input circuit 5 of the signal transmission circuit, which is composed of the output circuit 1 and the input circuit 5 and is terminated to the power supply via the terminating resistor, has the MOS resistor 8 operating as a terminating resistor, and the output of the output circuit 1 Signal and a reference signal, and each of the signals depends on whether the output signal is a power supply level or a ground potential level.
Since the differential circuit includes a differential input circuit that outputs a switching signal for switching the OS terminating resistor to the power supply side or the ground potential side, when the output signal of the output circuit changes from the power supply level to the ground potential level, the output circuit 1 And the level of the input signal of the input circuit 5 becomes the same level. Therefore, even if the polarity of the output signal of the output circuit changes, the steady current is prevented from flowing to reduce the power consumption. Becomes possible.

(2) A first reference signal Vref1 having a first level lower than the H level of the output signal of the output circuit 1 and a second reference signal Vref1 lower than the first level are supplied to the differential input circuit 6 of the input circuit 5. Since two types of reference signals, that is, the second reference signal Vref2 composed of levels, are input, it is possible to discriminate between the H level and the L level without a time delay when the output signal changes. Thus, the speed of signal transmission can be increased.

As described above, the invention made by the present inventor is:
Although specifically described based on the embodiment, the present invention
It is needless to say that the present invention is not limited to the above-described embodiment, but can be variously modified without departing from the scope of the invention.

For example, in the above-described embodiment, an example has been described in which two types of reference signals having different levels are input as the reference signals of the differential input circuit constituting the input circuit. However, if the signal transmission time does not matter so much. One type of reference signal may be input.

In the above description, the invention made mainly by the present inventor has been described by using the MPU which is the application field in which the background was used.
Although the description has been given of the case where the present invention is applied to an interface connected between a memory and a memory, the present invention can be applied to at least a condition that signal transmission is performed at high speed with low power consumption.

[0045]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

The input circuit of the signal transmission circuit, which is composed of an output circuit and an input circuit and is terminated to a power supply through a terminating resistor, receives a MOS resistor that operates as a terminating resistor, an output signal of the output circuit, and a reference signal. A differential input circuit for outputting a switching signal for switching the MOS terminating resistor to the power supply side or the ground potential side depending on whether the output signal is at the power supply level or the ground potential level. When the potential level changes, the level of the output signal of the output circuit and the level of the input signal of the input circuit become the same level. Thus, power consumption can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a signal transmission circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram illustrating an example of an operation of the signal transmission circuit according to the embodiment of the present invention.

FIG. 3 is a circuit diagram illustrating another example of the operation of the signal transmission circuit according to the embodiment of the present invention.

FIG. 4 is a timing chart of signal waveforms for explaining the operation of the signal transmission circuit according to the embodiment of the present invention.

FIG. 5 is a circuit diagram showing a signal transmission circuit according to a conventional example.

[Explanation of symbols]

1: output circuit, 2, 3: NMOS transistor, 4, 1
DESCRIPTION OF SYMBOLS 1 ... Inverter, 5 ... Input circuit, 6 ... Differential input circuit, 7
... Terminating resistance, 8 ... MOS resistance, 9, 10 ... NMOS transistor, 12 ... Delay circuit.

Claims (6)

[Claims] 1. A signal transmission circuit, comprising an output circuit and an input circuit, terminated to a power supply via a terminating resistor, wherein the input circuit includes a MOS resistor operating as the terminating resistor, and a power supply connected to the MOS resistor. And a differential input circuit for switching to a side or a ground potential side. 2. A signal transmission circuit comprising an output circuit and an input circuit and terminated to a power supply via a terminating resistor, wherein the input circuit includes a MOS resistor operating as the terminating resistor, and an output of the output circuit. A differential input circuit for inputting a signal and a reference signal, and outputting a switching signal for switching the MOS resistor to a power supply side or a ground potential side depending on whether the output signal is a power supply level or a ground potential level, respectively. Signal transmission circuit. 3. A differential input circuit according to claim 1, wherein said differential input circuit has a first level lower than a power supply level of an output signal of said output circuit.
3. The signal transmission circuit according to claim 2, wherein two types of reference signals are input: a first reference signal and a second reference signal having a second level lower than the first level. 4. 4. The first level and the second level are:
4. The signal transmission circuit according to claim 3, wherein the output signal of the output circuit is set to a threshold value for discriminating between a power supply level and a ground potential level. 5. The signal transmission circuit according to claim 1, wherein said output circuit comprises an NMOS push-pull circuit. 6. The MOS resistor according to claim 1, wherein said MOS resistor comprises an NMOS push-pull circuit.
The signal transmission circuit according to claim 1.