JP2011147194A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce power consumption of a semiconductor integrated circuit by reducing power consumption due to a signal line having a large load. <P>SOLUTION: A drive circuit DC21 for driving a signal line GL21 having a large load in response to an input signal S21 being a pulse signal of negative logic includes pMOS transistors TD21 and TD22. The pMOS transistor TD21 has a source and a drain connected to the signal line GL21 and a ground line VSS, respectively, and the gate thereof receives the input signal S21. The pMOS transistor TD22 has a source and a drain connected to a power line VDD and the signal line GL21, respectively, and the gate thereof receives an inverted signal of the input signal S21. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit, and more particularly to a technique for reducing power consumption of a semiconductor integrated circuit.

  Recently, portable electronic devices (such as mobile phones) driven by using batteries have become widespread. For semiconductor integrated circuits installed in these portable electronic devices, high-speed operation is required to enable higher functionality of electronic devices, and low power consumption is required to enable long-term use of batteries. There is a strong demand to be.

  In a semiconductor integrated circuit composed of a plurality of circuit blocks, the wiring length of inter-block signal lines (global signal lines) for transmitting signals between circuit blocks tends to increase. The increase is one of the major factors that reduce the performance (operation speed, power consumption, etc.) of the semiconductor integrated circuit. Therefore, development of a technique for improving the performance of a semiconductor integrated circuit having a signal line with a long wiring length is in progress. For example, Patent Document 1 discloses a technique for accelerating signal transmission through a signal line having a long wiring length and mitigating voltage fluctuation of a power supply line.

  Patent Document 2 discloses a technique for preventing a through current from flowing in a circuit connected to a data line even when the potential of the data line is equalized to an intermediate potential in advance in a semiconductor memory device.

JP-A-9-294063 Japanese Patent Laid-Open No. 9-190693

  Recently, of the power consumption of semiconductor integrated circuits, the proportion of power consumption due to long signal lines such as interblock signal lines (that is, signal lines with a large load) has increased. For this reason, in order to reduce the power consumption of the semiconductor integrated circuit, it is indispensable to reduce the power consumption due to the signal line having a large load.

  An object of the present invention is to reduce power consumption caused by a signal line having a large load and to realize low power consumption of a semiconductor integrated circuit.

  In one embodiment of the present invention, a semiconductor integrated circuit includes a signal line and a driver circuit that receives a negative logic pulse signal as an input signal and drives the signal line in accordance with the input signal. The drive circuit has a source connected to the signal line, a drain connected to the low power line, a gate receiving the input signal, a source connected to the high power line, and a drain connected to the signal line, A gate having a second p-type transistor for receiving an inverted signal of the input signal.

  In the first technique related to the present invention, the semiconductor integrated circuit includes a signal line and a drive circuit. The drive circuit drives the signal line according to the input signal. The drive circuit includes a first p-type transistor and a first n-type transistor. The source of the first p-type transistor is connected to the signal line. The drain of the first p-type transistor is connected to the low power supply line. The gate of the first p-type transistor receives an input signal. The source of the first n-type transistor is connected to the signal line. The drain of the first n-type transistor is connected to the high power supply line. The gate of the first n-type transistor receives an input signal.

  By configuring the drive circuit for driving the signal line to include the first p-type transistor and the second n-type transistor, the amplitude of the signal transmitted through the signal line can be set to the threshold voltage of the first p-type transistor from the potential of the low power supply line. The amplitude can be reduced from a potential higher by an absolute value to a potential lower by a threshold voltage of the first n-type transistor than a potential of the high power supply line. For this reason, the power consumption resulting from a signal line can be reduced. Therefore, when the load of the signal line driven by the drive circuit is large, it can greatly contribute to the reduction in power consumption of the semiconductor integrated circuit.

  In a preferred example of the first technique related to the present invention, the semiconductor integrated circuit includes a receiving circuit in addition to the signal line and the driving circuit. The receiving circuit sets the output signal to the potential of the low power supply line when the potential of the signal line is larger than the threshold value, and sets the output signal to the potential of the high power supply line when the potential of the signal line is smaller than the threshold value. The receiving circuit is configured with a cutoff circuit. The cutoff circuit cuts off the potential supply from the low power line and the high power line in response to the operation stop request.

  When it is requested to stop the operation of the receiving circuit, since the potential supply from the low power line and the high power line is cut off by the cutoff circuit in the receiving circuit, the signal transmitted through the signal line is set to the intermediate potential. It is possible to suppress the through current generated due to the above.

  In a preferred example of the first technique related to the present invention, the semiconductor integrated circuit includes a receiving circuit in addition to the signal line and the driving circuit. The receiving circuit sets the output signal to the potential of the low power supply line when the potential of the signal line is larger than the threshold value, and sets the output signal to the potential of the high power supply line when the potential of the signal line is smaller than the threshold value. The drive circuit includes a second n-type transistor, a second p-type transistor, a first switch circuit, and a second switch circuit in addition to the first p-type transistor and the first n-type transistor. The drain of the second n-type transistor is connected to the signal line. The gate of the second n-type transistor receives an inverted signal of the input signal. The drain of the second p-type transistor is connected to the signal line. The gate of the second p-type transistor receives an inverted signal of the input signal. The first switch circuit is provided between the source of the second n-type transistor and the low power supply line. The first switch circuit is turned on as the potential of the signal line exceeds the threshold value of the receiving circuit, and is turned off as the potential of the signal line falls below the threshold value of the receiving circuit. The second switch circuit is provided between the source of the second p-type transistor and the high power supply line. The second switch circuit is turned on as the potential of the signal line falls below the threshold value of the receiving circuit, and turned off as the potential of the signal line exceeds the threshold value of the receiving circuit.

  In the semiconductor integrated circuit having such a configuration, when the signal line is set to a potential lower than the potential of the high power supply line by the threshold voltage of the first n-type transistor, the first switch circuit is turned on and the second switch circuit is turned on. Is off. In this state, when a falling change of the input signal occurs, the second n-type transistor is turned on in addition to the first p-type transistor. Therefore, the time required for the falling change of the signal transmitted through the signal line is shortened. Then, as the potential of the signal line falls below the threshold value of the receiving circuit, the first switch circuit is turned off and the second switch circuit is turned on. When the signal line is set to a potential higher than the potential of the low power supply line by the absolute value of the threshold voltage of the first p-type transistor, the first switch circuit is turned off and the second switch circuit is turned on. In this state, when a rising change of the input signal occurs, the second p-type transistor is turned on in addition to the first n-type transistor. Therefore, the time required for the rise change of the signal transmitted through the signal line is shortened. Then, as the potential of the signal line exceeds the threshold value of the receiving circuit, the first switch circuit is turned on and the second switch circuit is turned off.

  As described above, the second n-type transistor is turned on in addition to the first p-type transistor when lowering the potential of the signal line, and the second p-type transistor is turned on in addition to the first n-type transistor when raising the potential of the signal line. The signal transmission through the signal line can be speeded up. The first switch circuit is turned off when the driving of the signal line by the second n-type transistor is unnecessary, and the second switch circuit is turned off when the driving of the signal line by the second p-type transistor is not needed. An excessive potential supply from the power supply line to the signal line can be avoided.

  In a preferred example of the first technology related to the present invention, the drive circuit includes a first p-type transistor, a first n-type transistor, a second n-type transistor, a second p-type transistor, a first switch circuit, and a second switch circuit, A detection circuit is provided. The detection circuit is provided to detect a change in the magnitude relationship between the potential of the signal line and the threshold value of the reception circuit, and has the same circuit configuration as the reception circuit. The first switch circuit turns on in response to a falling change in the output signal of the detection circuit, and turns off in response to a rise change in the output signal of the detection circuit. The second switch circuit is turned on in response to the rising change of the output signal of the detection circuit, and is turned off in response to the falling change of the output signal of the detection circuit.

  Since the detection circuit has the same circuit configuration as that of the reception circuit, a rise change and a fall change occur at substantially the same timing in the output signal of the detection circuit and the output signal of the reception circuit. For this reason, by controlling on / off of the first switch circuit and the second switch circuit with the output signal of the detection circuit, the first switch is immediately activated when the driving of the signal line by the second n-type transistor becomes unnecessary. The circuit can be turned off, and the second switch circuit can be turned off immediately when the driving of the signal line by the second p-type transistor becomes unnecessary. As a result, it is possible to reliably avoid excessive potential supply from the low power line and the high power line to the signal line.

  In the second technique related to the present invention, the semiconductor integrated circuit includes a signal line and a drive circuit. The drive circuit receives a negative logic pulse signal as an input signal, and drives the signal line in accordance with the input signal. The drive circuit includes a first p-type transistor and a second p-type transistor. The source of the first p-type transistor is connected to the signal line. The drain of the first p-type transistor is connected to the low power supply line. The gate of the first p-type transistor receives an input signal. The source of the second p-type transistor is connected to the high power supply line. The drain of the second p-type transistor is connected to the signal line. The gate of the second p-type transistor receives an inverted signal of the input signal.

  By configuring the driving circuit for driving the signal line to include the first p-type transistor and the second p-type transistor, the amplitude of the signal transmitted through the signal line is set to the threshold voltage of the first p-type transistor from the potential of the low power supply line. The amplitude can be reduced from the high potential by the absolute value to the potential of the high power supply line. For this reason, the power consumption resulting from a signal line can be reduced. Therefore, when the load of the signal line driven by the drive circuit is large, it can greatly contribute to the reduction in power consumption of the semiconductor integrated circuit.

  In a preferred example of the second technique related to the present invention, the semiconductor integrated circuit includes a receiving circuit in addition to the signal line and the driving circuit. The receiving circuit sets the output signal to the potential of the low power supply line when the potential of the signal line is larger than the threshold value, and sets the output signal to the potential of the high power supply line when the potential of the signal line is smaller than the threshold value. The drive circuit includes an n-type transistor and a switch circuit in addition to the first p-type transistor and the second p-type transistor. The drain of the n-type transistor is connected to the signal line. The gate of the n-type transistor receives an inverted signal of the input signal. The switch circuit is provided between the source of the n-type transistor and the low power supply line. The switch circuit is turned on as the potential of the signal line exceeds the threshold value of the receiving circuit, and turned off as the potential of the signal line falls below the threshold value of the receiving circuit.

  In the semiconductor integrated circuit having such a configuration, the switch circuit is turned on when the signal line is set to the potential of the high power supply line. In this state, when a falling change of the input signal occurs, the n-type transistor is turned on in addition to the first p-type transistor. Therefore, the time required for the falling change (activation) of the signal transmitted through the signal line is shortened. Then, as the potential of the signal line falls below the threshold value of the receiving circuit, the switch circuit is turned off. As described above, when the potential of the signal line is lowered, the n-type transistor is turned on in addition to the first p-type transistor, so that signal transmission through the signal line can be speeded up. Further, when the driving of the signal line by the n-type transistor becomes unnecessary, the switch circuit is turned off, so that an excessive potential supply from the low power line to the signal line can be avoided.

  In a preferred example of the second technology related to the present invention, the drive circuit includes a detection circuit in addition to the first p-type transistor, the second p-type transistor, the n-type transistor, and the switch circuit. The detection circuit is provided to detect a change in the magnitude relationship between the potential of the signal line and the threshold value of the reception circuit, and has the same circuit configuration as the reception circuit. The switch circuit is turned on in response to a falling change in the output signal of the detection circuit, and is turned off in response to a rise change in the output signal of the detection circuit.

  Since the detection circuit has the same circuit configuration as that of the reception circuit, a rise change and a fall change occur at almost the same timing in the output signal of the detection circuit and the output signal of the reception circuit. Therefore, by controlling on / off of the switch circuit with the output signal of the detection circuit, the switch circuit can be immediately turned off when the driving of the signal line by the n-type transistor becomes unnecessary. As a result, it is possible to reliably avoid an excessive potential supply from the low power supply line to the signal line.

  In the third technique related to the present invention, the semiconductor integrated circuit includes a positive phase side signal line, a negative phase side signal line, a positive phase side drive circuit, a negative phase side drive circuit, a positive phase side reception circuit, and a negative phase side reception circuit. And a state transition circuit. The positive phase side drive circuit receives a negative logic positive phase pulse signal as an input signal, and drives the positive phase side signal line in accordance with the input signal. The negative phase side drive circuit receives a negative logic negative phase pulse signal as an input signal, and drives the negative phase side signal line in accordance with the input signal. The positive phase side receiving circuit sets the output signal to the low power line potential when the positive phase signal line potential is greater than the threshold, and the output signal to the high power source when the positive phase signal line potential is less than the threshold. Set to line potential. The negative phase side receiving circuit sets the output signal to the low power line potential when the negative phase signal line potential is larger than the threshold, and the high phase power signal when the negative phase signal line potential is smaller than the threshold. Set to line potential. The state transition circuit transitions from the first operation state to the second operation state in response to the rising change of the output signal of the positive phase side receiving circuit, and the second state in response to the rising change of the output signal of the negative phase side receiving circuit. Transition from the operating state to the first operating state. The positive phase side driving circuit includes a positive phase side first p-type transistor and a positive phase side second p-type transistor. The source of the positive phase side first p-type transistor is connected to the positive phase side signal line. The drain of the positive-phase side first p-type transistor is connected to the low power line. The gate of the positive-phase side first p-type transistor receives an input signal (positive-phase pulse signal). The source of the positive phase side second p-type transistor is connected to the high power supply line. The drain of the positive phase side second p-type transistor is connected to the positive phase side signal line. The gate of the positive-phase side second p-type transistor receives an inverted signal of the input signal. The negative phase side drive circuit includes a negative phase side first p-type transistor and a negative phase side second p-type transistor. The source of the negative-phase side first p-type transistor is connected to the negative-phase side signal line. The drain of the negative-phase side first p-type transistor is connected to the low power line. The gate of the negative phase side first p-type transistor receives an input signal (negative phase pulse signal). The source of the negative-phase side second p-type transistor is connected to the high power supply line. The drain of the negative-phase side second p-type transistor is connected to the negative-phase side signal line. The gate of the negative-phase side second p-type transistor receives an inverted signal of the input signal.

  By configuring the positive phase side drive circuit for driving the positive phase side signal line with the positive phase side first p-type transistor and the positive phase side second p-type transistor, the amplitude of the signal transmitted by the positive phase side signal line can be reduced. The amplitude from the potential higher by the absolute value of the threshold voltage of the positive-phase side first p-type transistor than the potential of the low power supply line to the potential of the high power supply line can be reduced. Similarly, a signal transmitted by the negative phase side signal line is configured by configuring the negative phase side drive circuit for driving the negative phase side signal line with the negative phase side first p-type transistor and the negative phase side second p-type transistor. Can be reduced to an amplitude from a potential higher than the potential of the low power supply line by the absolute value of the threshold voltage of the negative-phase side first p-type transistor to the potential of the high power supply line. For this reason, the power consumption resulting from the positive phase side signal line and the negative phase side signal line can be reduced. Therefore, when the load on the positive phase side signal line driven by the positive phase side drive circuit and the negative phase side signal line driven by the negative phase side drive circuit is large, it can greatly contribute to the reduction in power consumption of the semiconductor integrated circuit.

  In a preferred example of the third technique related to the present invention, the positive phase side drive circuit includes a positive phase side n-type transistor and a positive phase side switch in addition to the positive phase side first p-type transistor and the positive phase side second p-type transistor. It is configured with a circuit. The drain of the positive phase side n-type transistor is connected to the positive phase side signal line. The gate of the positive phase side n-type transistor receives an inverted signal of the input signal (positive phase pulse signal). The positive phase side switch circuit is provided between the source of the positive phase side n-type transistor and the low power supply line. The positive phase side switch circuit turns on as the potential of the positive phase side signal line exceeds the threshold value of the positive phase side receiving circuit, and the potential of the positive phase side signal line falls below the threshold value of the positive phase side receiving circuit. Turn off with it. The negative phase side drive circuit includes a negative phase side n-type transistor and a negative phase side switch circuit in addition to the negative phase side first p-type transistor and the negative phase side second p-type transistor. The drain of the negative phase side n-type transistor is connected to the negative phase side signal line. The gate of the negative phase side n-type transistor receives an inverted signal of the input signal (negative phase pulse signal). The negative phase side switch circuit is provided between the source of the negative phase side n-type transistor and the low power supply line. The negative phase side switch circuit turns on as the potential of the negative phase side signal line exceeds the threshold value of the negative phase side receiving circuit, and the potential of the negative phase side signal line falls below the threshold value of the negative phase side receiving circuit. Turn off with it.

  In the semiconductor integrated circuit having such a configuration, when the positive phase side signal line is set to the potential of the high power supply line, the positive phase side switch circuit is turned on. In this state, when a falling change of the input signal of the positive phase side drive circuit occurs, the positive phase side n-type transistor is turned on in addition to the positive phase side first p-type transistor. Therefore, the time required for the falling change of the signal transmitted through the positive phase side signal line is shortened. Then, as the potential of the positive phase side signal line falls below the threshold value of the positive phase side receiving circuit, the positive phase side switch circuit is turned off. In this way, when the potential of the positive phase side signal line is lowered, the positive phase side n-type transistor is turned on in addition to the positive phase side first p-type transistor, so that the signal transmission through the positive phase side signal line can be speeded up. Further, since the positive phase side switch circuit is turned off when the driving of the signal line by the positive phase side n-type transistor is unnecessary, it is possible to avoid an excessive potential supply from the low power supply line to the positive phase side signal line.

  Similarly, when the negative phase side signal line is set to the potential of the high power supply line, the negative phase side switch circuit is on. In this state, when a falling change of the input signal of the negative phase side drive circuit occurs, the negative phase side n-type transistor is turned on in addition to the negative phase side first p-type transistor. Therefore, the time required for the falling change of the signal transmitted through the negative phase side signal line is shortened. Then, as the potential of the negative phase side signal line falls below the threshold value of the negative phase side receiving circuit, the negative phase side switch circuit is turned off. Thus, when the potential of the negative phase side signal line is lowered, the negative phase side n-type transistor is turned on in addition to the negative phase side first p-type transistor, so that the signal transmission through the negative phase side signal line can be speeded up. Further, when the driving of the signal line by the negative-phase side n-type transistor becomes unnecessary, the negative-phase side switch circuit is turned off, so that excessive potential supply from the low power supply line to the negative-phase side signal line can be avoided.

  In a preferred example of the third technique related to the present invention, the positive phase side receiving circuit is configured to include a positive phase side cutoff circuit. The positive phase side cut-off circuit cuts off the potential supply from the high power supply line in response to the transition of the state transition circuit from the first operation state to the second operation state. The negative phase side receiving circuit is configured to include a negative phase side cutoff circuit. The negative phase side cut-off circuit cuts off the potential supply from the high power supply line in response to the transition from the second operation state to the first operation state of the state transition circuit.

  When the state transition circuit transits from the first operation state to the second operation state, in the positive phase side receiving circuit, the potential supply from the high power supply line is cut off by the positive phase side cutoff circuit, so transmission is performed by the positive phase side signal line. The through current generated due to the set signal being set to the intermediate potential can be suppressed. Further, when the state transition circuit transits from the second operation state to the first operation state, in the negative phase side receiving circuit, the potential supply from the high power supply line is cut off by the negative phase side cutoff circuit, so the negative phase side signal line Can suppress the through current generated due to the signal transmitted by the signal being set at the intermediate potential.

  According to the present invention, by reducing the amplitude of a signal transmitted through a signal line having a large load, the power consumption caused by the signal line having a large load can be reduced, and the power consumption of the semiconductor integrated circuit can be greatly reduced. .

It is explanatory drawing which shows 1st Embodiment of this invention. It is explanatory drawing which shows the operation | movement waveform of 1st Embodiment of this invention. It is explanatory drawing which shows the 1st comparative example of this invention. It is explanatory drawing which shows 2nd Embodiment of this invention. It is explanatory drawing which shows the operation | movement waveform of 2nd Embodiment of this invention. It is explanatory drawing which shows 3rd Embodiment of this invention. It is explanatory drawing which shows 4th Embodiment of this invention. It is explanatory drawing which shows 5th Embodiment of this invention. It is explanatory drawing which shows the operation | movement waveform of 5th Embodiment of this invention. It is explanatory drawing which shows 6th Embodiment of this invention. It is explanatory drawing which shows 7th Embodiment of this invention. It is explanatory drawing which shows 8th Embodiment of this invention. It is explanatory drawing which shows the operation | movement waveform of 8th Embodiment of this invention. It is explanatory drawing which shows the 2nd comparative example of this invention. It is explanatory drawing which shows 9th Embodiment of this invention. It is explanatory drawing which shows 10th Embodiment of this invention. It is explanatory drawing which shows 11th Embodiment of this invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a first embodiment of the present invention. The semiconductor integrated circuit IC11 includes a signal line GL11, a drive circuit DC11 that drives the signal line GL11 according to the input signal S11, a reception circuit RC11 that generates an output signal according to the potential of the signal line GL11, and a reception circuit RC11. A latch circuit LC11 that latches the output signal and generates an output signal S12. For example, the drive circuit DC11 and the reception circuit RC11 are provided in separate circuit blocks that are spaced apart. The latch circuit LC11 is provided in the same circuit block as the reception circuit RC11. The signal line GL11 is a so-called global signal line (inter-block signal line) and is a signal line with a large load.

  The drive circuit DC11 has a pMOS transistor TD11 (first p-type transistor) and an nMOS transistor TD12 (first n-type transistor). The source of the pMOS transistor TD11 is connected to the signal line GL11. The drain of the pMOS transistor TD11 is connected to the ground line VSS (low power supply line). The gate of the pMOS transistor TD11 receives the input signal S11. The source of the nMOS transistor TD12 is connected to the signal line GL11. The drain of the nMOS transistor TD12 is connected to the power supply line VDD (high power supply line). The gate of the nMOS transistor TD12 receives the input signal S11. The input signal S11 is a level signal supplied from, for example, a circuit provided in the same circuit block as the drive circuit DC11, and is supplied from the ground potential VSS (the potential of the ground line VSS) to the power supply potential VDD (the potential of the power supply line VDD). ).

  The receiving circuit RC11 has an nMOS transistor TR11 and a pMOS transistor TR12. The source of the nMOS transistor TR11 is connected to the ground line VSS. The drain of the nMOS transistor TR11 and the drain of the pMOS transistor TR12 are connected to each other. The source of the pMOS transistor TR12 is connected to the power supply line VDD. The gate of the nMOS transistor TR11 and the gate of the pMOS transistor TR12 are connected to the signal line GL11. As described above, the receiving circuit RC11 is an inverter composed of the nMOS transistor TR11 and the pMOS transistor TR12. When the potential of the signal line GL11 is larger than the threshold value (about 1/2 of the power supply potential VDD), the output signal (nMOS transistor) The signal generated at the connection node between TR11 and pMOS transistor TR12) is set to the ground potential VSS, and the output signal is set to the power supply potential VDD when the potential of the signal line GL11 is smaller than the threshold value.

  The latch circuit LC11 includes inverters IL11 and IL12 connected in a ring shape. A connection node between the input terminal of the inverter IL11 and the output terminal of the inverter IL12 is connected to an output node of the reception circuit RC11 (a connection node between the nMOS transistor TR11 and the pMOS transistor TR12). The output signal S12 of the latch circuit LC11 is a signal generated at a connection node between the output terminal of the inverter IL11 and the input terminal of the inverter IL12.

  FIG. 2 shows operation waveforms of the first embodiment of the present invention. The pMOS transistor TD11 turns on when the gate-source voltage falls below the threshold voltage Vthp, and turns off when the gate-source voltage exceeds the threshold voltage Vthp. The nMOS transistor TD12 turns on when the gate-source voltage exceeds the threshold voltage Vthn, and turns off when the gate-source voltage falls below the threshold voltage Vthn. For this reason, when the input signal S11 changes from the ground potential VSS to the power supply potential VDD (FIG. 2A), only the nMOS transistor TD12 is turned on, and the potential of the signal line GL11 is raised (FIG. 2B). When the potential of the signal line GL11 is raised to the intermediate potential VMH (VDD−Vthn), the nMOS transistor TD12 is turned off. When the potential of the signal line GL11 exceeds the threshold value of the reception circuit RC11, the output signal of the reception circuit RC11 changes from the power supply potential VDD to the ground potential VSS, so that the output signal S12 of the latch circuit LC11 changes from the ground potential VSS to the power supply potential. It changes to VDD (FIG. 2C).

  Thereafter, when the input signal S11 changes from the power supply potential VDD to the ground potential VSS (FIG. 2 (d)), only the pMOS transistor TD11 is turned on, and the potential of the signal line GL11 is lowered (FIG. 2 (e)). When the potential of the signal line GL11 is lowered to the intermediate potential VML (VSS + | Vthp |), the pMOS transistor TD11 is turned off. When the potential of the signal line GL11 falls below the threshold value of the reception circuit RC11, the output signal of the reception circuit RC11 changes from the ground potential VSS to the power supply potential VDD, so that the output signal S12 of the latch circuit LC11 changes from the power supply potential VDD to the ground potential. It changes to VSS (FIG.2 (f)).

  Thus, in the semiconductor integrated circuit IC11, the amplitude of the signal transmitted through the signal line GL11 having a large load can be reduced to the amplitude from the intermediate potential VML to the intermediate potential VMH. For this reason, the power consumption caused by the signal line GL11 having a large load can be reduced, and the power consumption of the semiconductor integrated circuit IC11 can be greatly reduced.

  FIG. 3 shows a first comparative example of the present invention. In describing the first comparative example, the same elements as those described in the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted. The semiconductor integrated circuit ICC1 is configured by replacing the drive circuit DC11 with the drive circuit DCC1 with respect to the semiconductor integrated circuit IC11 (FIG. 1).

  The drive circuit DCC1 includes nMOS transistors TDC11 and TDC13 and pMOS transistors TDC12 and TDC14. The source of the nMOS transistor TDC11 is connected to the ground line VSS. The drain of the nMOS transistor TDC11 and the drain of the pMOS transistor TDC12 are connected to each other. The source of the pMOS transistor TDC12 is connected to the power supply line VDD. The gate of the nMOS transistor TDC11 and the gate of the pMOS transistor TDC12 receive the input signal S11. The source of the nMOS transistor TDC13 is connected to the ground line VSS. The drain of the nMOS transistor TDC13 and the drain of the pMOS transistor TDC14 are connected to the signal line GL11. The source of the pMOS transistor TDC14 is connected to the power supply line VDD. The gate of the nMOS transistor TDC13 and the gate of the pMOS transistor TDC14 are connected to a connection node between the nMOS transistor TDC11 and the pMOS transistor TDC12. That is, the drive circuit DCC1 is configured by connecting in series an inverter composed of an nMOS transistor TDC11 and a pMOS transistor TDC12 and an inverter composed of an nMOS transistor TDC13 and a pMOS transistor TDC14.

  In the semiconductor integrated circuit ICC1 having such a configuration, the amplitude of the signal transmitted through the signal line GL11 is the amplitude from the ground potential VSS to the power supply potential VDD. For this reason, in the semiconductor integrated circuit ICC1, the power consumption due to the signal line GL11 having a large load increases as compared with the semiconductor integrated circuit IC11.

  FIG. 4 shows a second embodiment of the present invention. In describing the second embodiment, the same elements as those described in the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted. The semiconductor integrated circuit IC12 is configured by replacing the semiconductor integrated circuit IC11 (FIG. 1) with the receiving circuit RC11 by the receiving circuit RC12. The receiving circuit RC12 is configured by adding an nMOS transistor TR13, a pMOS transistor TR14 (cut-off circuit), and an inverter IR11 to the receiving circuit RC11.

  The source of the nMOS transistor TR13 is connected to the ground line VSS. The drain of the nMOS transistor TR13 is connected to the source of the nMOS transistor TR11. The gate of the nMOS transistor TR13 receives a control signal CTL. The source of the pMOS transistor TR14 is connected to the power supply line VDD. The drain of the pMOS transistor TR14 is connected to the source of the pMOS transistor TR12. The gate of the pMOS transistor TR14 receives the control signal CTL via the inverter IR11. That is, the gate of the pMOS transistor TR14 receives the inverted signal of the control signal CTL.

  The control signal CTL is a signal for instructing permission / prohibition of the reception operation of the reception circuit RC12, and is supplied from, for example, a control circuit (not shown) that controls the entire semiconductor integrated circuit IC12. The control signal CTL is set to the power supply potential VDD when the operation of the reception circuit RC12 is permitted, and is set to the ground potential VSS when the operation of the reception circuit RC12 is prohibited. Accordingly, the nMOS transistor TR13 and the pMOS transistor TR14 are turned on in response to a rising change (operation start request) of the control signal CTL, and are turned off in response to a falling change (operation stop request) of the control signal CTL.

  FIG. 5 shows operation waveforms of the second embodiment of the present invention. When the input signal S11 changes from the ground potential VSS to the power supply potential VDD (FIG. 5A), only the nMOS transistor TD12 is turned on and the potential of the signal line GL11 is raised (FIG. 5B). When the potential of the signal line GL11 is raised to the intermediate potential VMH, the nMOS transistor TD12 is turned off. In this state, when the control signal CTL changes from the ground potential VSS to the power supply potential VDD (FIG. 5C), the nMOS transistor TR13 and the pMOS transistor TR14 are turned on, and the output signal of the receiving circuit RC12 changes from the power supply potential VDD to the ground potential. Since it changes to VSS, the output signal S12 of the latch circuit LC11 changes from the ground potential VSS to the power supply potential VDD (FIG. 5D). When the control signal CTL changes from the power supply potential VDD to the ground potential VSS (FIG. 5 (e)), the nMOS transistor TR13 and the pMOS transistor TR14 are turned off.

  Thereafter, when the input signal S11 changes from the power supply potential VDD to the ground potential VSS (FIG. 5 (f)), only the pMOS transistor TD11 is turned on, and the potential of the signal line GL11 is lowered (FIG. 5 (g)). When the potential of the signal line GL11 is lowered to the intermediate potential VML, the pMOS transistor TD11 is turned off. In this state, when the control signal CTL changes from the ground potential VSS to the power supply potential VDD (FIG. 5 (h)), the nMOS transistor TR13 and the pMOS transistor TR14 are turned on, and the output signal of the receiving circuit RC12 changes from the ground potential VSS to the power supply potential. Since it changes to VDD, the output signal S12 of the latch circuit LC11 changes from the power supply potential VDD to the ground potential VSS (FIG. 5 (i)). When the control signal CTL changes from the power supply potential VDD to the ground potential VSS (FIG. 5 (j)), the nMOS transistor TR13 and the pMOS transistor TR14 are turned off.

  Thus, in the semiconductor integrated circuit IC12, when the rising change of the control signal CTL occurs in order to stop the operation of the receiving circuit RC12, the nMOS transistor TR13 and the pMOS transistor TR14 are turned off in the receiving circuit RC12. From the power supply line VDD to the pMOS transistor TR12 is cut off. For this reason, the through current generated due to the signal transmitted through the signal line GL11 being set to the intermediate potentials VML and VMH can be suppressed.

  FIG. 6 shows a third embodiment of the present invention. In describing the third embodiment, the same elements as those described in the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted. The semiconductor integrated circuit IC13 is configured by replacing the drive circuit DC11 with the drive circuit DC12 with respect to the semiconductor integrated circuit IC11 (FIG. 1). The drive circuit DC12 has an nMOS transistor TD13 (second n-type transistor), a pMOS transistor TD14 (second p-type transistor), an nMOS transistor TD15 (first switch circuit), and a pMOS transistor TD16 (second switch circuit) with respect to the drive circuit DC11. It is configured by adding.

  The drain of the nMOS transistor TD13 is connected to the signal line GL11. The source of the nMOS transistor TD13 and the drain of the nMOS transistor TD15 are connected to each other. The source of the nMOS transistor TD15 is connected to the ground line VSS. The drain of the pMOS transistor TD14 is connected to the signal line GL11. The source of the pMOS transistor TD14 and the drain of the pMOS transistor TD16 are connected to each other. The source of the pMOS transistor TD16 is connected to the power supply line VDD. The gate of the nMOS transistor TD13 and the gate of the pMOS transistor TD14 receive the input signal S11 via the inverter ID11. That is, the gate of the nMOS transistor TD13 and the gate of the pMOS transistor TD14 receive the inverted signal of the input signal S11. The gate of the nMOS transistor TD15 and the gate of the pMOS transistor TD16 are connected to the signal line GL11.

  In the semiconductor integrated circuit IC13 having such a configuration, when the signal line GL11 is set to the intermediate potential VMH, the nMOS transistor TD15 is turned on and the pMOS transistor TD16 is turned off. In this state, when the falling change of the input signal S11 occurs, the nMOS transistor TD13 is turned on in addition to the pMOS transistor TD11. Therefore, the time required for the falling change of the signal transmitted through the signal line GL11 is shortened. Then, as the potential of the signal line GL11 falls below the threshold value of the receiving circuit RC11, the nMOS transistor TD15 is turned off and the pMOS transistor TD16 is turned on.

  Further, when the signal line GL11 is set to the intermediate potential VML, the nMOS transistor TD15 is turned off and the pMOS transistor TD16 is turned on. In this state, when the rising change of the input signal S11 occurs, the pMOS transistor TD14 is turned on in addition to the nMOS transistor TD12. Therefore, the time required for the rising change of the signal transmitted through the signal line GL11 is shortened. Then, as the potential of the signal line GL11 exceeds the threshold value of the receiving circuit RC11, the nMOS transistor TD15 is turned on and the pMOS transistor TD16 is turned off.

  Thus, the nMOS transistor TD13 is turned on in addition to the pMOS transistor TD11 when the potential of the signal line GL11 is lowered, and the pMOS transistor TD14 is turned on in addition to the nMOS transistor TD12 when the potential of the signal line GL11 is raised. Signal transmission via the line GL11 can be speeded up. Further, the nMOS transistor TD15 is turned off when the driving of the signal line GL11 by the nMOS transistor TD13 becomes unnecessary, and the pMOS transistor TD16 is turned off when the driving of the signal line GL11 by the pMOS transistor TD14 becomes unnecessary. Therefore, it is possible to avoid an excessive potential supply from the first to the signal line GL11.

  FIG. 7 shows a fourth embodiment of the present invention. In describing the fourth embodiment, the same elements as those described in the first and third embodiments are denoted by the same reference numerals, and detailed description thereof is omitted. The semiconductor integrated circuit IC14 is configured by replacing the semiconductor integrated circuit IC13 (FIG. 6) with a driving circuit DC12. The drive circuit DC13 is configured by adding an inverter ID12 (detection circuit) and an inverter ID13 to the drive circuit DC12.

  The input terminal of the inverter ID12 is connected to the signal line GL11. The output terminal of the inverter ID12 and the input terminal of the inverter ID13 are connected to each other. The output terminal of the inverter ID13 is connected to the gate of the nMOS transistor TD15 and the gate of the pMOS transistor TD16.

  In the semiconductor integrated circuit IC14 having such a configuration, the inverter ID12 has the same circuit configuration as that of the reception circuit RC11. Therefore, the rise change and fall change are substantially the same between the output signal of the inverter ID12 and the output signal of the reception circuit RC11. It occurs at the timing of Therefore, on / off of the nMOS transistor TD15 and the pMOS transistor TD16 is controlled by the output signal of the inverter ID13 (inverted signal of the output signal of the inverter ID12), so that the driving of the signal line GL11 by the nMOS transistor TD13 becomes unnecessary. At this time, the nMOS transistor TD15 can be immediately turned off, and when the driving of the signal line GL11 by the pMOS transistor TD14 becomes unnecessary, the pMOS transistor TD16 can be turned off immediately. As a result, it is possible to reliably avoid an excessive potential supply from the ground line VSS and the power supply line VDD to the signal line GL11.

  FIG. 8 shows a fifth embodiment of the present invention. The semiconductor integrated circuit IC21 includes a signal line GL21, a drive circuit DC21 that drives the signal line GL21 according to the input signal S21, a reception circuit RC21 that generates an output signal according to the potential of the signal line GL21, and a reception circuit RC21. A latch circuit LC21 that latches the output signal and generates an output signal S22. For example, the drive circuit DC21 and the reception circuit RC21 are provided in separate circuit blocks that are spaced apart. The latch circuit LC21 is provided in the same circuit block as the reception circuit RC21. The signal line GL21 is a global signal line with a heavy load.

  The drive circuit DC21 includes a pMOS transistor TD21 (first p-type transistor), a pMOS transistor TD22 (second p-type transistor), and an inverter ID21. The source of the pMOS transistor TD21 is connected to the signal line GL21. The drain of the pMOS transistor TD21 is connected to the ground line VSS (low power supply line). The gate of the pMOS transistor TD21 receives the input signal S21. The source of the pMOS transistor TD22 is connected to the power supply line VDD (high power supply line). The drain of the pMOS transistor TD22 is connected to the signal line GL21. The gate of the pMOS transistor TD22 receives the input signal S21 via the inverter ID21. That is, the gate of the pMOS transistor TD22 receives the inverted signal of the input signal S21. The input signal S21 is, for example, a negative logic pulse signal supplied from a circuit provided in the same circuit block as the drive circuit DC21. From the ground potential VSS (active level) to the power supply potential VDD (inactive level). Has an amplitude of.

  The receiving circuit RC21 has an nMOS transistor TR21 and a pMOS transistor TR22. The source of the nMOS transistor TR21 is connected to the ground line VSS. The drain of the nMOS transistor TR21 and the drain of the pMOS transistor TR22 are connected to each other. The source of the pMOS transistor TR22 is connected to the power supply line VDD. The gate of the nMOS transistor TR21 and the gate of the pMOS transistor TR22 are connected to the signal line GL21. As described above, the receiving circuit RC21 is an inverter composed of the nMOS transistor TR21 and the pMOS transistor TR22. When the potential of the signal line GL21 is larger than the threshold value (about 1/2 of the power supply potential VDD), the output signal (nMOS transistor) The signal generated at the connection node of TR21 and pMOS transistor TR22) is set to the ground potential VSS, and the output signal is set to the power supply potential VDD when the potential of the signal line GL21 is smaller than the threshold value.

  The latch circuit LC21 includes inverters IL21 and IL22 connected in a ring shape. A connection node between the input terminal of the inverter IL21 and the output terminal of the inverter IL22 is connected to an output node of the reception circuit RC21 (a connection node between the nMOS transistor TR21 and the pMOS transistor TR22). The output signal S22 of the latch circuit LC21 is a signal generated at a connection node between the output terminal of the inverter IL21 and the input terminal of the inverter IL22.

  FIG. 9 shows operation waveforms of the fifth embodiment of the present invention. The pMOS transistor TD21 is turned on when the gate-source voltage falls below the threshold voltage Vthp, and turned off when the gate-source voltage exceeds the threshold voltage Vthp. For this reason, when the input signal S21 changes from the power supply potential VDD to the ground potential VSS (FIG. 9A), the pMOS transistor TD21 is turned on and the pMOS transistor TD22 is turned off to lower the potential of the signal line GL21 (FIG. 9). (B)). When the potential of the signal line GL21 is lowered to the intermediate potential VML (VSS + | Vthp |), the pMOS transistor TD21 is turned off. Further, when the potential of the signal line GL21 falls below the threshold value of the receiving circuit RC21, the output signal of the receiving circuit RC21 changes from the ground potential VSS to the power supply potential VDD, so that the output signal S22 of the latch circuit LC21 changes from the power supply potential VDD to the ground potential. It changes to VSS (FIG.9 (c)).

  Thereafter, when the input signal S21 changes from the ground potential VSS to the power supply potential VDD (FIG. 9D), the pMOS transistor TD22 is turned on and the potential of the signal line GL21 is raised to the power supply potential VDD (FIG. 9E). ). Further, when the potential of the signal line GL21 exceeds the threshold value of the reception circuit RC21, the output signal of the reception circuit RC21 changes from the power supply potential VDD to the ground potential VSS, so that the output signal S22 of the latch circuit LC21 changes from the ground potential VSS to the power supply potential. It changes to VDD (FIG. 9 (f)).

  Thus, in the semiconductor integrated circuit IC21, the amplitude of the signal transmitted through the signal line GL21 with a large load can be reduced to the amplitude from the intermediate potential VML to the power supply potential VDD. For this reason, the power consumption caused by the signal line GL21 having a large load can be reduced, which can greatly contribute to the reduction of the power consumption of the semiconductor integrated circuit IC21.

  FIG. 10 shows a sixth embodiment of the present invention. In describing the sixth embodiment, the same elements as those described in the fifth embodiment are denoted by the same reference numerals, and detailed description thereof is omitted. The semiconductor integrated circuit IC22 is configured by replacing the drive circuit DC21 with the drive circuit DC22 with respect to the semiconductor integrated circuit IC21 (FIG. 8).

  The drive circuit DC22 is configured by adding an nMOS transistor TD23 (n-type transistor) and an nMOS transistor TD24 (switch circuit) to the drive circuit DC21. The drain of the nMOS transistor TD23 is connected to the signal line GL21. The source of the nMOS transistor TD23 and the drain of the nMOS transistor TD24 are connected to each other. The source of the nMOS transistor TD24 is connected to the ground line VSS. The gate of the nMOS transistor TD23 receives the input signal S21 via the inverter ID21. That is, the gate of the nMOS transistor TD23 receives the inverted signal of the input signal S21. The gate of the nMOS transistor TD24 is connected to the signal line GL21.

  In the semiconductor integrated circuit IC22 having such a configuration, the nMOS transistor TD24 is turned on when the signal line GL21 is set to the power supply potential VDD. In this state, when the falling change of the input signal S21 occurs, the nMOS transistor TD23 is turned on in addition to the pMOS transistor TD21. Accordingly, the time required for the falling change (activation) of the signal transmitted through the signal line GL21 is shortened. Then, as the potential of the signal line GL21 falls below the threshold value of the receiving circuit RC21, the nMOS transistor TD24 is turned off. As described above, when the potential of the signal line GL21 is lowered, the nMOS transistor TD23 is turned on in addition to the pMOS transistor TD21, so that the signal transmission through the signal line GL21 can be speeded up. Further, when the driving of the signal line GL21 by the nMOS transistor TD23 becomes unnecessary, the nMOS transistor TD24 is turned off, so that an excessive potential supply from the ground line VSS to the signal line GL21 can be avoided.

  FIG. 11 shows a seventh embodiment of the present invention. In describing the seventh embodiment, the same elements as those described in the fifth and sixth embodiments are denoted by the same reference numerals, and detailed description thereof is omitted. The semiconductor integrated circuit IC23 is configured by replacing the drive circuit DC22 with the drive circuit DC23 with respect to the semiconductor integrated circuit IC22 (FIG. 10). The drive circuit DC23 is configured by adding an inverter ID22 (detection circuit) and an inverter ID23 to the drive circuit DC22. An input terminal of the inverter ID22 is connected to the signal line GL21. The output terminal of the inverter ID22 and the input terminal of the inverter ID23 are connected to each other. The output terminal of the inverter ID23 is connected to the gate of the nMOS transistor TD24.

  In the semiconductor integrated circuit IC23 having such a configuration, the inverter ID22 has the same circuit configuration as that of the reception circuit RC21. Therefore, the rise change and the fall change are almost the same between the output signal of the inverter ID22 and the output signal of the reception circuit RC21. It occurs at the timing of Therefore, by controlling on / off of the nMOS transistor TD24 with the output signal of the inverter ID23 (inverted signal of the output signal of the inverter ID22), the driving of the signal line GL21 by the nMOS transistor TD23 becomes immediate. The nMOS transistor TD24 can be turned off. As a result, it is possible to reliably avoid an excessive potential supply from the ground line VSS to the signal line GL21.

  FIG. 12 shows an eighth embodiment of the present invention. The semiconductor integrated circuit IC31 includes a positive phase side signal line GL31A, a negative phase side signal line GL31B, a positive phase side drive circuit DC31A that drives the signal line GL31A according to the input signal S31A, and a signal line according to the input signal S31B. A negative phase side drive circuit DC31B that drives the GL 31B, a positive phase side reception circuit RC31A that generates an output signal according to the potential of the signal line GL31A, and a negative phase side reception that generates an output signal according to the potential of the signal line GL31B It has a circuit RC31B and a set / reset circuit SRC31 (state transition circuit) whose operation state transitions according to the output signals of the receiving circuits RC31A and RC31B. For example, the drive circuits DC31A and DC31B and the reception circuits RC31A and RC31B are provided in separate circuit blocks that are spaced apart from each other. The set / reset circuit SRC31 is provided in the same circuit block as the receiving circuits RC31A and RC31B. The signal lines GL31A and GL31B are global signal lines with a large load.

  The drive circuit DC31A includes a pMOS transistor TD31A (positive phase side first p-type transistor), a pMOS transistor TD32A (positive phase side second p-type transistor), and an inverter ID31A. The source of the pMOS transistor TD31A is connected to the signal line GL31A. The drain of the pMOS transistor TD31A is connected to the ground line VSS (low power supply line). The gate of the pMOS transistor TD31A receives the input signal S31A. The source of the pMOS transistor TD32A is connected to the power supply line VDD (high power supply line). The drain of the pMOS transistor TD32A is connected to the signal line GL31A. The gate of the pMOS transistor TD32A receives the input signal S31A via the inverter ID31A. That is, the gate of the pMOS transistor TD32A receives the inverted signal of the input signal S31A. The input signal S31A is a negative logic positive-phase pulse signal supplied from a circuit provided in the same circuit block as the drive circuits DC31A and DC31B, for example, and is supplied from the ground potential VSS (active level) to the power supply potential VDD (non- (Activity level).

  The drive circuit DC31B includes a pMOS transistor TD31B (negative-phase side first p-type transistor), a pMOS transistor TD32B (negative-phase side second p-type transistor), and an inverter ID31B. The source of the pMOS transistor TD31B is connected to the signal line GL31B. The drain of the pMOS transistor TD31B is connected to the ground line VSS. The gate of the pMOS transistor TD31B receives the input signal S31B. The source of the pMOS transistor TD32B is connected to the power supply line VDD. The drain of the pMOS transistor TD32B is connected to the signal line GL31B. The gate of the pMOS transistor TD32B receives the input signal S31B via the inverter ID31B. That is, the gate of the pMOS transistor TD32B receives the inverted signal of the input signal S31B. The input signal S31B is, for example, a negative logic negative-phase pulse signal supplied from a circuit provided in the same circuit block as the drive circuits DC31A and DC31B, and is supplied from the ground potential VSS (active level) to the power supply potential VDD (non-current). (Activity level).

  The receiving circuit RC31A has an nMOS transistor TR31A and a pMOS transistor TR32A. The source of the nMOS transistor TR31A is connected to the ground line VSS. The drain of the nMOS transistor TR31A and the drain of the pMOS transistor TR32A are connected to each other. The source of the pMOS transistor TR32A is connected to the power supply line VDD. The gate of the nMOS transistor TR31A and the gate of the pMOS transistor TR32A are connected to the signal line GL31A. As described above, the receiving circuit RC31A is an inverter composed of the nMOS transistor TR31A and the pMOS transistor TR32A, and outputs an output signal (nMOS transistor) when the potential of the signal line GL31A is larger than a threshold value (about 1/2 of the power supply potential VDD). The signal generated at the connection node between TR31A and the pMOS transistor TR32A) is set to the ground potential VSS, and the output signal is set to the power supply potential VDD when the potential of the signal line GL31A is smaller than the threshold value.

  The receiving circuit RC31B has an nMOS transistor TR31B and a pMOS transistor TR32B. The source of the nMOS transistor TR31B is connected to the ground line VSS. The drain of the nMOS transistor TR31B and the drain of the pMOS transistor TR32B are connected to each other. The source of the pMOS transistor TR32B is connected to the power supply line VDD. The gate of the nMOS transistor TR31B and the gate of the pMOS transistor TR32B are connected to the signal line GL31B. Thus, the receiving circuit RC31B is an inverter composed of the nMOS transistor TR31B and the pMOS transistor TR32B, and outputs an output signal (nMOS transistor) when the potential of the signal line GL31B is larger than a threshold value (about 1/2 of the power supply potential VDD). The signal generated at the connection node between TR31B and pMOS transistor TR32B) is set to the ground potential VSS, and the output signal is set to the power supply potential VDD when the potential of the signal line GL31B is smaller than the threshold value.

  The set / reset circuit SRC31 includes nMOS transistors TS31 and TS32 and inverters IS31 and IS32. The source of the nMOS transistor TS31 is connected to the ground line VSS. The drain of the nMOS transistor TS31, the input terminal of the inverter IS31, and the output terminal of the inverter IS32 are connected to each other. The drain of the nMOS transistor TS32, the output terminal of the inverter IS31, and the input terminal of the inverter IS32 are connected to each other. The source of the nMOS transistor TS32 is connected to the ground line VSS. The gate of the nMOS transistor TS31 is connected to a connection node between the nMOS transistor TR31A and the pMOS transistor TR32A in the reception circuit RC31A. The gate of the nMOS transistor TS32 is connected to a connection node between the nMOS transistor TR31B and the pMOS transistor TR32B in the reception circuit RC31B. The set / reset circuit SRC31 having such a configuration makes a transition from the set state to the reset state in response to the rising change of the output signal of the receiving circuit RC31A, and outputs the output signal S32 (the input terminal of the inverter IS31 and the output terminal of the inverter IS32). To the ground potential VSS. Further, the set / reset circuit SRC31 transitions from the reset state to the set state in response to the rising change of the output signal of the reception circuit RC31B, and sets the output signal S32 to the power supply potential VDD.

  FIG. 13 shows operation waveforms of the eighth embodiment of the present invention. The pMOS transistors TD31A and TD31B are turned on when the gate-source voltage falls below the threshold voltage Vthp, and turned off when the gate-source voltage exceeds the threshold voltage Vthp. Therefore, when the input signal S31A changes from the power supply potential VDD to the ground potential VSS (FIG. 13A), the pMOS transistor TD31A is turned on and the pMOS transistor TD32A is turned off, so that the potential of the signal line GL31A is lowered (FIG. 13). (B)). When the potential of the signal line GL31A is lowered to the intermediate potential VML (VSS + | Vthp |), the pMOS transistor TD31A is turned off. Further, when the potential of the signal line GL31A falls below the threshold value of the reception circuit RC31A, the output signal of the reception circuit RC31A changes from the ground potential VSS to the power supply potential VDD, and thus the output signal S32 of the set / reset circuit SRC31 changes from the power supply potential VDD. It changes to the ground potential VSS (FIG. 13C). When the input signal S31A changes from the ground potential VSS to the power supply potential VDD (FIG. 13 (d)), the pMOS transistor TD32A is turned on and the potential of the signal line GL31A is raised to the power supply potential VDD (FIG. 13 (e)). .

  Thereafter, when the input signal S31B changes from the power supply potential VDD to the ground potential VSS (FIG. 13 (f)), the pMOS transistor TD31B is turned on, the pMOS transistor TD32B is turned off, and the potential of the signal line GL31B is lowered (FIG. 13). (G)). When the potential of the signal line GL31B is lowered to the intermediate potential VML, the pMOS transistor TD31B is turned off. Further, when the potential of the signal line GL31B falls below the threshold value of the receiving circuit RC31B, the output signal of the receiving circuit RC31B changes from the ground potential VSS to the power supply potential VDD, and therefore the output signal S32 of the set / reset circuit SRC31 changes from the ground potential VSS. It changes to the power supply potential VDD (FIG. 13 (h)). When the input signal S31B changes from the ground potential VSS to the power supply potential VDD (FIG. 13 (i)), the pMOS transistor TD32B is turned on and the potential of the signal line GL31B is raised to the power supply potential VDD (FIG. 13 (j)). .

  As described above, in the semiconductor integrated circuit IC31, the amplitude of the signal transmitted through the signal lines GL31A and GL31B having a large load can be reduced to the amplitude from the intermediate potential VML to the power supply potential VDD. For this reason, the power consumption caused by the signal lines GL31A and GL31B having a large load can be reduced, and the power consumption of the semiconductor integrated circuit IC31 can be greatly reduced.

  FIG. 14 shows a second comparative example of the present invention. In describing the second comparative example, the same elements as those described in the eighth embodiment are denoted by the same reference numerals, and detailed description thereof is omitted. The semiconductor integrated circuit ICC2 is configured by replacing the positive phase side drive circuit DC31A and the negative phase side drive circuit DC31B with a positive phase side drive circuit DCC2A and a negative phase side drive circuit DCC2B, respectively, with respect to the semiconductor integrated circuit IC31 (FIG. 12). ing.

  The drive circuit DCC2A includes nMOS transistors TDC21A and TDC23A and pMOS transistors TDC22A and TDC24A. The source of the nMOS transistor TDC21A is connected to the ground line VSS. The drain of the nMOS transistor TDC21A and the drain of the pMOS transistor TDC22A are connected to each other. The source of the pMOS transistor TDC22A is connected to the power supply line VDD. The gate of the nMOS transistor TDC21A and the gate of the pMOS transistor TDC22A receive the input signal S31A. The source of the nMOS transistor TDC23A is connected to the ground line VSS. The drain of the nMOS transistor TDC23A and the drain of the pMOS transistor TDC24A are connected to the signal line GL31A. The source of the pMOS transistor TDC24A is connected to the power supply line VDD. The gate of the nMOS transistor TDC23A and the gate of the pMOS transistor TDC24A are connected to a connection node between the nMOS transistor TDC21A and the pMOS transistor TDC22A. That is, the drive circuit DCC2A is configured by connecting in series an inverter composed of an nMOS transistor TDC21A and a pMOS transistor TDC22A and an inverter composed of an nMOS transistor TDC23A and a pMOS transistor TDC24A.

  The drive circuit DCC2B has nMOS transistors TDC21B and TDC23B and pMOS transistors TDC22B and TDC24B. The source of the nMOS transistor TDC21B is connected to the ground line VSS. The drain of the nMOS transistor TDC21B and the drain of the pMOS transistor TDC22B are connected to each other. The source of the pMOS transistor TDC22B is connected to the power supply line VDD. The gate of the nMOS transistor TDC21B and the gate of the pMOS transistor TDC22B receive the input signal S31B. The source of the nMOS transistor TDC23B is connected to the ground line VSS. The drain of the nMOS transistor TDC23B and the drain of the pMOS transistor TDC24B are connected to the signal line GL31B. The source of the pMOS transistor TDC24B is connected to the power supply line VDD. The gate of the nMOS transistor TDC23B and the gate of the pMOS transistor TDC24B are connected to a connection node between the nMOS transistor TDC21B and the pMOS transistor TDC22B. That is, the drive circuit DCC2B is configured by connecting in series an inverter composed of an nMOS transistor TDC21B and a pMOS transistor TDC22B and an inverter composed of an nMOS transistor TDC23B and a pMOS transistor TDC24B.

  In the semiconductor integrated circuit ICC2 having such a configuration, signals transmitted through the signal lines GL31A and GL31B have an amplitude from the ground potential VSS to the power supply potential VDD. For this reason, in the semiconductor integrated circuit ICC2, the power consumption caused by the signal lines GL31A and GL31B having a large load is larger than that in the semiconductor integrated circuit IC31.

  FIG. 15 shows a ninth embodiment of the present invention. In describing the ninth embodiment, the same elements as those described in the eighth embodiment are denoted by the same reference numerals, and detailed description thereof is omitted. The semiconductor integrated circuit IC32 is configured by replacing the positive phase side driving circuit DC31A and the negative phase side driving circuit DC31B with a positive phase side driving circuit DC32A and a negative phase side driving circuit DC32B, respectively, with respect to the semiconductor integrated circuit IC31 (FIG. 12). ing.

  The drive circuit DC32A is configured by adding an nMOS transistor TD33A (positive phase side n-type transistor) and an nMOS transistor TD34A (positive phase side switch circuit) to the drive circuit DC31A. The drain of the nMOS transistor TD33A is connected to the signal line GL31A. The source of the nMOS transistor TD33A and the drain of the nMOS transistor TD34A are connected to each other. The source of the nMOS transistor TD34A is connected to the ground line VSS. The gate of the nMOS transistor TD33A receives the input signal S31A via the inverter ID31A. That is, the gate of the nMOS transistor TD33A receives the inverted signal of the input signal S31A. The gate of the nMOS transistor TD34A is connected to the signal line GL31A.

  The drive circuit DC32B includes an nMOS transistor TD33B (negative-phase side n-type transistor) and an nMOS transistor TD34B (negative-phase side switch circuit) with respect to the drive circuit DC31B. The drain of the nMOS transistor TD33B is connected to the signal line GL31B. The source of the nMOS transistor TD33B and the drain of the nMOS transistor TD34B are connected to each other. The source of the nMOS transistor TD34B is connected to the ground line VSS. The gate of the nMOS transistor TD33B receives the input signal S31B via the inverter ID31B. That is, the gate of the nMOS transistor TD33B receives the inverted signal of the input signal S31B. The gate of the nMOS transistor TD34B is connected to the signal line GL31B.

  In the semiconductor integrated circuit IC32 having such a configuration, when the signal line GL31A is set to the power supply potential VDD, the nMOS transistor TD34A is turned on. In this state, when a falling change of the input signal S31A occurs, the nMOS transistor TD33A is turned on in addition to the pMOS transistor TD31A. Therefore, the time required for the change (activation) of the signal transmitted through the signal line GL31A is shortened. Then, as the potential of the signal line GL31A falls below the threshold value of the receiving circuit RC31A, the nMOS transistor TD34A is turned off. As described above, when the potential of the signal line GL31A is lowered, the nMOS transistor TD33A is turned on in addition to the pMOS transistor TD31A, so that the signal transmission through the signal line GL31A can be speeded up. Further, when the driving of the signal line GL31A by the nMOS transistor TD33A becomes unnecessary, the nMOS transistor TD34A is turned off, so that an excessive potential supply from the ground line VSS to the signal line GL31A can be avoided.

  Similarly, when the signal line GL31B is set to the power supply potential VDD, the nMOS transistor TD34B is turned on. In this state, when the falling change of the input signal S31B occurs, the nMOS transistor TD33B is turned on in addition to the pMOS transistor TD31B. Therefore, the time required for the change (activation) of the signal transmitted through the signal line GL31B is shortened. Then, as the potential of the signal line GL31B falls below the threshold value of the receiving circuit RC31B, the nMOS transistor TD34B is turned off. As described above, since the nMOS transistor TD33B is turned on in addition to the pMOS transistor TD31B when the potential of the signal line GL31B is lowered, the signal transmission through the signal line GL31B can be speeded up. Further, when the driving of the signal line GL31B by the nMOS transistor TD33B becomes unnecessary, the nMOS transistor TD34B is turned off, so that an excessive potential supply from the ground line VSS to the signal line GL31B can be avoided.

  FIG. 16 shows a tenth embodiment of the present invention. In describing the tenth embodiment, the same elements as those described in the eighth and ninth embodiments are denoted by the same reference numerals, and detailed description thereof is omitted. The semiconductor integrated circuit IC33 is configured by replacing the semiconductor-side integrated circuit IC32 (FIG. 15) with the front-side drive circuit DC32A and the negative-phase side drive circuit DC32B, respectively, with the positive-phase-side drive circuit DC33A and the negative-phase-side drive circuit DC33B. Yes.

  The drive circuit DC33A is configured by adding an inverter ID 32A (positive phase side detection circuit) and an inverter ID 33A to the drive circuit DC32A. The input terminal of the inverter ID 32A is connected to the signal line GL31A. The output terminal of the inverter ID 32A and the input terminal of the inverter ID 33A are connected to each other. The output terminal of the inverter ID33A is connected to the gate of the nMOS transistor TD34A.

  The drive circuit DC33B is configured by adding an inverter ID32B (reverse phase side detection circuit) and an inverter ID33B to the drive circuit DC32B. The input terminal of the inverter ID 32B is connected to the signal line GL31B. The output terminal of the inverter ID 32B and the input terminal of the inverter ID 33B are connected to each other. The output terminal of the inverter ID33B is connected to the gate of the nMOS transistor TD34B.

  In the semiconductor integrated circuit IC33 having such a configuration, the inverter ID 32A has the same circuit configuration as that of the receiving circuit RC31A. Therefore, the rising change and the falling change are almost the same between the output signal of the inverter ID 32A and the output signal of the receiving circuit RC31A. It occurs at the timing of Therefore, by controlling on / off of the nMOS transistor TD34A with the output signal of the inverter ID33A (inverted signal of the output signal of the inverter ID32A), the driving of the signal line GL31A by the nMOS transistor TD33A becomes immediate. The nMOS transistor TD34A can be turned off. As a result, it is possible to reliably avoid an excessive potential supply from the ground line VSS to the signal line GL31A.

  Similarly, since the inverter ID 32B has the same circuit configuration as that of the reception circuit RC31B, the rise change and fall change occur at substantially the same timing in the output signal of the inverter ID 32B and the output signal of the reception circuit RC31B. Therefore, by controlling on / off of the nMOS transistor TD34B with the output signal of the inverter ID33B (inverted signal of the output signal of the inverter ID32B), the driving of the signal line GL31B by the nMOS transistor TD33B becomes unnecessary immediately. The nMOS transistor TD34B can be turned off. As a result, it is possible to reliably avoid an excessive potential supply from the ground line VSS to the signal line GL31B.

  FIG. 17 shows an eleventh embodiment of the present invention. In describing the eleventh embodiment, the same elements as those described in the eighth embodiment are denoted by the same reference numerals, and detailed description thereof is omitted. The semiconductor integrated circuit IC34 is configured by replacing the semiconductor integrated circuit IC31 (FIG. 12) with the positive phase side receiving circuit RC31A and the negative phase side receiving circuit RC31B with a positive phase side receiving circuit RC32A and a negative phase side receiving circuit RC32B, respectively. Has been.

  The reception circuit RC32A is configured by adding a pMOS transistor TR33A (positive phase side cutoff circuit) to the reception circuit RC31A. The source of the pMOS transistor TR33A is connected to the power supply line VDD. The drain of the pMOS transistor TR33A is connected to the source of the pMOS transistor TR32A. The gate of the pMOS transistor TR33A is connected to the connection node of the nMOS transistor TS32 and the inverters IS31 and IS32 in the set / reset circuit SRC31. That is, the gate of the pMOS transistor TR33A receives an inverted signal of the output signal S32 of the set / reset circuit SRC31. Accordingly, the pMOS transistor TR33A is turned on in response to the transition of the set / reset circuit SRC31 from the reset state to the set state, and is turned off in response to the transition of the set / reset circuit SRC31 from the set state to the reset state.

  The reception circuit RC32B is configured by adding a pMOS transistor TR33B (reverse phase side cutoff circuit) to the reception circuit RC31B. The source of the pMOS transistor TR33B is connected to the power supply line VDD. The drain of the pMOS transistor TR33B is connected to the source of the pMOS transistor TR32B. The gate of the pMOS transistor TR33B is connected to the connection node of the nMOS transistor TS31 and inverters IS31 and IS32 in the latch circuit SRC31. That is, the gate of the pMOS transistor TR33B receives the output signal S32 of the set / reset circuit SRC31. Accordingly, the pMOS transistor TR33B is turned on in response to the transition of the set / reset circuit SRC31 from the set state to the reset state, and is turned off in response to the transition of the set / reset circuit SRC31 from the reset state to the set state.

  In the semiconductor integrated circuit IC 34 having such a configuration, when the set / reset circuit SRC31 transits from the set state to the reset state, the pMOS transistor TR33A is turned off in the receiving circuit RC32A, so that the potential is supplied from the power supply line VDD to the pMOS transistor TR32A. Is cut off. For this reason, the through current generated due to the signal transmitted through the signal line GL31A being set to the intermediate potential VML can be suppressed. Further, when the set / reset circuit SRC31 transits from the reset state to the set state, the pMOS transistor TR33B is turned off in the receiving circuit RC32B, so that the potential supply from the power supply line VDD to the pMOS transistor TR32B is cut off. For this reason, the through current generated due to the signal transmitted through the signal line GL31B being set to the intermediate potential VML can be suppressed.

  In the fifth to seventh embodiments, examples in which the input signal of the drive circuit is a negative logic pulse signal have been described. However, the present invention is not limited to such embodiments. For example, when the input signal of the drive circuit is a positive logic pulse signal, the ground line and the power supply line are interchanged, the nMOS transistor is replaced with a pMOS transistor, and the pMOS transistor is replaced with an nMOS transistor to constitute the drive circuit. A similar effect can be obtained.

  In the eighth to eleventh embodiments, the example in which the input signal of the drive circuit is a negative logic positive / negative phase pulse signal has been described. However, the present invention is not limited to such an embodiment. For example, when the input signal of the drive circuit is a positive / negative phase pulse signal of positive logic, the ground line and the power supply line are switched, the nMOS transistor is replaced with a pMOS transistor, and the pMOS transistor is replaced with an nMOS transistor. By configuring the receiving circuit and the set / reset circuit, the same effect can be obtained.

The invention described in the above embodiments is organized and disclosed as an additional note below.
(Appendix 1)
A signal line;
A drive circuit for driving the signal line according to an input signal,
The drive circuit is
A first p-type transistor having a source connected to the signal line, a drain connected to a low power line, and a gate receiving an input signal;
A semiconductor integrated circuit comprising: a first n-type transistor having a source connected to the signal line, a drain connected to a high power supply line, and a gate receiving an input signal.
(Appendix 2)
In the semiconductor integrated circuit according to attachment 1,
A receiving circuit that sets an output signal to the potential of the low power supply line when the potential of the signal line is larger than a threshold, and sets an output signal to the potential of the high power supply line when the potential of the signal line is smaller than the threshold; Prepared,
The semiconductor integrated circuit according to claim 1, wherein the receiving circuit includes a cutoff circuit that cuts off the potential supply from the low power line and the high power line in response to an operation stop request.
(Appendix 3)
In the semiconductor integrated circuit according to attachment 1,
A receiving circuit that sets an output signal to the potential of the low power supply line when the potential of the signal line is larger than a threshold, and sets an output signal to the potential of the high power supply line when the potential of the signal line is smaller than the threshold; Prepared,
The drive circuit is
A second n-type transistor having a drain connected to the signal line and a gate receiving an inverted signal of the input signal;
A second p-type transistor having a drain connected to the signal line and a gate receiving an inverted signal of the input signal;
Provided between the source of the second n-type transistor and the low power supply line, and is turned on when the potential of the signal line exceeds the threshold value of the receiving circuit, and the potential of the signal line becomes the threshold value of the receiving circuit A first switch circuit that turns off as it falls below
Provided between the source of the second p-type transistor and the high power supply line and turned on as the potential of the signal line falls below the threshold value of the receiving circuit, and the potential of the signal line becomes the threshold value of the receiving circuit And a second switch circuit that is turned off as the value exceeds the upper limit.
(Appendix 4)
In the semiconductor integrated circuit according to attachment 3,
The drive circuit is provided for detecting a change in magnitude relationship between the potential of the signal line and the threshold value of the reception circuit, and includes a detection circuit having the same circuit configuration as the reception circuit,
The first switch circuit is turned on in response to a falling change in the output signal of the detection circuit, and is turned off in response to a rise change in the output signal of the detection circuit,
2. The semiconductor integrated circuit according to claim 1, wherein the second switch circuit is turned on in response to a rising change in the output signal of the detection circuit and turned off in response to a falling change in the output signal of the detection circuit.
(Appendix 5)
A signal line;
A drive circuit that receives a negative logic pulse signal as an input signal and drives the signal line according to the input signal;
The drive circuit is
A first p-type transistor having a source connected to the signal line, a drain connected to a low power line, and a gate receiving an input signal;
A semiconductor integrated circuit comprising: a second p-type transistor having a source connected to a high power supply line, a drain connected to the signal line, and a gate receiving an inverted signal of an input signal.
(Appendix 6)
In the semiconductor integrated circuit according to appendix 5,
A receiving circuit that sets an output signal to the potential of the low power supply line when the potential of the signal line is larger than a threshold, and sets an output signal to the potential of the high power supply line when the potential of the signal line is smaller than the threshold; Prepared,
The drive circuit is
An n-type transistor having a drain connected to the signal line and a gate receiving an inverted signal of the input signal;
It is provided between the source of the n-type transistor and the low power supply line, and is turned on when the potential of the signal line exceeds the threshold value of the receiving circuit, and the potential of the signal line decreases the threshold value of the receiving circuit. A semiconductor integrated circuit comprising: a switch circuit that is turned off as the voltage falls below. (Appendix 7)
In the semiconductor integrated circuit according to appendix 6,
The drive circuit is provided for detecting a change in magnitude relationship between the potential of the signal line and the threshold value of the reception circuit, and includes a detection circuit having the same circuit configuration as the reception circuit,
2. The semiconductor integrated circuit according to claim 1, wherein the switch circuit is turned on in response to a falling change in the output signal of the detection circuit and turned off in response to a rise change in the output signal of the detection circuit.
(Appendix 8)
Positive phase side signal line,
A negative phase side signal line,
A positive phase side drive circuit which receives a negative logic positive phase pulse signal as an input signal and drives the positive phase side signal line according to the input signal;
Receiving a negative logic negative phase pulse signal as an input signal, and driving the negative phase side signal line according to the input signal;
The output signal is set to the low power supply line potential when the positive phase signal line potential is greater than the threshold, and the output signal is set to the high power supply line potential when the positive phase signal line potential is less than the threshold. A positive-phase side receiving circuit,
The output signal is set to the potential of the low power supply line when the potential of the negative phase side signal line is larger than the threshold value, and the output signal is set to the potential of the high power supply line when the potential of the negative phase side signal line is smaller than the threshold value. A negative-phase side receiving circuit to be set to
In response to the rising change of the output signal of the positive phase side receiving circuit, the first operating state transits to the second operating state, and from the second operating state in response to the rising change of the output signal of the negative phase side receiving circuit. A state transition circuit for transitioning to the first operating state,
The positive phase side drive circuit is:
A positive phase side first p-type transistor having a source connected to the positive phase side signal line, a drain connected to the low power line, and a gate receiving an input signal;
A positive phase side second p-type transistor having a source connected to the high power line, a drain connected to the positive phase signal line, and a gate receiving an inverted signal of the input signal;
The negative phase side drive circuit is:
A negative phase side first p-type transistor having a source connected to the negative phase side signal line, a drain connected to the low power line, and a gate receiving an input signal;
A semiconductor integrated circuit comprising: a negative phase side second p-type transistor having a source connected to the high power supply line, a drain connected to the negative phase side signal line, and a gate receiving an inverted signal of an input signal.
(Appendix 9)
In the semiconductor integrated circuit according to appendix 8,
The positive phase side drive circuit is:
A positive phase side n-type transistor having a drain connected to the positive phase side signal line and a gate receiving an inverted signal of the input signal;
Provided between the source of the positive phase side n-type transistor and the low power supply line, and is turned on when the potential of the positive phase side signal line exceeds the threshold value of the positive phase side receiving circuit. A positive phase side switch circuit that turns off as the potential of the side signal line falls below the threshold value of the positive phase side receiving circuit,
The negative phase side drive circuit is:
A negative phase side n-type transistor having a drain connected to the negative phase side signal line and a gate receiving an inverted signal of the input signal;
Provided between the source of the negative-phase side n-type transistor and the low power supply line, and is turned on when the potential of the negative-phase side signal line exceeds the threshold value of the negative-phase side receiving circuit. And a reverse-phase side switch circuit that turns off when the potential of the side signal line falls below a threshold value of the negative-phase side reception circuit.
(Appendix 10)
In the semiconductor integrated circuit according to appendix 9,
The positive phase side driving circuit is provided to detect a change in magnitude relationship between the potential of the positive phase side signal line and the threshold value of the positive phase side receiving circuit, and has the same circuit configuration as the positive phase side receiving circuit A positive phase side detection circuit having
The positive phase side switch circuit is turned on in response to a falling change of the output signal of the positive phase side detection circuit, and is turned off in response to a rise change of the output signal of the positive phase side detection circuit.
The negative phase side driving circuit is provided for detecting a change in magnitude relationship between the potential of the negative phase side signal line and the threshold value of the negative phase side receiving circuit, and has the same circuit configuration as the negative phase side receiving circuit A negative phase side detection circuit having
The negative phase side switch circuit is turned on in response to a falling change in the output signal of the negative phase side detection circuit, and is turned off in response to a rise change in the output signal of the negative phase side detection circuit. A semiconductor integrated circuit.
(Appendix 11)
In the semiconductor integrated circuit according to appendix 8,
The positive phase side receiving circuit includes a positive phase side cutoff circuit that cuts off a potential supply from the high power supply line in response to a transition from the first operating state to the second operating state of the state transition circuit,
The negative phase side receiving circuit includes a negative phase side cutoff circuit that cuts off a potential supply from the high power supply line in response to a transition from the second operation state to the first operation state of the state transition circuit. A semiconductor integrated circuit.
(Appendix 12)
A signal line;
A drive circuit that receives a positive logic pulse signal as an input signal and drives the signal line according to the input signal;
The drive circuit is
A first n-type transistor having a source connected to the signal line, a drain connected to a high power line, and a gate receiving an input signal;
A semiconductor integrated circuit comprising: a second n-type transistor having a source connected to a low power supply line, a drain connected to the signal line, and a gate receiving an inverted signal of an input signal.
(Appendix 13)
In the semiconductor integrated circuit according to appendix 12,
A receiving circuit that sets an output signal to the potential of the low power supply line when the potential of the signal line is larger than a threshold, and sets an output signal to the potential of the high power supply line when the potential of the signal line is smaller than the threshold; Prepared,
The drive circuit is
A p-type transistor having a drain connected to the signal line and a gate receiving an inverted signal of the input signal;
Provided between the source of the p-type transistor and the high power supply line and turned on as the potential of the signal line falls below the threshold value of the receiving circuit, and the potential of the signal line decreases the threshold value of the receiving circuit. A semiconductor integrated circuit comprising: a switch circuit that is turned off as it exceeds the upper limit. (Appendix 14)
In the semiconductor integrated circuit according to attachment 13,
The drive circuit is provided for detecting a change in magnitude relationship between the potential of the signal line and the threshold value of the reception circuit, and includes a detection circuit having the same circuit configuration as the reception circuit,
2. The semiconductor integrated circuit according to claim 1, wherein the switch circuit is turned on in response to a rising change in the output signal of the detection circuit and turned off in response to a falling change in the output signal of the detection circuit.
(Appendix 15)
Positive phase side signal line,
A negative phase side signal line,
A positive-phase side drive circuit that receives a positive-phase positive-phase pulse signal as an input signal and drives the positive-phase side signal line according to the input signal;
A negative-phase side drive circuit that receives a positive-phase negative-phase pulse signal as an input signal and drives the negative-phase side signal line according to the input signal;
The output signal is set to the low power supply line potential when the positive phase signal line potential is greater than the threshold, and the output signal is set to the high power supply line potential when the positive phase signal line potential is less than the threshold. A positive-phase side receiving circuit,
The output signal is set to the potential of the low power supply line when the potential of the negative phase side signal line is larger than the threshold value, and the output signal is set to the potential of the high power supply line when the potential of the negative phase side signal line is smaller than the threshold value. A negative-phase side receiving circuit to be set to
In response to the falling change of the output signal of the positive phase side receiving circuit, the first operation state is changed to the second operating state, and in response to the falling change of the output signal of the negative phase side receiving circuit, the second operation is performed. A state transition circuit for transitioning from the state to the first operating state,
The positive phase side drive circuit is:
A positive phase side first n-type transistor having a source connected to the positive phase side signal line, a drain connected to the high power line, and a gate receiving an input signal;
A source connected to the low power supply line, a drain connected to the positive phase side signal line, and a gate receiving a positive phase side second n-type transistor for receiving an inverted signal of the input signal,
The negative phase side drive circuit is:
A negative phase side first n-type transistor having a source connected to the negative phase side signal line, a drain connected to the high power line, and a gate receiving an input signal;
A semiconductor integrated circuit comprising: a negative phase side second n-type transistor having a source connected to the low power supply line, a drain connected to the negative phase side signal line, and a gate receiving an inverted signal of the input signal.
(Appendix 16)
In the semiconductor integrated circuit according to appendix 15,
The positive phase side drive circuit is:
A positive phase side p-type transistor having a drain connected to the positive phase side signal line and a gate receiving an inverted signal of the input signal;
Provided between the source of the positive-phase side p-type transistor and the high power supply line, and turns on when the potential of the positive-phase side signal line falls below the threshold value of the positive-phase side receiving circuit. A positive phase side switch circuit that turns off as the potential of the side signal line exceeds a threshold value of the positive phase side receiving circuit,
The negative phase side drive circuit is:
A negative phase side p-type transistor having a drain connected to the negative phase side signal line and a gate receiving an inverted signal of the input signal;
Provided between the source of the negative-phase side p-type transistor and the high power supply line, and turns on when the potential of the negative-phase side signal line falls below the threshold value of the negative-phase side receiving circuit. A semiconductor integrated circuit, comprising: a negative phase side switch circuit that is turned off when the potential of the side signal line exceeds a threshold value of the negative phase side receiving circuit.
(Appendix 17)
In the semiconductor integrated circuit according to appendix 16,
The positive phase side driving circuit is provided to detect a change in magnitude relationship between the potential of the positive phase side signal line and the threshold value of the positive phase side receiving circuit, and has the same circuit configuration as the positive phase side receiving circuit A positive phase side detection circuit having
The positive phase side switch circuit is turned on in response to the rising change of the output signal of the positive phase side detection circuit, and is turned off in response to the falling change of the output signal of the positive phase side detection circuit.
The negative phase side driving circuit is provided for detecting a change in magnitude relationship between the potential of the negative phase side signal line and the threshold value of the negative phase side receiving circuit, and has the same circuit configuration as the negative phase side receiving circuit A negative phase side detection circuit having
The negative phase side switch circuit is turned on in response to a rising change in the output signal of the negative phase side detection circuit, and is turned off in response to a falling change in the output signal of the negative phase side detection circuit. A semiconductor integrated circuit.
(Appendix 18)
In the semiconductor integrated circuit according to appendix 15,
The positive phase side receiving circuit includes a positive phase side cutoff circuit that cuts off a potential supply from the low power line in response to a transition from the first operating state to the second operating state of the state transition circuit,
The negative phase side receiving circuit includes a negative phase side cutoff circuit that cuts off the potential supply from the low power line in response to the transition of the state transition circuit from the second operational state to the first operational state. A semiconductor integrated circuit.

  In the semiconductor integrated circuit of Supplementary Note 10, the positive phase side drive circuit includes a positive phase side first p-type transistor, a positive phase side second p-type transistor, a positive phase side n-type transistor, a positive phase side switch circuit, and a positive phase side A detection circuit is provided. The positive phase side detection circuit is provided to detect a change in the magnitude relationship between the potential of the positive phase side signal line and the threshold value of the positive phase side reception circuit, and has the same circuit configuration as the positive phase side reception circuit. The positive phase side switch circuit is turned on in response to the falling change of the output signal of the positive phase side detection circuit, and is turned off in response to the rise change of the output signal of the positive phase side detection circuit. The negative phase side drive circuit includes a negative phase side detection circuit in addition to the negative phase side first p-type transistor, the negative phase side second p-type transistor, the negative phase side n-type transistor, and the negative phase side switch circuit. . The negative phase side detection circuit is provided to detect a change in the magnitude relationship between the potential of the negative phase side signal line and the threshold value of the negative phase side reception circuit, and has the same circuit configuration as the negative phase side reception circuit. The negative phase side switch circuit is turned on in response to the falling change of the output signal of the negative phase side detection circuit, and is turned off in response to the rise change of the output signal of the negative phase side detection circuit.

  Since the positive phase side detection circuit has the same circuit configuration as the positive phase side reception circuit, there is a rise change and a fall change between the output signal of the positive phase side detection circuit and the output signal of the positive phase side reception circuit. It occurs at almost the same timing. For this reason, by controlling on / off of the positive phase side switch circuit with the output signal of the positive phase side detection circuit, the driving of the positive phase side signal line by the positive phase side n-type transistor becomes unnecessary immediately. The positive phase side switch circuit can be turned off. As a result, it is possible to reliably avoid an excessive potential supply from the low power supply line to the positive phase side signal line. Similarly, since the negative-phase side detection circuit has the same circuit configuration as the negative-phase side reception circuit, the output signal of the negative-phase side detection circuit and the output signal of the negative-phase side reception circuit have a rising change and a rising edge. Falling changes occur at almost the same timing. For this reason, by controlling the on / off of the negative phase side switch circuit with the output signal of the negative phase side detection circuit, the negative phase side signal line is no longer required to be driven by the negative phase side n-type transistor. The negative phase side switch circuit can be turned off. As a result, it is possible to reliably avoid an excessive potential supply from the low power supply line to the negative phase side signal line.

  In the semiconductor integrated circuit according to attachment 12, the semiconductor integrated circuit includes a signal line and a drive circuit. The drive circuit receives a positive logic pulse signal as an input signal and drives the signal line in accordance with the input signal. The drive circuit includes a first n-type transistor and a second n-type transistor. The source of the first n-type transistor is connected to the signal line. The drain of the first n-type transistor is connected to the high power supply line. The gate of the first n-type transistor receives an input signal. The source of the second n-type transistor is connected to the low power supply line. The drain of the second n-type transistor is connected to the signal line. The gate of the second n-type transistor receives an inverted signal of the input signal.

  By configuring the drive circuit for driving the signal line to include the first n-type transistor and the second n-type transistor, the amplitude of the signal transmitted through the signal line is changed from the potential of the low power supply line to the potential of the high power supply line by the first nth transistor. The amplitude can be reduced to a potential lower by the threshold voltage of the type transistor. For this reason, the power consumption resulting from a signal line can be reduced. Therefore, when the load of the signal line driven by the drive circuit is large, it can greatly contribute to the reduction in power consumption of the semiconductor integrated circuit.

  In the semiconductor integrated circuit according to attachment 13, the semiconductor integrated circuit includes a receiving circuit in addition to the signal line and the driving circuit. The receiving circuit sets the output signal to the potential of the low power supply line when the potential of the signal line is larger than the threshold value, and sets the output signal to the potential of the high power supply line when the potential of the signal line is smaller than the threshold value. The drive circuit includes a p-type transistor and a switch circuit in addition to the first n-type transistor and the second n-type transistor. The drain of the p-type transistor is connected to the signal line. The gate of the p-type transistor receives an inverted signal of the input signal. The switch circuit is provided between the source of the p-type transistor and the high power supply line. The switch circuit is turned on as the potential of the signal line falls below the threshold value of the receiving circuit, and turned off as the potential of the signal line exceeds the threshold value of the receiving circuit.

  In the semiconductor integrated circuit having such a configuration, the switch circuit is turned on when the signal line is set to the potential of the low power supply line. In this state, when a rising change of the input signal occurs, the p-type transistor is turned on in addition to the first n-type transistor. Therefore, the time required for the rise change (activation) of the signal transmitted through the signal line is shortened. Then, as the potential of the signal line exceeds the threshold value of the receiving circuit, the switch circuit is turned off. In this way, when raising the potential of the signal line, the p-type transistor is turned on in addition to the first n-type transistor, so that signal transmission through the signal line can be speeded up. Further, when the driving of the signal line by the p-type transistor becomes unnecessary, the switch circuit is turned off, so that excessive potential supply from the high power supply line to the signal line can be avoided.

  In the semiconductor integrated circuit according to attachment 14, the drive circuit includes a detection circuit in addition to the first n-type transistor, the second n-type transistor, the p-type transistor, and the switch circuit. The detection circuit is provided to detect a change in the magnitude relationship between the potential of the signal line and the threshold value of the reception circuit, and has the same circuit configuration as the reception circuit. The switch circuit is turned on in response to the rising change of the output signal of the detection circuit, and is turned off in response to the falling change of the output signal of the detection circuit.

  Since the detection circuit has the same circuit configuration as that of the reception circuit, a rise change and a fall change occur at almost the same timing in the output signal of the detection circuit and the output signal of the reception circuit. Therefore, by controlling on / off of the switch circuit with the output signal of the detection circuit, the switch circuit can be immediately turned off when driving of the signal line by the p-type transistor becomes unnecessary. As a result, excessive potential supply from the high power supply line to the signal line can be reliably avoided.

  In the semiconductor integrated circuit according to attachment 15, the semiconductor integrated circuit includes a positive phase side signal line, a negative phase side signal line, a positive phase side drive circuit, a negative phase side drive circuit, a positive phase side reception circuit, a negative phase side reception circuit, and a state. It is configured with a transition circuit. The positive phase side drive circuit receives a positive logic positive phase pulse signal as an input signal, and drives the positive phase side signal line in accordance with the input signal. The negative phase side drive circuit receives a positive logic negative phase pulse signal as an input signal, and drives the negative phase side signal line in accordance with the input signal. The positive phase side receiving circuit sets the output signal to the low power line potential when the positive phase signal line potential is greater than the threshold, and the output signal to the high power source when the positive phase signal line potential is less than the threshold. Set to line potential. The negative phase side receiving circuit sets the output signal to the low power line potential when the negative phase signal line potential is larger than the threshold, and the high phase power signal when the negative phase signal line potential is smaller than the threshold. Set to line potential. The state transition circuit transitions from the first operation state to the second operation state in response to the falling change of the output signal of the positive phase side receiving circuit, and responds to the falling change of the output signal of the negative phase side receiving circuit. Transition from the second operating state to the first operating state. The positive phase side drive circuit includes a positive phase side first n-type transistor and a positive phase side second n-type transistor. The source of the positive phase side first n-type transistor is connected to the positive phase side signal line. The drain of the positive-phase side first n-type transistor is connected to the high power supply line. The gate of the positive-phase side first n-type transistor receives an input signal (positive-phase pulse signal). The source of the positive-phase side second n-type transistor is connected to the low power supply line. The drain of the positive phase side second n-type transistor is connected to the positive phase side signal line. The gate of the positive-phase side second n-type transistor receives an inverted signal of the input signal. The negative phase side driving circuit includes a negative phase side first n-type transistor and a negative phase side second n-type transistor. The source of the negative phase side first n-type transistor is connected to the negative phase side signal line. The drain of the negative-phase side first n-type transistor is connected to the high power supply line. The gate of the negative phase side first p-type transistor receives an input signal (negative phase pulse signal). The source of the negative-phase side second n-type transistor is connected to the low power line. The drain of the negative phase side second n-type transistor is connected to the negative phase side signal line. The gate of the negative-phase side second n-type transistor receives an inverted signal of the input signal.

  By configuring the positive phase side drive circuit for driving the positive phase side signal line with the positive phase side first n-type transistor and the positive phase side second n-type transistor, the amplitude of the signal transmitted by the positive phase side signal line can be reduced. The amplitude from the potential of the low power supply line to the potential lower than the potential of the high power supply line by the threshold voltage of the positive-phase first n-type transistor can be reduced. Similarly, a signal transmitted through the negative phase side signal line by configuring the negative phase side drive circuit for driving the negative phase side signal line with the negative phase side first n-type transistor and the negative phase side second n-type transistor. Can be reduced to an amplitude from the potential of the low power supply line to the potential lower than the potential of the high power supply line by the threshold voltage of the negative-phase side first n-type transistor. For this reason, the power consumption resulting from the positive phase side signal line and the negative phase side signal line can be reduced. Therefore, when the load on the positive phase side signal line driven by the positive phase side drive circuit and the negative phase side signal line driven by the negative phase side drive circuit is large, it can greatly contribute to the reduction in power consumption of the semiconductor integrated circuit.

  In the semiconductor integrated circuit of appendix 16, the positive phase side drive circuit includes a positive phase side p-type transistor and a positive phase side switch circuit in addition to the positive phase side first n-type transistor and the positive phase side second n-type transistor. Is done. The drain of the positive phase side p-type transistor is connected to the positive phase side signal line. The gate of the positive phase side p-type transistor receives an inverted signal of the input signal (positive phase pulse signal). The positive phase side switch circuit is provided between the source of the positive phase side p-type transistor and the high power supply line. The positive phase side switch circuit is turned on as the potential of the positive phase side signal line falls below the threshold value of the positive phase side receiving circuit, and the potential of the positive phase side signal line exceeds the threshold value of the positive phase side receiving circuit. Turn off with it. The negative phase side drive circuit includes a negative phase side p-type transistor and a negative phase side switch circuit in addition to the negative phase side first n-type transistor and the negative phase side second n-type transistor. The drain of the negative phase side p-type transistor is connected to the negative phase side signal line. The gate of the negative phase side p-type transistor receives an inverted signal of the input signal (negative phase pulse signal). The negative phase side switch circuit is provided between the source of the negative phase side p-type transistor and the high power supply line. The negative phase side switch circuit is turned on as the potential of the negative phase side signal line falls below the threshold value of the negative phase side receiving circuit, and the potential of the negative phase side signal line exceeds the threshold value of the negative phase side receiving circuit. Turn off with it.

  In the semiconductor integrated circuit having such a configuration, when the positive phase side signal line is set to the potential of the low power supply line, the positive phase side switch circuit is turned on. In this state, when a rising change of the input signal of the positive phase side drive circuit occurs, the positive phase side p-type transistor is turned on in addition to the positive phase side first n-type transistor. Therefore, the time required for the rising change of the signal transmitted by the positive phase side signal line is shortened. Then, as the potential of the positive phase side signal line exceeds the threshold value of the positive phase side receiving circuit, the positive phase side switch circuit is turned off. In this way, when the potential of the positive phase side signal line is raised, the positive phase side p-type transistor is turned on in addition to the positive phase side first n-type transistor, so that the signal transmission through the positive phase side signal line can be speeded up. Further, since the positive phase side switch circuit is turned off when the driving of the signal line by the positive phase side p-type transistor is unnecessary, it is possible to avoid an excessive potential supply from the high power supply line to the positive phase side signal line.

  Similarly, when the negative phase side signal line is set to the potential of the low power supply line, the negative phase side switch circuit is turned on. In this state, when a rising change of the input signal of the negative phase side drive circuit occurs, the negative phase side p-type transistor is turned on in addition to the negative phase side first n-type transistor. Therefore, the time required for the rising change of the signal transmitted through the negative phase side signal line is shortened. Then, as the potential of the negative phase side signal line exceeds the threshold value of the negative phase side receiving circuit, the negative phase side switch circuit is turned off. Thus, since the negative phase side p-type transistor is turned on in addition to the negative phase side first n-type transistor when raising the potential of the negative phase side signal line, the signal transmission through the negative phase side signal line can be speeded up. In addition, when the driving of the signal line by the negative-phase side p-type transistor becomes unnecessary, the negative-phase side switch circuit is turned off, so that excessive potential supply from the high power supply line to the negative-phase side signal line can be avoided.

  In the semiconductor integrated circuit of Appendix 17, the positive phase side drive circuit includes a positive phase side first n-type transistor, a positive phase side second n-type transistor, a positive phase side p-type transistor, a positive phase side switch circuit, and a positive phase side A detection circuit is provided. The positive phase side detection circuit is provided to detect a change in the magnitude relationship between the potential of the positive phase side signal line and the threshold value of the positive phase side reception circuit, and has the same circuit configuration as the positive phase side reception circuit. The positive phase side switch circuit is turned on in response to the rising change of the output signal of the positive phase side detection circuit, and is turned off in response to the falling change of the output signal of the positive phase side detection circuit. The negative phase side drive circuit includes a negative phase side detection circuit in addition to the negative phase side first n-type transistor, the negative phase side second n-type transistor, the negative phase side p-type transistor, and the negative phase side switch circuit. . The negative phase side detection circuit is provided to detect a change in the magnitude relationship between the potential of the negative phase side signal line and the threshold value of the negative phase side reception circuit, and has the same circuit configuration as the negative phase side reception circuit. The negative phase side switch circuit is turned on in response to the rising change of the output signal of the negative phase side detection circuit, and is turned off in response to the falling change of the output signal of the negative phase side detection circuit.

  Since the positive phase side detection circuit has the same circuit configuration as the positive phase side reception circuit, there is a rise change and a fall change between the output signal of the positive phase side detection circuit and the output signal of the positive phase side reception circuit. It occurs at almost the same timing. For this reason, by controlling the on / off of the positive phase side switch circuit with the output signal of the positive phase side detection circuit, the driving of the positive phase side signal line by the positive phase side p-type transistor becomes unnecessary immediately. The positive phase side switch circuit can be turned off. As a result, it is possible to reliably avoid an excessive potential supply from the high power supply line to the positive phase side signal line. Similarly, since the negative-phase side detection circuit has the same circuit configuration as the negative-phase side reception circuit, the output signal of the negative-phase side detection circuit and the output signal of the negative-phase side reception circuit have a rising change and a rising edge. Falling changes occur at almost the same timing. For this reason, by controlling the on / off of the negative phase side switch circuit with the output signal of the negative phase side detection circuit, the negative phase side signal line is not required to be driven by the negative phase side p-type transistor. The negative phase side switch circuit can be turned off. As a result, it is possible to reliably avoid an excessive potential supply from the high power supply line to the negative phase side signal line.

  In the semiconductor integrated circuit according to appendix 18, the positive phase side receiving circuit includes a positive phase side cutoff circuit. The positive phase side cut-off circuit cuts off the potential supply from the low power supply line in response to the transition of the state transition circuit from the first operation state to the second operation state. The negative phase side receiving circuit is configured to include a negative phase side cutoff circuit. The negative phase side cut-off circuit cuts off the potential supply from the low power supply line in response to the transition of the state transition circuit from the second operation state to the first operation state.

  When the state transition circuit transits from the first operation state to the second operation state, in the positive-phase side receiving circuit, the potential supply from the low power supply line is cut off by the positive-phase side cut-off circuit. The through current generated due to the set signal being set to the intermediate potential can be suppressed. Further, when the state transition circuit transits from the second operation state to the first operation state, in the negative phase side receiving circuit, the potential supply from the low power supply line is cut off by the negative phase side cutoff circuit, so the negative phase side signal line Can suppress the through current generated due to the signal transmitted by the signal being set at the intermediate potential.

  As mentioned above, although this invention was demonstrated in detail, the above-mentioned embodiment and its modification are only examples of this invention, and this invention is not limited to these. Obviously, modifications can be made without departing from the scope of the present invention.

DC11-DC13, DC21-DC23... Driving circuit; DC31A-DC33A .. normal phase side driving circuit; DC31B-DC33B .. reverse phase side driving circuit; IC11-IC14, IC21-IC23, IC31-IC34. RC11, RC12, RC21 Receive circuit; RC31A, RC32A Normal phase side receive circuit; RC31B, RC32B Reverse phase side receive circuit; SRC31 Set / Reset circuit

Claims (14)

A signal line;
A drive circuit that receives a negative logic pulse signal as an input signal and drives the signal line according to the input signal;
The drive circuit is
A first p-type transistor having a source connected to the signal line, a drain connected to a low power line, and a gate receiving an input signal;
A semiconductor integrated circuit comprising: a second p-type transistor having a source connected to a high power supply line, a drain connected to the signal line, and a gate receiving an inverted signal of an input signal. The semiconductor integrated circuit according to claim 1,
A receiving circuit that sets an output signal to the potential of the low power supply line when the potential of the signal line is larger than a threshold, and sets an output signal to the potential of the high power supply line when the potential of the signal line is smaller than the threshold; Prepared,
The drive circuit is
An n-type transistor having a drain connected to the signal line and a gate receiving an inverted signal of the input signal;
It is provided between the source of the n-type transistor and the low power supply line, and is turned on when the potential of the signal line exceeds the threshold value of the receiving circuit, and the potential of the signal line decreases the threshold value of the receiving circuit. A semiconductor integrated circuit comprising: a switch circuit that is turned off as the voltage falls below. The semiconductor integrated circuit according to claim 2.
The drive circuit is provided for detecting a change in magnitude relationship between the potential of the signal line and the threshold value of the reception circuit, and includes a detection circuit having the same circuit configuration as the reception circuit,
2. The semiconductor integrated circuit according to claim 1, wherein the switch circuit is turned on in response to a falling change in the output signal of the detection circuit and turned off in response to a rise change in the output signal of the detection circuit. Positive phase side signal line,
A negative phase side signal line,
A positive phase side drive circuit which receives a negative logic positive phase pulse signal as an input signal and drives the positive phase side signal line according to the input signal;
Receiving a negative logic negative phase pulse signal as an input signal, and driving the negative phase side signal line according to the input signal;
The output signal is set to the low power supply line potential when the positive phase signal line potential is greater than the threshold, and the output signal is set to the high power supply line potential when the positive phase signal line potential is less than the threshold. A positive-phase side receiving circuit,
The output signal is set to the potential of the low power supply line when the potential of the negative phase side signal line is larger than the threshold value, and the output signal is set to the potential of the high power supply line when the potential of the negative phase side signal line is smaller than the threshold value. A negative-phase side receiving circuit to be set to
In response to the rising change of the output signal of the positive phase side receiving circuit, the first operating state transits to the second operating state, and from the second operating state in response to the rising change of the output signal of the negative phase side receiving circuit. A state transition circuit for transitioning to the first operating state,
The positive phase side drive circuit is:
A positive phase side first p-type transistor having a source connected to the positive phase side signal line, a drain connected to the low power line, and a gate receiving an input signal;
A positive phase side second p-type transistor having a source connected to the high power line, a drain connected to the positive phase signal line, and a gate receiving an inverted signal of the input signal;
The negative phase side drive circuit is:
A negative phase side first p-type transistor having a source connected to the negative phase side signal line, a drain connected to the low power line, and a gate receiving an input signal;
A semiconductor integrated circuit comprising: a negative phase side second p-type transistor having a source connected to the high power supply line, a drain connected to the negative phase side signal line, and a gate receiving an inverted signal of an input signal. The semiconductor integrated circuit according to claim 4, wherein
The positive phase side drive circuit is:
A positive phase side n-type transistor having a drain connected to the positive phase side signal line and a gate receiving an inverted signal of the input signal;
Provided between the source of the positive phase side n-type transistor and the low power supply line, and is turned on when the potential of the positive phase side signal line exceeds the threshold value of the positive phase side receiving circuit. A positive phase side switch circuit that turns off as the potential of the side signal line falls below the threshold value of the positive phase side receiving circuit,
The negative phase side drive circuit is:
A negative phase side n-type transistor having a drain connected to the negative phase side signal line and a gate receiving an inverted signal of the input signal;
Provided between the source of the negative-phase side n-type transistor and the low power supply line, and is turned on when the potential of the negative-phase side signal line exceeds the threshold value of the negative-phase side receiving circuit. And a reverse-phase side switch circuit that turns off when the potential of the side signal line falls below a threshold value of the negative-phase side reception circuit. The semiconductor integrated circuit according to claim 5, wherein
The positive phase side driving circuit is provided to detect a change in magnitude relationship between the potential of the positive phase side signal line and the threshold value of the positive phase side receiving circuit, and has the same circuit configuration as the positive phase side receiving circuit A positive phase side detection circuit having
The positive phase side switch circuit is turned on in response to a falling change of the output signal of the positive phase side detection circuit, and is turned off in response to a rise change of the output signal of the positive phase side detection circuit.
The negative phase side driving circuit is provided for detecting a change in magnitude relationship between the potential of the negative phase side signal line and the threshold value of the negative phase side receiving circuit, and has the same circuit configuration as the negative phase side receiving circuit A negative phase side detection circuit having
The negative phase side switch circuit is turned on in response to a falling change in the output signal of the negative phase side detection circuit, and is turned off in response to a rise change in the output signal of the negative phase side detection circuit. A semiconductor integrated circuit. The semiconductor integrated circuit according to claim 4, wherein
The positive phase side receiving circuit includes a positive phase side cutoff circuit that cuts off a potential supply from the high power supply line in response to a transition from the first operating state to the second operating state of the state transition circuit,
The negative phase side receiving circuit includes a negative phase side cutoff circuit that cuts off a potential supply from the high power supply line in response to a transition from the second operation state to the first operation state of the state transition circuit. A semiconductor integrated circuit. A signal line;
A drive circuit that receives a positive logic pulse signal as an input signal and drives the signal line according to the input signal;
The drive circuit is
A first n-type transistor having a source connected to the signal line, a drain connected to a high power line, and a gate receiving an input signal;
A semiconductor integrated circuit comprising: a second n-type transistor having a source connected to a low power supply line, a drain connected to the signal line, and a gate receiving an inverted signal of an input signal. The semiconductor integrated circuit according to claim 8, wherein
A receiving circuit that sets an output signal to the potential of the low power supply line when the potential of the signal line is larger than a threshold, and sets an output signal to the potential of the high power supply line when the potential of the signal line is smaller than the threshold; Prepared,
The drive circuit is
A p-type transistor having a drain connected to the signal line and a gate receiving an inverted signal of the input signal;
Provided between the source of the p-type transistor and the high power supply line and turned on as the potential of the signal line falls below the threshold value of the receiving circuit, and the potential of the signal line decreases the threshold value of the receiving circuit. A semiconductor integrated circuit comprising: a switch circuit that is turned off as it exceeds the upper limit. The semiconductor integrated circuit according to claim 9, wherein
The drive circuit is provided for detecting a change in magnitude relationship between the potential of the signal line and the threshold value of the reception circuit, and includes a detection circuit having the same circuit configuration as the reception circuit,
2. The semiconductor integrated circuit according to claim 1, wherein the switch circuit is turned on in response to a rising change in the output signal of the detection circuit and turned off in response to a falling change in the output signal of the detection circuit. Positive phase side signal line,
A negative phase side signal line,
A positive-phase side drive circuit that receives a positive-phase positive-phase pulse signal as an input signal and drives the positive-phase side signal line according to the input signal;
A negative-phase side drive circuit that receives a positive-phase negative-phase pulse signal as an input signal and drives the negative-phase side signal line according to the input signal;
The output signal is set to the low power supply line potential when the positive phase signal line potential is greater than the threshold, and the output signal is set to the high power supply line potential when the positive phase signal line potential is less than the threshold. A positive-phase side receiving circuit,
The output signal is set to the potential of the low power supply line when the potential of the negative phase side signal line is larger than the threshold value, and the output signal is set to the potential of the high power supply line when the potential of the negative phase side signal line is smaller than the threshold value. A negative-phase side receiving circuit to be set to
In response to the falling change of the output signal of the positive phase side receiving circuit, the first operation state is changed to the second operating state, and in response to the falling change of the output signal of the negative phase side receiving circuit, the second operation is performed. A state transition circuit for transitioning from the state to the first operating state,
The positive phase side drive circuit is:
A positive phase side first n-type transistor having a source connected to the positive phase side signal line, a drain connected to the high power line, and a gate receiving an input signal;
A source connected to the low power supply line, a drain connected to the positive phase side signal line, and a gate receiving a positive phase side second n-type transistor for receiving an inverted signal of the input signal,
The negative phase side drive circuit is:
A negative phase side first n-type transistor having a source connected to the negative phase side signal line, a drain connected to the high power line, and a gate receiving an input signal;
A semiconductor integrated circuit comprising: a negative phase side second n-type transistor having a source connected to the low power supply line, a drain connected to the negative phase side signal line, and a gate receiving an inverted signal of the input signal. The semiconductor integrated circuit according to claim 11, wherein
The positive phase side drive circuit is:
A positive phase side p-type transistor having a drain connected to the positive phase side signal line and a gate receiving an inverted signal of the input signal;
Provided between the source of the positive-phase side p-type transistor and the high power supply line, and turns on when the potential of the positive-phase side signal line falls below the threshold value of the positive-phase side receiving circuit. A positive phase side switch circuit that turns off as the potential of the side signal line exceeds a threshold value of the positive phase side receiving circuit,
The negative phase side drive circuit is:
A negative phase side p-type transistor having a drain connected to the negative phase side signal line and a gate receiving an inverted signal of the input signal;
Provided between the source of the negative-phase side p-type transistor and the high power supply line, and turns on when the potential of the negative-phase side signal line falls below the threshold value of the negative-phase side receiving circuit. A semiconductor integrated circuit, comprising: a negative phase side switch circuit that is turned off when the potential of the side signal line exceeds a threshold value of the negative phase side receiving circuit. The semiconductor integrated circuit according to claim 12, wherein
The positive phase side driving circuit is provided to detect a change in magnitude relationship between the potential of the positive phase side signal line and the threshold value of the positive phase side receiving circuit, and has the same circuit configuration as the positive phase side receiving circuit A positive phase side detection circuit having
The positive phase side switch circuit is turned on in response to the rising change of the output signal of the positive phase side detection circuit, and is turned off in response to the falling change of the output signal of the positive phase side detection circuit.
The negative phase side driving circuit is provided for detecting a change in magnitude relationship between the potential of the negative phase side signal line and the threshold value of the negative phase side receiving circuit, and has the same circuit configuration as the negative phase side receiving circuit A negative phase side detection circuit having
The negative phase side switch circuit is turned on in response to a rising change in the output signal of the negative phase side detection circuit, and is turned off in response to a falling change in the output signal of the negative phase side detection circuit. A semiconductor integrated circuit. The semiconductor integrated circuit according to claim 11, wherein
The positive phase side receiving circuit includes a positive phase side cutoff circuit that cuts off a potential supply from the low power line in response to a transition from the first operating state to the second operating state of the state transition circuit,
The negative phase side receiving circuit includes a negative phase side cutoff circuit that cuts off the potential supply from the low power line in response to the transition of the state transition circuit from the second operational state to the first operational state. A semiconductor integrated circuit.

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