JPH10227825A - Method for detecting ground fault of power system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a detecting method in which a ground fault including a phase change can be detected with high accuracy by a method wherein the capacitance of a coupling capacitor whose phase is n-1 with reference to the phase number of (n) s formed to be (k) times the capacitance of a remaining coupling capacitor whose phase is 1 and a voltage change due to the ground fault is fetched as 2k+1 times. SOLUTION: Coupling capacitors Ca, Cb, Cc are formed of conductors and charging conductors La, Lb, Lc. In addition, neutral points of the coupling capacitors Ca, Cb, Cc are grounded via a voltage-dividing capacitor Cd, and capacitances of the coupling capacitors Ca, Cb, Cc are set in such a way that a phase (a) and a phase (c) are (k) times (two times) and that a phase (b) is one times. Thereby, as compared with the case of a single-phase voltage detection, a voltage change amount Δ↑V is expanded to 2k+1 times, and also a phase shape can be detected. Even when the magnitude of an interterminal voltage ↑Vdg after the generation of a ground fault is within a setting value, it is judged that a ground fault is not generated when the voltage change amount Δ↑V including the phase change is larger than a prescribed settling value, and the accuracy of a judgment can be enhanced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for detecting a ground fault in an electric power system which is preferably used in connection with a power distribution equipment, particularly a gas-insulated switchgear called GIS.

[0002]

2. Description of the Related Art In a conventional ground fault detection method, a zero-phase current value obtained by a CT (current transformer) or a ZCT (zero-phase current transformer) is equal to or more than a predetermined set value, and a three-phase PT ( When the zero-phase voltage detected by the voltage transformer) or the GPT (ground instrument transformer) becomes equal to or higher than a predetermined set value, it is determined that a ground fault has occurred. For example, when a ground fault is detected in this way, the ground fault protection circuit derives a trip output to the circuit breaker.

However, the purpose of the GIS is to reduce the equipment cost and the installation space by downsizing, and the PT and GPT, which become large with the increase of the line voltage, are not used in power facilities of substations. It is no longer being installed. For this reason, conventionally, as shown in FIG. 15, a ground fault is easily and inexpensively detected to prevent an accident.

FIG. 15 is a block diagram for explaining a typical prior art ground fault detection method. Among the charging conductors La, Lb, Lc of the respective phases a, b, c in the GIS, a conductor is formed in parallel with any one of the charging conductors Lc in the example of FIG. Therefore, this conductor and the charging conductor Lc can be regarded as a coupling capacitor having a stray capacitance Co. In this way, the voltage dividing capacitor Cd is further interposed between the coupling capacitor Co coupled to the charging conductor Lc and the ground, and the voltage Vd between the terminals of the voltage dividing capacitor Cd is protected via a transformer or the like. It is taken in the relay. When the change amount ΔV of the inter-terminal voltage Vd is equal to or more than a predetermined set value,
It is determined that a ground fault has occurred, and a trip output is derived to a circuit breaker or the like.

However, in this prior art, since the single-phase voltage detection is used, the terminal voltage ↑ Vdo (↑ represents a vector) before the occurrence of a ground fault and the terminal voltage ↑ Vdg after the occurrence of a ground fault Is small. That is, the phase voltages ↑ Va, ↑ Vb, ↑ Vc of the respective phases a, b, c
Of the phase in which the ground fault of x% occurs, for example, ↑
Vb decreases by x ↑ Vb, that is, (1−x) ↑ Vb. On the other hand, the terminal voltage ↑ Vdg includes the phase voltage 、 Vc of the detection phase and the voltage −x ↑ Vb of the ground fault. And the rate of change α is α = | ↑ Vdg | / | ｇVdo | (1)

As described above, in the state where the c-phase is being detected, the change in the voltage change rate α with respect to the difference between the ground fault phase and the ground fault rate is described with reference to Table 1 and FIG. It will be described in detail.

FIG. 16 is a vector diagram for explaining the above-mentioned ground fault detecting method. As an example, x = 50 in the b phase.
% Ground fault has occurred. This FIG.
Then, the vector of each phase voltage ↑ Va, ↑ Vb, ↑ Vc is
The symbols a, b, or c of the respective phases are shown with an additional numeral indicating the size (%). As described above, since the detection is of the c-phase, ΔVdo = ΔVc, and in FIG. 16, “c1
00 ”. When a ground fault of x = 50% occurs in the b-phase, the terminal voltage ↑ Vdg becomes ↑ Vdg = ↑ Vc−x ↑ Vb (2), and the voltage change rate α is c100 = 1,

[0008]

(Equation 1)

## EQU1 ##

The above-mentioned change rate α of the inter-terminal voltage ΔVdg after the occurrence of the ground fault to the inter-terminal voltage ΔVdo before the occurrence of the ground fault is shown in Table 1 and FIG.

[0011]

[Table 1]

Therefore, there is a problem that the detection sensitivity is low and the detection can be performed only when the ground fault ratio x is about 10% or more. Another conventional technique that can solve such a problem is disclosed in Japanese Patent Publication No. 4-27775.

FIG. 18 is a block diagram for explaining another conventional ground fault detecting method. In this prior art, parallel conductors are provided facing the charging conductors La, Lb, Lc, respectively, and the coupling capacitors Ca, C are formed by the conductors and the charging conductors La, Lb, Lc.
b and Cc are respectively formed. The voltage dividing capacitor Cd includes these coupling capacitors Ca, Cb, and Cc.
Neutral point is connected.

Therefore, each phase voltage {Va, {Vb,}
In contrast to Vc, the inter-terminal voltage ΔVd is zero in a steady state. On the other hand, when a ground fault of x% occurs in the c phase as described above, the phase voltages ΔVa, ΔVb, and ΔVc become −xΔVc.
Are added. For this reason, the variation Δ の V of the inter-terminal voltage ↑ Vd (= ↑ Vdg- ↑ Vdo)
Becomes −3x ↑ Vc. Thus, in the conventional technique shown in FIG. 18, the voltage change amount Δ 量 V due to the ground fault is tripled.

[0015]

However, in such a conventional technique, although the voltage change amount Δ ↑ V can be enlarged to improve the detection sensitivity, the terminal voltage ↑ Vd is zero in a normal state. Yes, the ground fault detection is performed based only on the magnitude of the inter-terminal voltage ΔVd. For this reason, there is a problem that even if the phase is largely changed, it cannot be detected.

An object of the present invention is to provide a power system ground fault detection method capable of performing highly accurate detection including a phase change.

[0017]

SUMMARY OF THE INVENTION A method for detecting a ground fault in a power system according to the present invention comprises connecting a coupling capacitor to each of the transmission lines of each phase, and connecting the coupling capacitor between a neutral point and the ground. In a method of detecting a ground fault in a power system from a voltage between terminals of a voltage dividing capacitor by interposing a voltage dividing capacitor, the capacity of an n-1 phase coupling capacitor is changed with respect to the number of phases n by one. The capacitance of the coupling capacitor is k times as large, and the voltage change due to the ground fault is taken out as 2k + 1 times.

According to the above configuration, the terminal voltage .DELTA.Vd of the voltage dividing capacitor is generated in a steady state. For example, the capacity of the b-phase coupling capacitor is set to 1, and the remaining a-phase and c-phase capacitors are set.
Assuming that the capacitance of the phase coupling capacitor is doubled, the terminal-to-terminal voltage ↑ Vdo at steady state is as follows: ↑ Vdo = 2 ↑ Va + ↑ Vb + 2 ↑ Vc = 2 (↑ Va + ↑ Vc) / 2 = − ↑ Vb (4) ).

When a ground fault of x% occurs in any of the phases with reference to the inter-terminal voltage ΔVdo before the occurrence of the ground fault, the terminal before the occurrence of the ground fault of the inter-terminal voltage ΔVdg after the occurrence of the ground fault. As the voltage change Δ ↑ V with respect to the inter-voltage ↑ Vdo, a five-fold voltage change can be extracted, and the voltage change Δ
A phase change of ↑ V with respect to the inter-terminal voltage ↑ Vdo before the occurrence of the ground fault can also be detected.

Therefore, as compared with a case where a ground fault is detected by single-phase voltage detection, the voltage change amount Δ ↑ V can be expanded to 2k + 1 times, and a phase change can be detected. Even if the magnitude of the inter-terminal voltage ΔVdg is within the set value, if the voltage change Δ 量 V including the phase change is larger than a predetermined set value, it is determined that a ground fault has occurred. Thus, the determination accuracy can be improved.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described.
This will be described below with reference to FIGS.

FIG. 1 is a block diagram for explaining a ground fault detecting method according to an embodiment of the present invention. In the present invention, a conductor is formed in parallel with the charging conductors La, Lb, Lc of each phase a, b, c, and this conductor and the charging conductors La, Lb,
Lc forms coupling capacitors Ca, Cb and Cc. Further, these coupling capacitors Ca, C
The neutral points of b and Cc are grounded via a voltage dividing capacitor Cd, and the capacity of each of the coupling capacitors Ca, Cb and Cc is k times for two phases and one time for the remaining phase. In the example of FIG. 1, the b-phase is one-time, and the a-phase and c-phase
The phase has doubled.

Therefore, the terminal voltage 定 常 Vdo in the steady state
Is as shown in FIG.

In this state, for example, as shown in FIG.
When the ground fault of x% occurs in the a phase, the voltage between terminals ↑ Vdg after the occurrence of the ground fault is expressed as follows: ↑ Vdg = 2 (1-x) ↑ Va + (↑ Vb-x ↑ Va) +2 (↑ Vc-x ↑) Va) = 2 ↑ Va + ↑ Vb + 2 ↑ Vc−5x ↑ Va (5) Accordingly, the voltage change amount Δ ↑ V is Δ ↑ V = ↑ Vdo− ↑ Vdg = (2 ↑ Va + ↑ Vb + 2 ↑ Vc−5x ↑ Va) − (2 ↑ Va + ↑ Vb + 2 ↑ Vc) = − 5x ↑ Va ... ( 6)

When a ground fault of x% occurs in the b-phase, as shown in FIG.
g is as follows: Vdg = 2 (Va-x Vb) + (1-x) Vb + 2 (Vc-x Vb) = 2 Va + Vb + 2 Vc-5x Vb (7) The change amount Δ ↑ V is as follows: Δ ↑ V = −5 × ↑ Vb (8)

Furthermore, similarly to the above-mentioned a phase, x is added to c phase.
% When a ground fault occurs, the voltage change amount Δ ↑ V becomes Δ ↑ V = −5 × ↑ Vc (9).

FIG. 5 is a diagram showing voltage vectors at each local phase and each local ratio obtained in the same manner as described above. Further, Table 2 shows that the terminal-to-terminal voltage ΔV after the occurrence of the ground fault is the same as in Table 1.
It shows the rate of change of dg with respect to the inter-terminal voltage ΔVdo before the occurrence of a ground fault.

[0028]

[Table 2]

Therefore, in the present invention, when k = 2, the voltage change Δ ↑ V is expanded to (2k + 1) = 5 times as compared with the case of the single-phase voltage detection shown in FIG. And it is possible to detect even a ground fault of about 2%. Further, for example, when k = 3, the magnification can be increased seven times.

Further, according to the present invention, the terminal-to-terminal voltage ↑ Vdo can be detected even in a steady state, so that the terminal-to-terminal voltage ↑ Vdo after the occurrence of a ground fault is referenced with respect to the terminal-to-terminal voltage ↑ Vdo.
Even if the magnitude of dg is within a predetermined set value, for example, within the above 10%, the voltage change amount Δ ↑ V including the phase difference is a value corresponding to this 10%, that is, tan ⁻¹ 0.1 ≒ ±. 6
If the angle exceeds °, it is determined that a ground fault has occurred. That is, in FIG. 6, the voltage between terminals after the occurrence of a ground fault ΔVd
When g is outside the area indicated by hatching, it is determined that a ground fault has occurred.

FIG. 7 is a block diagram showing an electrical configuration of the ground fault voltage change relay 1 to which the above-described ground fault detecting method is applied. The neutral point of the coupling capacitors Ca, Cb, and Cc is connected to the ground fault voltage change relay 1 via a signal line 2, and the voltage of the neutral point is connected to one terminal of a voltage dividing capacitor Cd via a terminal h. Are applied to the terminals. Voltage dividing capacitor C
The other terminal of d is grounded via terminal l. Therefore, for example, the charging conductor L of 77 / √3 kV
The inter-terminal voltage Vd obtained by dividing the sum of the line voltages Va, Vb, and Vc of a, Lb, and Lc is input to the inspection circuit 3. An arrester 4 is provided in parallel with the voltage dividing capacitor Cd, and coupling capacitors Ca, Cb, Cc are provided.
The surge that entered from the side is eliminated.

The inspection circuit 3 is provided for inspecting a circuit at a subsequent stage, and is realized by, for example, a switch having a common contact and two individual contacts. This inspection circuit 3
An oscillation circuit 5 is provided in connection with the above. Oscillation circuit 5
Oscillates, for example, a signal having a frequency equal to the system voltage and having an amplitude obtained by dividing the voltage amplitude of the charging conductors La, Lb, Lc in a steady state.

In the inspection circuit 3, one terminal of the voltage dividing capacitor Cd is connected to the common contact and one input of the input filter 6 at the subsequent stage, and one individual contact is connected to the other terminal of the voltage dividing capacitor Cd. And the other input of the input filter 6, and the other individual contact is connected to the oscillation circuit 5. Thus, from the common contact of the inspection circuit 3, the terminal-to-terminal voltage Vd can be switched to a voltage corresponding to the steady state and 0V and output to the subsequent circuit, thereby enabling inspection. Further, when the common contact is disconnected from any individual contact, the terminal voltage of the voltage dividing capacitor Cd can be output as the terminal voltage Vd.

The output from the inspection circuit 3 is supplied to an input filter 6
Is input to the amplifier circuit 7 via the. The output of the amplifier circuit 7 is input to the bandpass filter 11 as an input I corresponding to the inter-terminal voltage Vd. In the bandpass filter 11, the amplitude level is changed by the amplitude control unit 11a, and the resonance frequency control unit After the frequency component set by 11b is extracted, it is input to the subtraction circuit 12. The input I is also directly input to the subtraction circuit 12, so that the subtraction circuit 12 outputs from the band-pass filter 11 an output consisting of a component that is one cycle earlier and within ± 3 Hz of the system frequency. The voltage waveform of I ′ is compared with the voltage waveform of the current input I, the difference between them is inverted and amplified, and the output ΔI is output as ΔI = −I + I ′. Therefore, when a ground fault occurs, the input I corresponds to the terminal voltage ↑ Vdg after the occurrence of the ground fault, the output I ′ corresponds to the terminal voltage ↑ Vdo before the occurrence of the ground fault, and the output Δ
I corresponds to the voltage change amount Δ ↑ V.

In connection with the band pass filter 11,
A phase error detection circuit 13 and an amplitude error detection circuit 14 are provided. These circuits 13 and 14 receive the input I in common and the output ΔI from the subtraction circuit 12.

Output ΔI = −I + from the subtraction circuit 12
I ′ is, for the input I to the bandpass filter 11,
Depending on whether the phase of the output I ′ is advanced or delayed, it is advanced or delayed by 90 ° from the input I. Therefore, the phase error detection circuit 13 adds the input I to the band-pass filter 11 and the output ΔI from the subtraction circuit 12, and when the output I ′ is ahead of the input I, the band-pass filter 11 It is determined that the resonance frequency is high, and when it is late, it is determined that the resonance frequency is low, and an output corresponding to the determination result is given to the resonance frequency control unit 11b to change the resonance frequency.

The amplitude error detecting circuit 14 compares the phases of the input I and the output .DELTA.I, and when they are in phase, the output I 'is large.
Is determined to be large, and when the phases are opposite, the output I ′ is determined to be small, that is, the gain is determined to be small, and an output corresponding to the determination result is output to the amplitude control unit 1.
1a. In this manner, the bandpass filter 11 outputs a component having only a predetermined gain and a predetermined frequency, with its phase inverted.

The output ΔI corresponding to the voltage change Δ ↑ V during one cycle of the terminal voltage ΔVd is input to the rectifier circuit 15, rectified and smoothed to a DC voltage, and then to the level detector 16. Is entered. The level detection circuit 16 determines whether or not the output level of the rectifier circuit 15 is equal to or greater than a predetermined set value of the voltage change amount Δ ↑ V, for example, a value corresponding to 10% of the system voltage. If the value is equal to or greater than the set value, a trip output is derived to the drive circuit 17.

The drive circuit 17 includes a power element for switching, a diode for absorbing a back electromotive force, and the like.
8 is conducted, and a contact output is derived.

As described above, when the output .DELTA.I corresponding to the voltage change .DELTA..SIGMA.V becomes equal to or larger than a predetermined set value, the occurrence of a ground fault is detected.

FIG. 8 is an electric circuit diagram for explaining a specific configuration for detecting the voltage change amount Δ ↑ V.
The band-pass filter 11 includes the amplitude control unit 11a
, A resonance frequency control unit 11b, and a filter unit 11c. The amplitude control unit 11a
T (field effect transistor) Q1 and resistors R1 and R2
, And a capacitor C1. The input I is input via a line 31. An FET Q1 is interposed in series on the line 31, a drain is supplied with an input I from the amplifier circuit 7 via a resistor R1, and a source is connected to the resonance frequency control unit 11b and the filter unit 11c. The output from the amplitude error detection circuit 14 is given to the gate via the resistor R2. A capacitor C is provided between the gate and source of the FET Q1.
1 is interposed. Therefore, the amplitude error detection circuit 1
4, the higher the output voltage, the lower the effective resistance value of the FET Q1 and the larger the maximum amplitude.

The resonance frequency control section 11b is connected to the FET Q2
And resistors R3 and R4. Resistance R
3, R4 are interposed in series between the source of the FET Q1 and the ground level line 32, and their voltage dividing points are connected to the drain of the FET Q2. FET Q2
The output from the phase error detection circuit 13 is given to the gate of the IGBT, and the source is connected to the line 32. Therefore, as the output voltage from the phase error detection circuit 13 increases, the effective resistance value of the FET Q2 decreases, the voltage division ratio of the resistors R3 and R4 changes, and the resonance frequency increases.

The filter section 11c includes a differential amplifier OP1
, Resistors R5 to R7, and capacitors C2 and C3. Outputs from the amplitude control unit 11a and the resonance frequency control unit 11b are input to the inverting input terminal of the differential amplifier OP1 via the input coupling capacitor C2. The non-inverting input terminal of the differential amplifier OP1 is connected to the line 32, and an output -I 'is derived from the output terminal. Also, the output -I 'of the differential amplifier OP1
Is divided by the resistors R5 and R6, then negatively fed back through the feedback resistor R7, and fed back to the input side of the capacitor C2 through the capacitor C3. Therefore, the resonance frequency can be controlled by the feedback resistor R7.

The subtraction circuit 12 includes a differential amplifier OP2
And resistors R8 to R10. The output -I 'of the band-pass filter 11 is input to an inverting input terminal of a differential amplifier OP2 via a resistor R10, and the input I is connected to an inverting input terminal of the differential amplifier OP2 via a resistor R8. And therefore I + (−
I ′) is added, that is, a subtraction operation of II ′ is performed, inverted, and output. The non-inverting input terminal of the differential amplifier OP2 is connected to the line 32, and the output ΔI is negatively fed back via a feedback resistor R9.

The phase error detection circuit 13 detects the phase error between the input and output I and -I 'of the band-pass filter 11 as described above, and calculates the input I and the output ΔI from the subtraction circuit 12. Input. On the other hand, ΔI = −I +
Because of I ′, when there is a phase difference, the output ΔI is generated as shown in FIG. When the output I ′ is advanced with respect to the input I, that is, when the resonance frequency is too high, the output ΔI is advanced by 90 ° as shown in FIG. When it is late, that is, when the resonance frequency is too low, FIG.
As shown in (b), the output ΔI is delayed by 90 °. Utilizing this, the phase error detection circuit 13 outputs the output I ′
, And controls the gate voltage of the FET Q2 of the resonance frequency control section 11b in accordance with the output ΔI corresponding to the phase error.

In this phase error detecting circuit 13, FIG.
The input I as indicated by 0 (a) is input to an integrating circuit including a resistor R11 and a capacitor C4. Therefore, as shown in FIG. 10B, the terminal voltage of the capacitor C4 is delayed by 90 degrees with respect to the input I, and is input to the comparator CMP1. The comparator CMP1 compares the input voltage with a reference voltage, that is, 0 V, and outputs an in-phase output OUT.
10 (c) and FIG. 10 (d), respectively.

On the other hand, the output ΔI is determined by the resistances R12 and R1.
3, and is input to the inverting input terminal of the differential amplifier OP3 with a large time constant due to the capacitor C5. The non-inverting input terminal of the differential amplifier OP3 is connected to the line 32, and the output is divided by resistors R14 and R15 and applied to the gate of the FET Q2.
Negative feedback is provided via the capacitor C5 or the diode D1.

At the connection point between the resistors R12 and R13,
Transistors Tr of opposite polarities for bypass
1 and Tr2 are connected via diodes D2 and D3, respectively. The common mode output O is connected to the base of the transistor Tr1 via a resistor R16 and a diode D4.
UT is provided, and the opposite-phase output / OUT is provided to the base of the transistor Tr2 via the resistor R17 and the diode D5. Therefore, in response to the in-phase output OUT and the anti-phase output / OUT shown in FIGS. 10 (c) and 10 (d), the transistors Tr1 and Tr2 are turned on in FIGS.
As shown by 0 (f), conduction / cutoff is performed at the same time. When the transistors Tr1 and Tr2 are conducting, the output ΔI is bypassed, whereas when the transistors Tr1 and Tr2 are cut off, the output ΔI is input to the differential amplifier OP3.

Therefore, the output ΔI is
As shown in FIG. 10 (g), when the input I shown in FIG. 10 (a) has a waveform advanced in phase, the input to the differential amplifier OP3 forming the integrating circuit is shown in FIG. 10 (h). As shown in FIG. 10 (i), the output from the differential amplifier OP3 decreases as shown in FIG. 10 (i), the effective resistance of the FET Q2 increases, and the resonance frequency of the bandpass filter 11 decreases.

On the other hand, FIGS.
(F) respectively correspond to FIG. 10 (a) to FIG. 10 (f), and as shown in FIG.
When the phase of I lags behind the input I, FIG.
As shown in (h), the input to the differential amplifier OP3 is on the negative polarity side, and the output of the differential amplifier OP3 is
, The effective resistance of the FET Q2 decreases, and the resonance frequency of the bandpass filter 11 increases. Thus, the resonance frequency of the bandpass filter 11 can be controlled by the phase error detection circuit 13.

As described above, the amplitude error detection circuit 14 has an amplitude error between the input I and the output I ′ of the band-pass filter 11, and as shown in FIG. When the output I ′ is large, that is, when the output ΔI is positive, it is determined that the gain of the bandpass filter 11 is too large, and as shown in FIG.
When the output I ′ is small and the output ΔI is negative, it is determined that the gain is too small, and the gate voltage of the FET Q1 of the amplitude control section 11a is controlled in accordance with the output ΔI.

Therefore, the amplitude error detection circuit 14
Similarly to the phase error detecting circuit 13, the input I and the output ΔI
Compare with However, in the phase error detection circuit 13,
While the input I is input via an integrating circuit consisting of a resistor R11 and a capacitor C4, that is, with a phase delayed by 90 °, in the amplitude error detection circuit 14, the input I is connected to a voltage dividing resistor R21. , R22. The output of the comparator CMP1a is also inverted, and the in-phase output OUTa is given to the transistor Tr1a, and the opposite-phase output / OUTa is given to the transistor Tr2a. The rest of the configuration is the same as that of the phase error detection circuit 13, and corresponding portions are denoted by the same reference numerals with the suffix a. However, parameters such as the resistance value and the capacitance are not necessarily the same.

FIGS. 13 and 14 are waveform charts for explaining the operation of the amplitude error detection circuit 14. FIG. FIG.
(A) and the input I shown in FIG.
The divided voltage output from the resistors R21 and R22 is as shown in FIG. 13 (b) and FIG. 14 (b). As a result, the in-phase output OUTa of the comparator CMP1a becomes as shown in FIG. 13C and FIG.
a is as shown in FIGS. 13D and 14D. Further, the transistor Tr1a is turned on / off as shown in FIGS. 13 (e) and 14 (e), and the transistor Tr2a is also operated in conjunction therewith, as shown in FIGS.
Conduction / interruption is performed as shown in FIG.

Here, when the output ΔI has the same phase as the input I shown in FIG. 13A as shown in FIG. 13G, that is, when I ′> I, the input ΔI
As shown in FIG. 13 (h), the positive polarity component is input to the differential amplifier OP3a via the transistors Tr1a and Tr2a. Therefore, the differential amplifier OP
The output voltage of the bandpass filter 11a decreases as shown in FIG. 13 (i), thereby increasing the effective resistance value of the FET Q1 of the amplitude control section 11a of the bandpass filter 11, and reducing the maximum amplitude of the bandpass filter 11. Become smaller.

On the other hand, as shown in FIG. 14 (g), when the output ΔI has the opposite phase to the input I shown in FIG. 14 (a), that is, when I> I ′, the differential amplifier OP3a 14 (h), the output of the differential amplifier OP3a becomes negative as shown in FIG.
(I), the effective resistance value of the FET Q1 decreases, and the maximum amplitude of the bandpass filter 11 increases.

As described above, the ground fault voltage change relay 1 can detect a ground fault as shown in FIG. 6 from the level and phase of the output ΔI corresponding to the voltage change amount Δ ↑ V. it can.

The present invention is not limited to the above-mentioned GIS, but can be suitably applied to an extra high voltage or high voltage system in which the line voltage is high and the cost and the installation space of the PT and GPT pose problems. Further, the present invention can be applied not only to a three-phase power system but also to a two-phase power system.

Further, as described above, the voltage change Δ
If the detection sensitivity becomes too high due to the increase of ΔV, the inter-terminal voltage Vd may be input via a divider realized by a voltage dividing resistor or the like. Instead of using an analog circuit such as the band-pass filter 11 and the subtraction circuit 12 for calculating the voltage change amount Δ 量 V, one cycle delay and subtraction may be performed by a digital circuit.

[0059]

As described above, according to the method for detecting a ground fault in a power system according to the present invention, the capacity of the coupling capacitor connected to the transmission line of each phase is determined by the number of phases n and n-1 phases. The remaining one-phase is formed k times, the voltage change between the terminals of the voltage dividing capacitor ↑ Vd due to the ground fault is taken as 2k + 1 times, and the voltage change Δ 変 化 V between the terminals before the occurrence of the ground fault 絡A phase change with respect to Vdo is also detected.

Therefore, as compared with the case where a ground fault is detected by single-phase voltage detection, the voltage change Δ ↑ V can be expanded to 2k + 1 times, and a phase change can be detected.
Even when the magnitude of the inter-terminal voltage ΔVdg after the occurrence of the ground fault is within the set value, when the voltage change amount Δ ↑ V including the phase change is larger than a predetermined set value, a ground fault has occurred. And the accuracy of the determination can be improved.

[Brief description of the drawings]

FIG. 1 is a line block diagram for explaining a ground fault detection method according to an embodiment of the present invention.

FIG. 2 is a voltage vector diagram in a steady state for explaining a ground fault detection method according to the present invention.

FIG. 3 is a diagram illustrating a ground fault detection method according to the present invention;
It is a voltage vector diagram at the time of a phase ground fault.

FIG. 4 b illustrates a ground fault detection method according to the present invention.
It is a voltage vector diagram at the time of a phase ground fault.

FIG. 5 is a voltage vector diagram showing a change in inter-terminal voltage ΔVdg with respect to a change in a ground fault phase and a ground fault rate, for explaining a ground fault detection method according to the present invention.

FIG. 6 is a diagram illustrating an example of a ground fault determination area according to the present invention.

FIG. 7 is a block diagram showing an electrical configuration of a ground fault voltage change relay to which the ground fault detection method shown in FIGS. 1 to 6 is applied.

FIG. 8 is an electric circuit diagram showing a specific configuration for detecting a voltage change amount in the ground fault voltage change relay.

FIG. 9 is a vector diagram for explaining a phase error detection operation by the phase error detection circuit shown in FIGS. 7 and 8;

FIG. 10 is a waveform chart for explaining the phase error detection operation of the phase error detection circuit shown in FIG. 9 and the resonance frequency control operation of the band-pass filter corresponding to the detection result.

FIG. 11 is a waveform chart for explaining the phase error detection operation shown in FIG. 9 by the phase error detection circuit and the resonance frequency control operation of the band-pass filter corresponding to the detection result.

FIG. 12 is a vector diagram for explaining an operation of detecting an amplitude error by the amplitude error detection circuit shown in FIGS. 7 and 8;

FIG. 13 is a waveform chart for explaining the amplitude error detection operation shown in FIG. 12 by the amplitude error detection circuit and the amplitude control operation of the band-pass filter corresponding to the detection result.

FIG. 14 is a waveform diagram for explaining the amplitude error detection operation shown in FIG. 12 by the amplitude error detection circuit and the amplitude control operation of the band-pass filter corresponding to the detection result.

FIG. 15 is a block diagram illustrating a typical prior art ground fault detection method.

FIG. 16 shows an example of the ground fault detection method shown in FIG.
FIG. 5 is a voltage vector diagram for explaining a terminal voltage ΔVdg at the time of a 50% phase ground fault.

17 is a voltage vector diagram showing a change in inter-terminal voltage ΔVdg with respect to a change in a ground fault phase and a ground fault rate in the ground fault detection method shown in FIG.

FIG. 18 is a block diagram for explaining another ground fault detection method according to the related art.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Ground fault voltage change relay 2 Signal line 3 Check circuit 5 Oscillation circuit 6 Input filter 11 Bandpass filter 11a Amplitude control unit 11b Resonance frequency control unit 11c Filter unit 12 Subtraction circuit 13 Phase error detection circuit 14 Amplitude error detection circuit 16 Level detection Circuit 17 Drive circuit Ca, Cb, Cc coupling capacitor Cd voltage dividing capacitor La, Lb, Lc charging conductor

Claims (1)

[Claims] A coupling capacitor is connected to the transmission line of each phase, and a voltage dividing capacitor is interposed between the neutral point of the coupling capacitor and the ground. In a method of detecting a ground fault in a system, the capacity of an n-1 phase coupling capacitor is defined as
A method for detecting a ground fault in a power system, wherein the capacity is formed to be k times the capacity of the remaining one-phase coupling capacitor, and a voltage change due to the ground fault is taken out as 2k + 1 times.