JPH10224709A - Display controller and television receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To allow a television receiver to display a plurality of duplicated lines with a small amount of hardware. SOLUTION: A display memory 13 stores a character string to be displayed in the unit of lines, and a character memory 17 stores character fonts. A start line memory 204 stores a display start line for each line stored in the display memory 13. A display line selection section 7 allows line number latches 213-216 to latch a number of a line to be displayed on a current horizontal line indicated by a line counter 206 and provides an output of the latched line numbers to a memory control section 11 with priority via a line number selector 234. In-line line latches 243-246 in cooperation with a selector 280 and an adder 281 count in-line line numbers of the line numbers latched by the corresponding line number latches 213-216 and provide an output of the result to a memory control section 15 via a selector 235.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a so-called on-screen display function for displaying operation data and information of a device as characters and graphics on a display screen, and more particularly, to display information on a television display screen. The present invention relates to a display control method, a display control device, and a television receiver.

[0002]

2. Description of the Related Art Video equipment such as a television receiver and a video tape recorder (hereinafter, abbreviated as VTR) includes guide information for setting device states and operation settings such as channel display, volume display, timer reservation, and the like. Screen Display (On Screen Displa
y, hereinafter abbreviated as OSD) function.

In the conventional television receiver, if there is an OSD function for displaying channel switching and volume adjustment by a remote control device on a screen, there is no major problem in operation of the television receiver.

In recent years, the aspect ratio of an image has been reduced to the conventional 4: 3
From now on, wide broadcasting of 16: 9 has begun, and a television receiver having a wider angle of view has come to be preferred. Such a wide-screen television receiver incorporates a two-screen television that displays two images on one screen and a super live function that naturally fits a 4: 3 video image to a 16: 9 screen, and the like. Was.

[0005] Further, with the digitalization of CS broadcasts and broadcasts, broadcast programs on a large number of channels have been provided, and have more functions than conventional television receivers. For this reason, for example, the number of buttons on the operation panel is increased for the operation of the remote controller, and the operation is complicated.

When the functions of such a complicated television receiver are described in an instruction manual, the number of pages of the instruction manual is greatly increased, and it takes time to find and understand a target function. It was necessary to keep the instruction manual for a long time, and it was especially avoided by elderly people and young people.

Therefore, a method of incorporating a help function used in a personal computer or the like into a video device such as a television receiver has been studied. In addition, there are attempts to provide a demonstration display that introduces many functions included in the device.

A display control circuit for realizing the OSD function used in a television receiver or the like has been devised to display a wide variety of information with small-scale hardware in order to realize the display control circuit at low cost. Was.

An example of a circuit configuration of such a conventional display control device is shown in a block circuit diagram of FIG. This display control device is a display control IC (product name: TMP8) manufactured by Toshiba Corporation.
7CS38N). This configuration realizes changing the character size to be displayed on a line-by-line basis, and makes it possible to express characters of different sizes by enlarging one character font. In addition, when large characters are displayed, there are lines that are hidden at a fixed line spacing, so that the line spacing changing function allows the line spacing to be set freely and does not increase the storage capacity of the display memory. Have been added.

In FIG. 12, a conventional display control device 12 is shown.
Reference numeral 01 denotes a display clock (abbreviated as display CLK in the figure) input terminal 1, a horizontal synchronization signal (abbreviated as H in the figure) input terminal 3, a vertical synchronization signal (abbreviated as V in the figure) input terminal 5, and a display row. Selecting section 1207, frequency dividing circuit 9, memory control section 11,
It comprises a display memory 13, a memory control unit 1215, a character memory 17, a P / S conversion circuit 19, a decoration circuit 21, and a coloring circuit 23.

The horizontal synchronizing signal input terminal 3 and the vertical synchronizing signal input terminal 5 are terminals for inputting a horizontal synchronizing signal and a vertical synchronizing signal, respectively.
A terminal for inputting a display clock which is a reference clock having a cycle corresponding to the display time per dot.

The frequency dividing circuit 9 divides the frequency of the display clock,
A digit number to be displayed is generated and given to the memory control unit 11.

The display memory 13 has, for example, 12 rows × 24
It is a character string storage memory having a storage capacity of digits (= 288 characters). Each character stored in this display memory is stored in a character code along with its attribute data and color designation information.

The memory control unit 11 includes a display selection unit 1207
In accordance with the row number given by the subroutine and the digit number given by the frequency dividing circuit 9, the reading control of the character code and the accompanying information stored in the display memory 13 is performed.

The character memory 17 includes a display memory 13
This is a memory for reading out a character font corresponding to the character code read out from, for example, one character is stored in 14 horizontal x 18 vertical dots.

The memory control unit 1215 operates in accordance with the character code read out from the display memory, its accompanying information, and the in-line line number given from the display line selection unit 1207.
Control is performed to read a character font from the character memory 17.

The P / S conversion circuit 19 converts a plurality of dot signals read in parallel from the character memory 17 into serial data.

The decoration circuit 21 is a circuit for performing decoration according to attribute data such as shadowing and bordering of characters. The coloring circuit 23 generates RGB color signals in accordance with the designation of the character color.

A display line selection unit 1207 selects a line number and a line in the display memory 13 to display a line number and a line in the current horizontal line indicated by the built-in line counter 206. This is a circuit section for generating an in-line line number.

For this reason, the display row selection unit 1207 includes a line counter 206 initialized by the vertical synchronization signal and counting the horizontal synchronization signal, and a row counter initialized by the horizontal synchronization signal and counting the display clock up to the maximum display row number. 2
03, a start line memory 204 for storing a horizontal line number to start displaying for each line of the display memory 13, a read output of the start line memory 204, and a line counter 206.
And a row counter 203 for comparing the output of the
, A row number latch 1293 for temporarily holding the horizontal synchronization signal (H), an in-line line counter 1295 for counting the horizontal synchronization signal (H),
Line number latch 1293 and in-line line counter 129
5, an AND gate 1291 for generating a signal for controlling 5
It is provided with.

Next, the operation of the conventional display control device 1201 will be described with reference to FIGS. 12, 13 and 14. FIG.
FIG. 13 is a diagram showing an example of a display screen by the display control device of FIG. 12, and FIG. 14 is a diagram for explaining a limitation of display control in a conventional example.

For each line of the character string stored in the display memory 13, a drawing start line, VS1, VS2,. A memory 204 is provided.

The character size is separately stored in the display memory 13 on a line-by-line basis. The display clock is a reference clock having a cycle corresponding to the display time per dot, and the display control device operates based on this clock.
The horizontal synchronization signal (H) and the vertical synchronization signal (V) are used as reference timings to synchronize with the video signal.

The maximum number of characters to be displayed by the display control device is 12 rows × 2 from the configuration of the display memory 13 described above.
4 digits = 288 characters. Each of the character patterns is composed of 14 horizontal x 18 vertical from the configuration of the character memory 17 described above.
It is composed of a dot character font.

From these conditions, if the display clock used at this time is such that the effective display period is about 50 μS for one horizontal scanning period (about 63.5 μS), the display time for one dot is the effective display period. It can be obtained by dividing by the maximum number of dots in the period,

(Equation 1) Therefore, the display clock is about 6.7 (MHz).

Generally, the display clock is 6 to 8 (MHz).
Is used. At this time, in the modification circuit 21 of FIG. 12, when a smoothing processing means for displaying an oblique line smoothly is used, the display clock is doubled to reduce the dot size displayed on the screen to 12 to 1
6 (MHz) is used. As the smoothing processing means, for example, a "smoothing circuit" disclosed in Japanese Patent Application Laid-Open No. Sho 60-202475 is known.

In FIG. 12, the horizontal synchronizing signal (H) inputted from the input terminal 3 is supplied to the line counter 206,
And input to the in-line line counter 1295 as a count input. The content of the line counter 206 is initialized for each vertical synchronizing signal (V), and the content of the count indicates the number of a line scanning one screen.

On the other hand, the row counter 203 is used to search the start line memory 204 at the beginning of each horizontal period to detect whether there is a line to be displayed in the horizontal period. is there. For this reason, the horizontal synchronization signal (H) from the input terminal 3 is input to the row counter 203 as a reset signal, reset at the beginning of each horizontal period, and from 0 to 0 at the timing of the display clock within the horizontal synchronization period. It is counted up to the maximum row number (= 12) of the display memory 13. The count value output from the row counter 203 is stored in the start line memory 204 and the row number latch 1
293.

The start line memory 204 stores a drawing start line for each line, and stores VS1, VS in FIG.
2,... VS12 are stored as the line numbers of the horizontal lines. If the value of the row counter 203 is 1, the start line memory 204 has a value of VS1.
The value of S2 is read out. The data read here is input to the comparator 205, and is compared with the output (line number) of the line counter 206. The output of the comparator 205 is supplied to a row number latch 129 via an AND gate 1291.
3 is supplied as the latch timing.

That is, the row number in the display memory 13 to be displayed on the current horizontal line indicated by the line counter 206 is held in the row number latch 1293, and the memory control unit 11
Will be supplied.

On the other hand, the display clock input from the terminal 1 is frequency-divided by the frequency dividing circuit 9 and supplied to the memory control unit 11 as a timing signal of a digit position to be displayed. The memory control unit 11 determines the position of the digit based on the digit position given by the frequency dividing circuit 9 and the row number given by the row number latch 1293.
Data written in advance from the display memory 13 by a control circuit (not shown) such as a microcomputer is read. The data is attribute designation data such as a character code to be displayed and a character color, shadow, border, or the like.

When a character code is output from the display memory 13, the data is input to a memory control unit 1215 which controls a character memory 17 storing a character font which is a display image of a character. At this time, data indicating which part of the display image of the character is to be displayed in the vertical direction is given from the in-line line counter 1295, and one part of the required character display image is read from the character memory 17. The read data is converted into serial data by the P / S conversion circuit 19, modified by the modification circuit 21, and converted into RGB color signals by the coloring circuit 23.

Signal Ys output from modification circuit 21
Is a signal for designating the distinction between a character portion and a blank portion, and this signal is used to switch between the output from the display control signal and the video signal. Some of these signals simply function as switches, while others have control signals for realizing a transparent function of mixing a display control signal and a video signal at a certain level.

The in-line line counter 1295 is initialized by a timing signal supplied from the AND gate 1291, and counts up at the timing of the horizontal synchronizing signal (H) input from the terminal 3. The in-line line counter 1295 indicates which line of the currently displayed line is being displayed, and outputs a signal (a) indicating that the currently specified line is being displayed. The gate 1291 is controlled to prohibit the start of display of another line before the display of one line is completed.

Next, the operation when the display of a plurality of lines is specified at the same position on the screen in duplicate will be described with reference to the screen display image of FIG.

In this example, before the display of the first line in which the display start line is specified by VS5 ends, there is a second line in which the display start line is specified by VS2, and the second line in which the display start line is specified by VS2. This shows a case where the display start line of the third line is designated before the display ends.

When such overlapping display designation is made, the conventional display control device continues to display the character of the line designated by VS5 even if the display start line of VS2 is reached, The display was ignored. At this time, VS3
Originally corresponds to the period during which the line of VS2 is displayed, but since the line display of VS2 was not executed, VS3
Was controlled to be displayed.

This is because the control signal (a) input to the AND gate 1291 for controlling the row number latch 1293 to latch the row number in accordance with the coincidence signal of the comparator 205 is set to "1" in the configuration of FIG. If fixed, VS of FIG.
14, the display prohibition process is eliminated, but VS5 and VS in FIG.
2 overlapped portion 1401 (row of VS5), VS2 and V
There is a problem that a part of the character in the area of the line portion 1402 where S3 overlaps (line of VS2) is not displayed. Therefore, an AND gate 1291 is provided in order to prevent a display in which a part of characters is missing, and a control signal (a) indicating that the in-line line counter 1295 is counting.
Controls the displayed lines so that they do not overlap.

With such a configuration, the OSD
At the design stage, the display start line had to be specified so that the lines did not overlap. Especially when displaying special capital letters, it was difficult to understand what line the next line would be, and it took time to set and adjust.

In addition, since one line is not allowed to overlap, it is necessary to store character data having different sizes in the character memory 17 in an overlapping manner. Was needed.

By the way, as to what kind of display is required in recent years, as an example, the installation of a demonstration mode for introducing functions of a television receiver as shown in FIG. 6 is being studied. .

FIG. 12 shows such a demonstration.
When executed by a conventional display control device such as
(A) to (d) are displayed in time series.
In FIG. 15, the display of “Now demoing” indicating that the mode is the demonstration mode is scrolled up from the bottom of the screen to the top of the display such as “TV function explanation” and “1,...”. It is to try to make it.

In the configuration of FIG. 12, since there is a display prohibition processing function that always displays only one line, the configuration of FIG.
As shown in (b) and (c), there is a scene where the display of “Now demoing” disappears. In other words, although it was intended to display “Now demoing” also in the areas 1501 and 1502 indicated by the dotted lines, this scene is not displayed because it overlaps with other lines.

Therefore, a display control circuit as shown in FIGS. 16 and 17 has been proposed. This is a US patent (US
P) 5,420,610. For example, the configuration of FIG. 16A is a configuration including two sets of the memory control unit 1215 and the character memory 17 of FIG. 12, and the character memory is composed of a ROM and a RAM. FIG.
The configuration is such that a priority determination circuit (10 in FIG. 16) and a synthesizing means (8 in FIG. 16) are inserted between the character memory 17 and the P / S conversion circuit 19.

With such a configuration, as shown in FIG. 16B, even if two lines overlap by one line, display of one line does not stop, and
Characters drawn on one line can be displayed in an overlapping manner.

However, this has a major problem. FIG.
6 (a) First display RAM 4 and second display RAM 1
4, and a first character ROM 5 and a second character ROM 15 exist. When these circuits are incorporated in an IC, the area occupied by the memory is large, so that the duplication of data is reduced as much as possible and the circuit is limited to a small capacity. Therefore, this configuration is not suitable for the IC.

When two character ROMs are further provided, if the same data or completely different data is not built in both ROMs for the sake of OSD creation, usable characters are limited by the overlapping condition, and the OSD is limited. There is a problem that it takes time to design and create the device.

There is a configuration shown in FIG. This is the second character ROM in FIG.
15 is omitted. In other words, the character ROMs are combined into one, and when necessary, the necessary characters are transferred from the first character ROM 5 to the second character RAM 24 for superimposed display. I have. In this way, the display shown in FIG. 17B has been realized.

In any case, it is necessary to have a corresponding character memory for realizing the superimposed display, and one memory control circuit is not configured to output one data. For this purpose, there is a problem that the memory must be increased.

In particular, there is a problem that a large chip area is required for incorporating a memory into an IC.

FIG. 18 shows another conventional example. In this example, a character font specified by a storage unit (display memory) 1 is read from a character / graphic generation unit (character memory) 2 and input to a display data generation unit 9. A display area (a) and a prohibited area (b) shown in FIG. 19 are stored in the display area storage unit 10, and are displayed on the display surface 7 or 6 or 8 on the final display example shown in FIG. The display area data of FIG. 19 is read by designating whether or not to perform.

The display area data read from the display area storage section 10 is given to the display data generation section 9. The display data generator 9 reads out the currently displayed OSD from the display buffer 3 at any time and outputs the OSD to the display 5. The image data in the display buffer is also returned to the display data generator 9, and a new OSD is added to the display buffer as necessary, and a new OSD is output to the display buffer. A newly created OSD is initialized by prohibiting feedback from the display buffer 3.

This method is similar to bitmap processing used in personal computers and the like. In this case, although the superimposed display can be freely performed, the capacity of the display data generator 9 and the display buffer 3 increases, and the circuit becomes a large-scale circuit, which is not suitable for being incorporated in a television receiver. In particular, since a display buffer is used, in order to improve the quality of a character to be displayed, it is necessary to reduce an area on the screen where one piece of data is displayed, and a thin data display cannot be performed without more memory. There is a problem.

Further, according to this method, since data is written to the display buffer, the processing speed for reading and writing data from and to the memory becomes a problem. It would be good if one picture was displayed for a certain period of time, but it was not suitable for instantaneously rewriting the entire screen. In order to realize this method, a personal computer or the like has a method in which the display buffer 3 is doubled or more, writing and displaying are performed separately, and switching is performed.

That is, in the case of the bitmap format, not only does the memory capacity increase, but also the quality of displayed characters depends on the capacity of the bitmap memory.

Assume that the display clock is (6.7 'MHz)
Assuming that the effective display period is 50 (μS), the number of cycles in clock units in the horizontal direction is approximately 336 (= 14 dots × 24 digits). One field of the NTSC system of television is 262.5 lines, of which 216 lines (= 18 dots × 12 lines) are used by the display control circuit. Assuming that the data "1" and "0" are "present" and "absent" in the display and that the data is in 1-bit units of memory, a memory of 72,576 bits (= 336.times.216 lines) is required. That is, there must be an 8 Mbit memory. What is displayed at this time is "Yes"
And "none", it is not possible to color each bit.

The memory capacity of the display control circuit so far cannot be limited because there are various types. However, the character font is horizontal 14 × vertical 18 dots and has 256 characters, and the display memory has 24 digits × 12. Assuming that there is an area for setting line, character modification, color specification, etc., it is composed of 18 bits,

## EQU2 ## The capacity of the character memory is 64,512 bits = horizontal 14 dots × vertical 18 dots × 256 characters, and the capacity of the display memory is 5,184 bits = 24 digits × 12 rows × 18 bits.

In a configuration using a bit map memory, a character memory is also necessary, and it is possible to reduce the display memory by converting it to a format that describes the arrangement and the like when displaying each character in a microcomputer program. 5,184
Just a bit. If the screen data to be displayed is colored in bit units, three screens for R, G, B

## EQU3 ## 72,576 (bits / surface) × 3 (surface) = 21
7,728 (bit) memory is required.

Also, with such a large-capacity memory, it takes time to update the data, and the display cannot be switched instantaneously.

[0060]

As described above,
A control circuit that is built into a video device such as a television receiver and displays characters and graphics on the screen of the television receiver is a small-scale circuit and is required to display high-quality characters and graphics. However, in the conventional display control circuit, the display in which even one line overlaps with one line cannot be performed due to a problem that a graphic in a portion of the overlapped line is missing.

In order to display the overwriting, a method of preparing a character superimposed in advance in a character memory or using two or more display control circuits has been considered. There was a problem of becoming.

Further, a method of using a bitmap memory used in a personal computer or the like is also used. However, in consideration of the quality of the characters to be displayed, an unprecedented large-capacity bitmap memory is added. In addition, a circuit for controlling the memory is required, and there is a problem that the scale of the display control circuit becomes too large for use in video equipment such as a television receiver.

In view of the above problems, it is a main object of the present invention to improve the quality of characters and the like displayed on the screen without increasing the memory capacity, and to improve the display capability such as overlapping display of characters. It is to provide a control device.

Further, according to the present invention, in a display control apparatus capable of designating a display start line for each line of the display memory, which line of a character is drawn for each line, and which character is overlapped with a character of another line, By providing a means to determine whether to draw the characters in the line first,
It is an object of the present invention to prepare a font in which a plurality of characters are duplicated in advance, and to realize a display in which characters are duplicated without having a bitmap memory.

[0065]

In order to achieve the above object, the present invention provides a display memory comprising a plurality of lines each storing a character string to be displayed on a screen in a line unit comprising a plurality of digits. A start line memory for storing a horizontal line number at which display of the content is to be started for each line, a character memory for storing a character font in a dot matrix format, and characters from the display memory based on vertical and horizontal synchronization signals. Character reading means for reading;
A display control device comprising: a font reading unit that reads a character font corresponding to the read character code from the character memory; and a signal conversion unit that converts the read character font from a parallel signal to a serial signal. In the above, when a plurality of rows to be displayed on a certain horizontal line are designated, priority determination means for determining which row has a higher priority for each digit, based on a determination result of the priority determination means. And control means for controlling the contents of a line with a higher priority to be displayed on the horizontal line.

Further, in the present invention, the priority determining means may determine, at a digit position where the character to be displayed in the line with the highest priority is a blank, the highest priority from the line displaying the non-blank character. Rows can be selected.

Further, in the present invention, there is further provided switching means for switching a plurality of serial signals in units of display clocks based on priorities, and the font reading means is configured to display different lines in different lines within one character display period in the horizontal direction. The specified character font is read a plurality of times, the signal conversion means converts the character fonts read a plurality of times from parallel signals to serial signals, and the switching means is converted by the signal conversion means, respectively. It is possible to control to switch a plurality of signals in units of display clocks based on the priority.

(Operation) By judging the priority order of the lines to be displayed with priority for each digit of each horizontal line, the order of superposition when a plurality of lines are superimposed and displayed is distinguished, and Can be prevented from being cut off.

Also, since the in-line number is counted for each line being drawn, when the display of the other line having the higher priority is completed, the remaining portion of the other line having the lower priority can be displayed. .

Further, since only a means for determining the priority for each horizontal line is added to the conventional display control device, an increase in the circuit scale can be suppressed very slightly. OSD can be displayed.

[0071]

Next, an embodiment of a display control device according to the present invention will be described in detail with reference to the drawings. FIG.
1 is a circuit configuration diagram showing a configuration of a first embodiment of a display control device, and FIG. 2 is a detailed circuit diagram of a main part of the display control device.

For simplicity of the following description, unless otherwise specified, a code given to a certain component and an output signal of the component are given as a pair. For example, when the reference numeral 202 is assigned to the frequency dividing circuit, the reference Sg 202 is applied to the frequency-divided clock output from the frequency dividing circuit 202.

In FIG. 1, the display control device 101 has a display clock (abbreviated as display CLK in the figure) input terminal 1.
, Display row selection unit 7, frequency division circuit 9, memory control unit 1
1, a display memory 13, a memory control unit 15, a character memory 17, a P / S conversion circuit 19, and a decoration circuit 2.
1 and a coloring circuit 23. In addition,
Components having the same functions as the components of the conventional display control device shown in FIG. 12 are denoted by the same reference numerals.

The display control device 101 according to the present embodiment
The components different from the two conventional display control devices are a display line selection unit 7 and a memory control unit 15 that controls reading of the character memory 17. Other components are
It has the same function as the conventional example of FIG. When the display control device according to the present invention is applied to a television receiver, the display control device is connected to a display device such as a CRT via a switching circuit or a superimposing circuit for switching the output between a video signal and a coloring circuit after the coloring circuit. do it.

The display clock input terminal 1 is a terminal for inputting a display clock which is a reference clock having a cycle corresponding to a display time per dot, which is also provided to the frequency dividing circuit 9 and the display row selecting section 7. Has been distributed.

The frequency dividing circuit 9 divides the frequency of the display clock,
A digit number signal indicating which digit of the line to be displayed is to be displayed is generated and given to the memory control unit 11.

The display memory 13 is, for example, 16 rows × 24
This is a memory having a storage capacity of digits (= 384 characters), which stores characters and symbols to be displayed on the screen as character codes, and also includes attribute data and color designation information as accompanying information of the characters for each line. It is remembered.

The memory control unit 11 controls the reading of the character code stored in the display memory 13 and its accompanying information in accordance with the row number given by the display row selecting unit 7 and the digit number given by the frequency dividing circuit 9.

The character memory 17 is a display memory 13
This is a memory for reading out a character font corresponding to the character code read out from, for example, one character is stored in 14 horizontal x 18 vertical dots.

The memory control unit 15 controls the character memory 17 according to the character code read from the display memory 13 and the in-line line number given from the display line selection unit 7.
To control the reading of character fonts from.

The P / S conversion circuit 19 converts a plurality of dot signals read in parallel from the character memory 17 into serial data.

The decoration circuit 21 is a circuit for performing decoration in accordance with attribute data such as shadowing and bordering of characters. The coloring circuit 23 generates RGB color signals in accordance with the designation of the character color.

The display row selector 7 stores the display memory 1 in the current horizontal line indicated by the built-in line counter 206.
3 is a circuit unit for generating a line number and an in-line line number in order to select which of the three lines to display.

For this reason, the display row selection unit 7 includes a line counter 206 initialized by the vertical synchronization signal and counting the horizontal synchronization signal, and a signal obtained by dividing the display clock by the maximum display row number (in the case of the present embodiment). 16), and a start line memory 204 for storing a horizontal line number to start displaying for each line of the display memory 13
And the output of the start line memory 204 and the line counter 2
, A comparator 291, a selector 280, four in-line line latches 243 to 246, and an in-line line selector 235,
The configuration includes an adder 281 and control units 291 and 293.

The difference between the display row selection unit 7 and the conventional display row selection unit (for example, 1207 in FIG. 12) is that a large number of rows can be displayed on the same horizontal line. In order to display the contents of the line selected from the plurality of lines according to the priority, a plurality (4 in the present embodiment) is displayed.
Row number latches 213, 214, 215, and 216, and operate as in-line line counters corresponding thereto, respectively.
246. In-line line latch 24
3, 244, 245, and 246 cooperate with the selector 280 and the adder 281 to realize the functions of four sets of in-line line counters.

The display line selection unit 7 sends a signal for designating a display line to the memory control unit 11 for controlling the display memory 13 and a memory control unit 15 for controlling the character memory 17 to determine which line of the character to be displayed is to be read. Outputs the specified signal.

The display clock for operating the display control device is used as a reference clock for operating each block and is input from the terminal 1 to the frequency dividing circuit 9, and the frequency dividing circuit 9 determines the horizontal position of the character to be displayed, that is, the digit. It is converted into a signal indicating the position. The signal indicating the digit position output from the frequency dividing circuit 9 is input to the memory control unit 11.

The memory control unit 11 uses a signal indicating a display line and a signal indicating a digit position provided by the display line selection unit 7 to place a microprocessor (not shown) at the column position of the line specified by the display memory 13. The data written in the display memory 13 is read from the system control means.

By the way, the system control means such as a microprocessor means a microprocessor, a ROM and a RAM.
And may control the entire television receiver by a command description for controlling the microprocessor stored in the ROM, or may control only the display control circuit, and may include a synchronization signal obtained from the television signal. A control circuit that operates at the timing of (1) and controls only the display control circuit may be used.

The data stored in the display memory 13 includes a character code for designating where the character to be displayed is stored in the character memory 17, and the color of the character to be displayed, the background color, There are bordering, shadowing, underlining designation, blink designation, dot-colored character or character, character size, and whether or not to perform smoothing processing.

The decoration designation does not always include all functions depending on the specifications of the display control device. However, in the present invention, the internal configuration of the decoration circuit 21 in the configuration shown in FIG. 1 may be limited or may have more functions.

The data read from the display memory 13 is stored in the memory controller 1 for controlling the character memory 17.
5 is input. The memory control unit 15 includes a display row selection unit 7
A signal for specifying the line of the character to be read is also given.
7, one line of data of one character is read out. The bit width of the read data is determined by limiting the read time by the access time of the character memory 17 and minimizing the circuit scale of the P / S conversion circuit 19.

The read data (part of the character font) is converted by the P / S conversion circuit 19 into serial data corresponding to the scanning of the television signal on a display clock basis and output, and is trimmed by the decoration circuit 21. , Shadowing, smoothing, etc.
Output RGB signals as color signals specified by

The Ys signal output from the modification circuit 21 is
A signal instructing switching between a signal output from the display control device 101 and a video signal of a television receiver or the like,
For example, when displaying numbers that mean channel numbers, etc.,
Numeric font data has a value of “1” or “0”, for example, is represented by a group of 14 × 18 points.

When “1” is a numeral portion and “0” is treated as a background, such a Ys signal is provided in the background portion so that the video signal can be seen in display clock units. This signal may be a signal for completely switching and scanning and a signal for controlling the amount of mixing with the video signal.

FIG. 2 is a circuit diagram showing a detailed configuration example of the display row selecting section 7 which is a main part of the display control apparatus 101. In the figure, a display row selection unit 7 includes a frequency dividing circuit 202, a row counter 203, a start line memory 204, a comparator 2
05, the line counter 206, and the row number latch 21
3, 214, 215, 216 and a row number selector 234
, Selector 280, in-line line latches 243, 24
4, 245, 246, an in-line line selector 235,
An adder 281, a control unit 291, and a control unit 293 are provided. Note that the same components as those shown in FIG. 1 are denoted by the same reference numerals, and duplicate descriptions will be omitted.

The control unit 291 has four row number latches 21
3 to 216 and 4 in-line line latches 243 to 24
6 is a control unit for generating an update timing signal common to 6 and holding a line number at which display is started until display is completed.

For this purpose, the control unit 291 controls the comparator 20
7, 222, and pulsing circuits 208, 209, 210
AND gates 217 and 218 and OR gate 219
, NAND gate 220, latches 223, 224, and 2
25, 226 and selectors 230, 231, 232, 2
33 and an adder 221.

The control section 293 is a control section mainly for sequentially counting up the in-line line number corresponding to each line where the display is started until the display of each line is completed.

For this purpose, the control unit 293 controls the latch 25
3, 254, 255, 256 and selectors 260, 26
1, 262, 263 and the last line decoder 282 in the row.
It is comprised including.

Next, the operation of the display row selecting section 7 shown in FIG. 2 will be described with reference to the timing chart of FIG. FIG. 3 shows a timing chart when the number of rows in the display memory 13 is up to 16.

The display row selection section 7 starts operating based on the horizontal synchronizing signal (H). First, the horizontal synchronization signal (H)
Thus, a signal “counter enable” 201 that determines a horizontal blanking period and determines a period during which the display row selection unit 7 operates is generated. This “counter enable” 2
With 01, the row counter 203 operates at the timing of the divided clock Sg202 obtained by dividing the display clock by the dividing circuit 202.

In the present embodiment, a divided clock Sg202 obtained by dividing the display clock by the dividing circuit 202
Is used as the count input of the row counter, but any timing clock that can sequentially read data from the start line memory 204 that stores the start line of each display row may be used, and a display clock may be used.
However, as a matter of course, if the row counter 203 changes from “0” to “1” during the horizontal blanking period in the example of FIG.
Must count to 6 ".

During the operation period of the row counter 203, the priority of a row to be displayed in a horizontal line to be displayed is determined.

Now, the display row selecting section 7 of FIG. 2 operates as follows. First, at the timing (not shown) of the vertical synchronizing signal (V), the data held by all the latches (or flip-flops) of the display row selection unit 7 in FIG.
Cleared. The start line memory 204 is not cleared at the timing of the vertical synchronization signal.

When the video period starts in the vertical direction, the display row selecting section 7 starts operating. The row counter 203 starts counting by “counter enable” 201 generated based on the horizontal synchronization signal (H). At this time, the start line memory 204 is sequentially addressed by the counter value sequentially output from the row counter 203, and the display start line number of the corresponding row is sequentially output. The comparator 205 compares the output start line number with the current line number obtained from the line counter 206.

If the comparison results are equal, the comparator 205 outputs a signal indicating the coincidence, and the signal is converted into the set timing pulse (A) 211 of the latches 213 to 216 by the pulsing means 209. Then, the latch 213 holds the counter value output from the row counter 203 by the timing pulse (A) 211.

If the other lines are set to display characters from the same line, the line to be displayed is detected by the comparator 205 while the line counter 203 continues to operate, and the timing pulse (A) 211 is changed. able to make. Then, every time a row to be displayed is found, the data of the latch 215 is shifted to 216, the data of 214 is shifted to 215, and the data of 213 is shifted to 214.

At this time, in this embodiment, the latch
Since only three lines 216 to 216 control the FIFO, if a line to be displayed more than that is found, the data of the line found first is lost.
That is, in this example, the one with the larger line number has the highest priority. In the configuration of FIG. 2, the row number is "1".
To “16”, and “0” means no designation.

Here, the number of latches is 213 to 216, but the number of latches may be increased to the maximum number (16 in the case of 16 lines shown in the timing chart of FIG. 3). Since it is necessary to always read the display memory 13 during the reading process, there is a case where the display row selection unit 7 can hold the data but cannot perform the display processing due to the memory read timing of the display memory 13. Conversely, the number of the latches may be reduced to two or three.

Next, the case where the display moves to a different line will be described. The data held in the latches 213 to 216 in FIG. 2 are switched so that the selectors 230 to 233 select the outputs of the latches 213 to 216, respectively, while the timing signal of the data holding pulse 270 in FIG. 3 is “Low”. . Thereby, each of the latches 213 to
216 are connected so as to be input to the latches 223 to 226, respectively, and are copied to the latches 223 to 226 at the timing of the latch CLK271.

At this time, similarly, data holding pulse 270
, The selectors 260 to 263 are controlled to copy the data of the latches 243 to 246 to the latches 253 to 256, respectively. This latch 243-2
Reference numeral 46 holds an in-line number which is the number of display lines of each line currently displayed.

Since the data held in the start line memory 204 is the display start line of each line, if the display is shifted to the next line, the data will be different,
Will be inconsistent. Therefore, the latch 243
By holding the line numbers of the displayed lines in .about.246, it is possible to prevent the character whose display has been started from being lost in the middle.

The latches 223 to 226 to which the data has been copied from the latches 213 to 216 holding the displayed row number operate as follows.

When the data held by the latch 226 is "0", that is, when there is no overlap of the row to be displayed, there is data only in the latch 223, and the others are "0". Therefore, as shown in the timing chart of FIG.
Thereafter, it is provided until the next horizontal retrace period starts.

In the case of the embodiment, it is sufficient that the minimum display clock is for three cycles.

In FIG. 3, after the row counter 203 operates, the data holding pulse 270 is issued, and the values of the latches 213 to 216 are copied to the latches 223 to 226, and the data sequential transfer period starts, the OR gate 219 is turned on.
It is determined whether the data held in the latch 226 is “0”.

If "0", a pulse for sequentially transferring the data of the latch 223 to the right is generated, and the latch 22
This is repeated until the row number appears in 6 or the data in the latch 223 is transferred.

In this embodiment, when the timing pulse is generated three times, the data in the latch 223 is transferred to the latch 226. In other words, the data may be transferred by generating a pulse that is less than or equal to the number of latches and waiting for the start of the next line and the operation of the row counter 203.

Further, the comparators 205 and 207 perform the comparison process only during the period when the counter enable signal is “High”, and in the other periods, a mismatch result is output. Then, during the operation period of the row counter 203, it operates correspondingly.

Here, it is determined whether the data held in the latches 223 to 226 is "0" or not.
9 and if it is "0", the pulsing circuit 21
The timing pulse (B) 212 of the latches 223 to 226 is generated by 0, and the data held by the latches 223 to 226 are sequentially transferred to the right latch. This operation is performed at the same cycle as the row counter 203, and the timing pulse (B) is output from the pulse generator 210.
212 is generated. At this time, the latches 253 to 256 perform the same operation in parallel.

During the count period of the row counter 203, the value held by the latch 226 and the value of the row counter
Is compared by the comparator 207, and if they match, the pulsing circuit 208 generates a timing pulse (A) 211 for sequentially transferring the data held by the latches 213 to 216 and 243 to 246 to the right latch. . The output of the comparator 207 is also provided to the selector 280.

By the way, the line number in each line is counted from 0. Thus, the management of the line number of the display row selection circuit 7 is performed as follows.

As described above, the comparator 205 determines that the line number output from the start line memory 204 and the value output from the line counter 206 match based on the line number output from the line counter 203. When this occurs (this is the row start line), the row number at that time is stored in the latch 213, and “0” is given to the latch 243 from the selector 280. The selector 280 is normally configured to input “0” to the latch 243.

Now, during the period of the timing signal of the data holding pulse 270 shown in FIG.
To 3, the value in latch 243 is copied to latch 253.

When moving to the next line, the row counter 203 operates in the same manner. However, no coincidence pulse from the comparator 205 appears this time, and the value of the latch 223 is sequentially transferred to the latch 226, where it is transmitted. When the comparator 207 determines that the stored row number and the value of the row counter 203 match, the row number is stored in the latch 213 again. The value of the latch 253 is stored in the latch 256.
Is transferred in the same way as the value of

According to the signal generated from the comparator 207,
The selector 280 adds “1” to the data held in the latch 256 by the adder 281 and newly holds the data in the latch 243.

Finally, when each row being displayed reaches the last line in the row, the data of the latch 226 corresponding to the displayed row is cleared to "0". The determination as to whether or not this is the last line is performed by comparing the result of addition by the adder 281 with the last line number in the in-line last line comparator 282.

The in-line last line comparator 282 is a circuit for displaying the value to which "1" has been added by the adder 281 and the number of lines constituting one character, for example, a character stored by 14 × 18 dots. In this case, the value is compared with a value of "18". This means that when displaying the character displayed on the "18" line, the last line is "17" because the line number is expressed from "0" here.

Therefore, since the line to which "1" is added becomes unnecessary, the data of the latch 226 is cleared when the output of the adder 281 becomes "18". Therefore, the data stored in the latch 226 may be cleared when the number of lines actually displayed is increased by "1".

To explain the timing of this clearing a little more, the row number is held in the latch 226 and the line number is held in the latch 256 simultaneously by the timing pulse (B).

The data held in the latch 256 is added with “1” by the adder 281, and the in-row last line comparator 282 determines whether or not the data is the last line. If it is the last line, the row number which is the data of the latch 226 is cleared to "0". In this embodiment, the line number "0" is not specified, that is, the line number to be displayed is not held. The clear terminal of the latch 226 is an asynchronous clear terminal and is cleared by a short pulse regardless of the clock cycle.

When the row number issued from the row counter 203 matches the data held in the latch 226, the comparison result is also output from the comparator 207. In order to generate a pulse signal, a signal having a width of at least one cycle of a display clock must be input.

However, after the line number is held in the latch 256, the adder 281 and the in-line last line comparator wait until the data in the latch 226 is cleared by the signal issued by the last line in-line comparator 282. 2
Since it is only the internal circuit delay of 82, it is equal to nothing compared to the cycle width of the display clock.

When the value of the latch 226 is cleared, a signal is generated by the OR gate 219 and the timing pulse (B) is given from the pulsating circuit 210.

This timing will be further described with reference to the timing chart of FIG. The counter value generated from the row counter 203 is equivalent to two cycles of the display clock. Therefore, this period is divided into four periods,
3 and 4. Assume that the timing at which data is held in the latches 226 and 256 changes from the period 3 to the period 4.
Assuming that the circuit delay of the adder 281 and the in-row final line comparator 282 takes one period, the data is held in the latches 226 and 256, and the period becomes period 4.

The row counter 203 is counted, and when the next cycle starts, the result that the data held in the latch 256 is determined to be the last line by the in-row last line comparator 282 appears under a new counter value. The data in the latch 226 is cleared in the period 1, and the pulse generator 210 generates a “0” pulse between the periods 2 and 3. And period 4
, New data will be held in latches 226 and 256.

If it is not the last line, the data held in the latches 226 and 256 during the period 3 to 4 is counted up by the comparator 207 after the end of the period 4 and held by the comparator 207. The row number is compared with the current row number. If they match, the row number is held in the latch 213 and the new line number of the row is held in the latch 243. If the line numbers do not match, the change in the counter value is monitored until the line numbers match.

For example, when the display of the row of the number held in the latch 214 ends, the contents of the
After shifting to 26, the data is cleared to "0". The data in the latches 213 to 216 and 223 to 226 are cleared for each line at the timing of the data clear 272 in FIG.

With such a configuration, display line selection processing and priority setting are always performed for each line. When there is no overlapping display row, data is always supplied to the latches 213 and 243 and does not enter the latches 214 to 216 and 244 to 246, but the data copied to the latch 223 is transmitted through the latches 224 and 225. Is sent to the latch 226, and is compared with the value of the row counter 203 by the comparator 207 which compares the content of the latch 226 with the row counter 203, and adds 1 to the content of the latch 243 by the coincidence signal of the comparator 207. It counts the number of lines.

Next, how the lines and line numbers to which the priorities are assigned are selected during the video display period will be described with reference to FIG.

"Counter enable" 201 is "Hig
The row to be displayed during the period "h" is selected, for example, in the line A, the fourth, eighth, tenth, and fifteenth rows are selected from among the rows from "1" to "16". The fourth example in the display example
In the row, “A □□□ O”, in the eighth row, “□□ U”, in the tenth row
It is assumed that “□” is specified in the line and “□□□” is specified in the 15th line. (“□” means a blank.) When the lines to be displayed and their priorities are determined by the display line selecting section 7, “a”, “b”, “c” are used in this order in descending order of priority. "," D ". And
During the display period, the display row selection unit 7 and the memory control units 11 and 15 switch the display memory 13 from the one with the highest priority to the selectors 234 and 235 of FIG. Is read, and it is checked whether or not there is data to be displayed.

The priority control by the memory control units 11 and 15 is such that if the contents of the digit in the line with the higher priority are blank, the contents of the digit in the line with the lower priority are sequentially read out. This is performed by latching data which is a character code.

For example, in the case of FIG. 4, four rows are selected, and a row having data to be displayed is searched from the four rows. In FIG. 4, "a" specified in the fourth line having the lowest priority is found, and the corresponding character font is read from the character memory 17.

Unless processing such as smoothing is particularly performed, data reading is performed only once and the character memory 1
There is a cycle that does not read 7. The data read out here is converted into serial data by the P / S conversion circuit 19, and is displayed on a display means such as a CRT via the decoration circuit 21 and the coloring circuit 23.

In the line B, only two lines, ie, the tenth line and the fifteenth line, are selected to be displayed, and the same processing as the line A is performed.

In the data reading of the display memory 13 during the display period, if the data to be displayed is read out from the one with the highest priority and the data to be displayed is found, the process of stopping the data reading of the lower order row may be added. Absent.

According to this embodiment, even if the lines to be displayed overlap, the characters themselves can be displayed without missing if the digit positions are different. For example, character positions can be shifted in the vertical direction and arranged as in the display example shown in FIG.

If the characters overlap each other, the display is as shown in FIG. 8C. This FIG.
The display example of (c) is the P example in the configuration example of FIG.
Since the / S conversion circuit 19 and the decoration circuit 21 correspond to only one row, only one row having a high priority can be processed.
Does not appear on the screen.

In the conventional display control device, this is prohibited, but if overlapping of lines is permitted, FIG.
As shown in (b), characters are missing. FIG.
(C) In a display control device having a small number of colors, it is sometimes difficult to see a display as shown in FIG. However, since the characters on the rear side are not displayed and the characters do not overlap, the display control device with a small number of colors does not make the characters difficult to read.

FIG. 5 is a circuit diagram showing the configuration of the second embodiment of the display control device. The second embodiment is different from the first embodiment in that P / S conversion circuits 19a, 19b,
And two modification circuits 21a and 21b are provided in parallel, respectively, and a priority switching unit 25 for controlling which output of the modification circuits 21a and 21b is selected and output is also newly provided.

According to this embodiment, the display shown in FIG. 8D, which cannot be displayed in the first embodiment, becomes possible. However, even in this example, when three or more lines are overlapped, the display in which the characters themselves overlap is up to two lines, and the third line is as in the first embodiment. If the number of pairs of the P / S conversion circuit and the modification circuit is increased, the P / S conversion circuit and the decoration circuit can be further overlapped.

If the character size to be displayed on each line is fixed, the priority switching section 25 determines the priority of the set of the P / S conversion circuit 19a and the modification circuit 21a as the P / S conversion circuit 19b. There is a method of setting the priority higher than the priority of the combination with the decoration circuit 21b. According to this method, the circuit of the priority switching unit 25 can be configured to be the smallest.

However, the character size is set in the character memory 1
There is a case where one character data is enlarged and displayed by a control signal due to a capacity problem of No. 7. Therefore, the set of the P / S conversion circuit and the decoration circuit performing the enlarged display processing continues the processing as it is, and only the other performs the display processing according to the priority. In this case, the set of one P / S conversion circuit and the modification circuit is fixed, and the other line may change the priority order with the line displaying the large characters. Therefore, the priority switching unit 25 determines the highest display point among the display points that are overlapped according to the priority order previously assigned to the display row, and outputs the same to the coloring circuit 23. This is switched for each point data in units of one clock, and characters overlapping on the screen are displayed.

For example, as shown in FIG. 6, when the television receiver has a demonstration processing function for introducing the function of the television receiver itself, the demonstration processing function must be executed. Is displayed in such a manner that the message "Now demoing" is scrolled up from the bottom of the screen to the top. FIG. 6 shows the scroll-up operation in a chronological order by changing the screen display examples from (a) to (d).

The display memory is divided in units of rows.
Each is assigned a priority. As described in the description of the display row selection unit 7 in the first embodiment, in this example, the priority order is low for small numbers and high for high numbers. This prioritization is merely performed in this order for the sake of explanation, and the configuration may be reversed. For example, to reverse the order, the row counter 20 of FIG.
It can be realized by replacing 3 with a down counter.

As a method of inserting data to be stored in the start line memory 204, the number of the line to be displayed and the line number at which the display is started are stored, so that the program creator operating the display control device can freely set the priority order. Can also be changed. In this case, the circuit configuration in FIG. 2 is such that the counter value output from the row counter 203 is input to the latch 213, the comparator 207, and the start line memory 204 as the number of the row for displaying.

If the setting of the priority order can be changed, the number of the line to be displayed is stored in the start line memory 204 in addition to the line number for starting the display. In this configuration, the output of the row counter 203 is given only to the start line memory 204.

The line number for starting display, which is one of the outputs of the start line memory 204, is determined by the comparator 0205.
To output the number of the line to be displayed on the other side. The row number changes the output and connection of the row counter 203 as an input to the latch 213 and the comparator 207 in FIG. With this configuration, the display line selection unit can control the superposition of the lines to be displayed in accordance with the priority order specified by the program creator that controls the display control device.

Since the priorities are assigned to the respective rows as described above, the display screen shown in FIG. 6 has the highest priority in the 16th row in which the “☆” mark is described as shown in FIG. Moving this line draws it above any other line. Just like the mouse pointer used in personal computers, it can be moved without being hidden by other characters.

[0161] The message "Now demoing" is described on the tenth line, and the message that passes under other character strings is exemplified. That is, the "TV function explanation" displayed on the twelfth line
And the display on the third line. Since the priority order is simply set in advance for each line, it is only necessary to determine what line is to be written in the OSD design. The order of the rows, that is, the first row and the second row may be displayed at a higher position on either screen.

Therefore, what should be noted when designing an OSD is to determine which display is to be displayed on which character string, and the layout can be freely determined.

In the second embodiment, up to two lines, characters in each line can be displayed on the screen in an overlapping manner. For example, when a display as shown in FIG.
The character "TV" is used as a screen design, and if you select a color that is close to the background or a color that makes the character string you want to read "Wide Clear Vision Broadcasting" to stand out, the characters are superimposed. Can improve the image on the screen.

In particular, a character such as an icon of a different image can be created and displayed not only by combining icons such as an icon display character used in a personal computer such as a dot-colored character but also by superimposing them.

It should be added that the two lines can be displayed completely overlapped with each other, but the display of FIG. 8C can also be made by stopping one set of the P / S conversion circuits. is there.

FIG. 9 is a circuit diagram showing the configuration of the third embodiment of the display control device. In the third embodiment, the P / S conversion circuits 19a and 19b of the second embodiment
The conversion circuit and the delay correction circuit are replaced with P / S-delay correction circuits 35a and 35b which are integrated, and a horizontal position correction amount circuit 31 for detecting and controlling the correction amount of the horizontal position is added. This is a configuration for improving the problems remaining in the first and second embodiments.

When the standard size characters and the enlarged large characters are displayed in a superimposed manner in the embodiments described above, for example, when the three size characters in the frame 1000 in FIG. May have occurred.

For example, in the case of the first embodiment, FIG.
(A) Three types of characters 1001, 1 having different sizes shown in FIG.
002 and 1003 with the character 1001 at the top as shown in 1010 in FIG.
There is a problem that the portion indicated by (x) is not displayed when the display is attempted to be superimposed on 3. This occurs when a process of replacing one character font with several sizes is performed. In the case of the second embodiment, 1 in FIG.
As shown at 020, characters up to two lines can be overlapped, but the character at (x) is missing the character as in FIG. 10B.

FIG. 10 (c) shows why this is the case.
The description will be added by showing the overlapping order of the characters (f) and (f). The part (x) is “2” and “3” in FIG. 10C according to the first embodiment, that is, the priority is the second or third priority. In the first embodiment, since the P / S conversion circuit and the decoration circuit are one set, when processing of one row is performed, processing of another row cannot be performed.

In particular, in the case of using enlarged characters, since blocks constituting large characters are not combined,
Both large and small characters read data at the same timing. Therefore, when the display of the line with the higher priority is started, it is necessary to read the data of the large character and the character of the standard size at the same timing.

When characters are enlarged and displayed, both standard size characters and large characters are read out at the same timing, and P / S
The point is enlarged by extending the time for displaying one point by the conversion circuit. For this reason, there is a problem that the enlarged character data cannot be read out even after the display of the upper character is completed, and that even if it is read out, the display timing does not match because the data is converted into serial data by the P / S conversion circuit. there were.

In this embodiment, the horizontal position deviation of each row is detected by the horizontal position correction amount circuit 31 for detecting and controlling the horizontal position correction amount, and the P / S-delay correction circuit 35 is used.
The delay amount is corrected by a and b. For example, when displaying the portion (x) in FIG. 10B, the data at the left end is deleted by the P / S-delay correction circuits 35a and 35b, and the delay amount of the remaining data is corrected. Then, character deletion is prevented by superimposed display including correction of each line. By adding this correction means, a display as shown in FIG. 11 can be made.

Since the display control device according to the present invention has the above-described configuration, display such as superposition can be easily realized without increasing the character memory capacity or making the circuit scale too large. be able to. Also,
Since the data display control is performed for each line in the field, the displayed screen can be rewritten instantaneously by rewriting the data in the display memory which specifies where and what to display. The display quality of the character can be improved by extending the function of the modification processing such as the smoothing processing.

Furthermore, even if display of different lines is started from the same line, display control is performed in accordance with a predetermined display priority order, so that characters can be easily arranged in the positional relationship of characters that could not be displayed until now. Thus, in the design of the OSD, it is possible to draw without worrying about the positional relationship between the characters.

By combining characters, it is possible to express more figures and characters that can be expressed with fewer characters.

[0176]

As described above, according to the display control device of the present invention, a display memory consisting of a plurality of lines, a character memory for storing a character font, and the display of the contents of each line of the display memory are displayed. When a plurality of lines to be displayed on a certain horizontal line are designated, a display control device having a start line memory for storing a horizontal line number to be started determines which line has a higher priority. The apparatus further includes a priority determination unit, and a control unit that controls, based on the determination result of the priority determination unit, to display the contents of a line with a higher priority on the horizontal line. In addition to enabling display, characters that are colored in dot units and smoothing processing to improve the quality of characters can be displayed simultaneously and overlapped. Shimesuru content and quality there is an effect that dramatically improved.

According to the display control device of the present invention,
In the character memory, data duplication can be eliminated, so that there is an effect that a large amount of data can be stored in a small memory capacity.

Furthermore, according to the television receiver to which the present invention is applied, a high-quality OSD can be displayed with a small-scale circuit, so that the operation information of the television receiver having complicated functions can be easily understood. There is an effect that it can be provided.

[Brief description of the drawings]

FIG. 1 is a circuit diagram illustrating a display control device according to a first embodiment of the present invention.

FIG. 2 is a detailed circuit diagram of a main part of the first embodiment.

FIG. 3 is a timing chart illustrating an operation of a main part of the first embodiment.

FIG. 4 is a diagram illustrating the operation of the first embodiment.

FIG. 5 is a circuit diagram illustrating a display control device according to a second embodiment of the present invention.

FIG. 6 is a diagram showing an example of an OSD display according to the second embodiment.

FIG. 7 is a diagram illustrating an example of display memory allocation (a) and an example of a display screen (b) thereof in the second embodiment.

FIG. 8 is a diagram illustrating another display example according to the second embodiment.

FIG. 9 is a circuit diagram illustrating a display control device according to a third embodiment of the present invention.

FIG. 10 is a diagram illustrating an improvement according to the third embodiment.

FIG. 11 is a diagram showing a display example according to the third embodiment.

FIG. 12 is a circuit configuration diagram of a conventional example of a display control device.

FIG. 13 is a diagram for explaining designation of a display start line position by a conventional display control device.

FIG. 14 is a diagram illustrating a limitation on display control in a conventional example.

FIG. 15 is a display example according to a conventional example (for comparison with FIG. 6).

FIG. 16 is a diagram showing a configuration diagram (a) and a display example (b) of another conventional example.

FIG. 17 is a diagram showing a configuration diagram (a) and a display example (b) of another conventional example.

FIG. 18 is a configuration diagram of a conventional example using a memory equivalent to a bitmap memory.

FIG. 19 is a bitmap diagram in the conventional example of FIG. 18;

20 is a diagram showing a display example in the conventional example of FIG.

[Explanation of symbols]

101: display control device, 1: display clock input terminal, 3
... horizontal synchronizing signal (H) input terminal, 7 ... display row selection unit, 9
... frequency divider circuit, 11 ... memory control unit, 13 ... display memory,
15: memory control unit, 17: character memory, 19:
P / S conversion circuit, 21: decoration circuit, 23: coloring circuit, 2
01: frequency dividing circuit, 203: row counter, 204: starting line memory, 205: comparator, 206: line counter, 213, 214, 215, 216: row number latch,
234: row number selector, 235: in-line line selector, 243, 244, 245, 246 ... in-line line latch, 280 ... selector, 281 ... adder, 291, 29
3. Control unit.

Claims (6)

[Claims] 1. A display memory consisting of a plurality of lines each storing a character string to be displayed on a screen in a line unit consisting of a plurality of digits, and a horizontal line number to start displaying the contents of each line of the display memory A starting line memory for storing
A character memory for storing a character font in a dot matrix format; character reading means for reading characters from the display memory based on vertical and horizontal synchronization signals; and a character font corresponding to the read character code from the character memory. When a plurality of rows to be displayed on a certain horizontal line are specified in a display control device including a font reading unit to be read and a signal conversion unit that converts the read character font from a parallel signal to a serial signal, A priority determining unit that determines, for each digit, which line has a higher priority, based on the determination result of the priority determining unit, the content of the higher priority line is displayed on the horizontal line. A display control device, further comprising: control means for controlling. 2. The method according to claim 1, wherein the priority determining means selects a line having the highest priority from the lines displaying non-blank characters at the column position where the character to be displayed on the line having the highest priority is blank. The display control device according to claim 1, wherein: 3. The display control device according to claim 1, wherein the order specified in the start line memory is a priority of a line displayed on the same horizontal line. 4. The system further comprises switching means for switching a plurality of serial signals in units of display clocks based on priority, wherein said font reading means is designated on different lines within one horizontal character display period. The character font is read a plurality of times, the signal conversion unit converts the character font read a plurality of times from a parallel signal to a serial signal, and the switching unit converts the plurality of signals respectively converted by the signal conversion unit. 2. The display control device according to claim 1, wherein control is performed so as to be switched in units of display clocks based on priority. 5. The apparatus according to claim 1, further comprising horizontal position means for changing a horizontal position at which display is started for each line of said display memory, reading a specified character font from said character memory, and setting a horizontal position with a character on another line. 3. The display control device according to claim 2, wherein the position is corrected for each display clock. 6. A television receiver comprising the display control device according to claim 1. Description: