JPH10224402A - Data transfer method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain the sure and highly reliable transfer of data between the equipments connected together via a serial interface with use of a limited receiver by transferring synchronously the data enciphered by means of the prescribed relative data and also transferring asynchronously the relative data to a specific equipment. SOLUTION: A system controller 15 reads the data 22 out of a buffer memory and inputs them to an adder 34. The adder 34 adds the data 22 to the relative data stored in a relative data storage register 33 and outputs them to a multiplexer 20 as the enciphered data 35. The controller 15 controls an input/ output data switching register 19 to switch the output of the multiplexer 20 between the data 35 and the relative data 36 stored in the register 33. The controller 15 also outputs the control signals 23, 26 and 27 to an IEEE1394 interface part 21 to switch the data transfer mode between the synchronous and asynchronous transfer modes.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial interface device for a computer peripheral device, and more particularly to a method for transferring data between devices using the serial interface.

[0002]

2. Description of the Related Art In recent years, SSA, Fiber Channel, and IEEE have been replaced by parallel interfaces such as SCSI which are main interfaces of computer peripheral devices.
Serial interfaces such as 1394 have been developed and are receiving attention. Each company is researching and developing peripheral devices compatible with the above interface, aiming at the industry standard.

In the above interface, since data transfer is performed serially, there are few factors that hinder speeding-up, such as crosstalk between data signals and variations in signal delay, as seen in a parallel interface, and high-speed transfer is possible. Interface is expected. Further, since the instruction system uses the conventional SCSI instruction set, there is an advantage that existing device drivers can be easily ported. In particular, the IEEE 1394 interface has a mode that is conscious of data transfer requiring real-time properties, and is expected as an interface suitable for multimedia applications.

[0004] The present invention provides an I
The present invention relates to a data transfer method of the IEEE 1394 interface. Here, an example of a DVD device will be described.

FIG. 17 shows a configuration of a DVD data reproducing system. DVD disk 2 by optical pickup 1
Is supplied to the RF amplifier circuit 3. The RF amplifier circuit 3 extracts a focus error signal and a tracking error signal from the output of the optical pickup 1, supplies the focus error signal and the tracking error signal to the focus / tracking control circuit 4, and amplifies the RF signal to the level slice / PLL circuit 5.
Supply signal. The level slice / PLL circuit 5 obtains a binary signal of the obtained RF signal and generates a PLL clock 6 synchronized to read the signal. The binarized signal is supplied to the DVD signal processing circuit 7.

In the synchronization detecting section of the DVD signal processing circuit 7, P
Using the LL clock 6, a periodic synchronization signal 8 caused by the format is detected. The detected synchronization signal 8 is supplied to a disk motor control circuit 9. The disc motor control circuit 9 compares the frequency and phase of the supplied reproduction synchronizing signal 8 having a time-axis variation with the frequency and phase of the clock signal 11 having a fixed period obtained by dividing the frequency of the signal from the fixed clock generation circuit 10. The components are extracted, converted to a voltage, amplified, and fed back to the disk motor 12.

The signal demodulation section of the DVD signal processing circuit 7 uses the PLL clock 6 and the synchronization signal from the synchronization detection section to supply the signal 2 supplied from the level slice / PLL circuit 5.
The value signal is decoded, and data is written to the buffer RAM 13 using the PLL clock 6. Next, data is read out from the buffer RAM 13 by the clock 11 having a fixed period, corrected, and then re-read.
Write to 13. At this time, the time axis fluctuation component caused by the disk motor 12 is absorbed (jitter absorption). The data subjected to the correction processing is read out from the buffer RAM 13 by the clock 11 having a constant period, and transferred to the host computer by the I / F control circuit 14.

The system controller 15 controls a control signal 16
To control the operation of the entire disk system, such as search, ON / OFF of the operation of each circuit, and interface circuit control. The search instruction signal 16 is a feed motor control circuit 17
The feed motor control circuit 17 supplies a control signal to a feed motor 18.

The I / F control circuit 14 will be described in more detail. FIG. 18 shows a conventional serial interface.
1 shows an example of a data transfer control system. The system controller 15 is the same as that shown in the overall system diagram of FIG.

The system controller 15 switches the output of the multiplexer 20 by writing to the input / output data switching register 19 to select data to be output to the IEEE 1394 interface 21. When data from the buffer RAM is selected, the corrected data 22 is output to the IEEE 1394 interface unit 21. Alternatively, the data 22 from the host computer is output to the buffer RAM. When the system data bus 23 is selected, writing of control data to the IEEE1394 interface unit 21 and reading of registers are performed.

IEEE 1394 interface unit 21
Performs parallel-to-serial conversion of data between the host and the system, generates an arbitration signal, generates an interrupt signal 24 to the system controller 15, and the like.

A read / write pulse generation circuit 25 decodes a read / write signal 26 and an address signal 27 output from the system controller 15, and writes / reads to / from each register in the system and a control signal 28.
Is generated.

[0013] When data is exchanged between the devices connected as described above, an asynchronous communication is performed.
Two data transfer modes called a "nous" mode and an isochronous mode are provided. FIG. 19 shows the state of the transfer. In FIG. 19, the state of each data transfer is divided for the sake of simplicity, but data is actually exchanged on the same bus line.

The isochronous mode is a mode in which a period for periodically transferring data is guaranteed, and is an effective mode for a device requiring a constant data transfer speed. Asynchronous mode is a conventional parallel interface SCSI (Small Computer System Interface).
This is the same as that used in (rface), in which each peripheral device arbitrates and the device that has acquired the right to use the bus transfers data to the target device.

In the isochronous mode, a device called a cycle master manages the transfer cycle, and the node having the highest priority usually becomes the cycle master, so that the bus occupation right can always be acquired by arbitration. The cycle master outputs a start packet to the bus by broadcast transfer at regular intervals. IEEE
When the E1394 interface unit 21 detects the start packet, it performs arbitration, and transmits the data on a predetermined specific channel (here, channel 2). The channel number is described in a format including data, and the receiving node monitors the channel number and takes in target data.

On the other hand, in the asynchronous mode, the IEEE
The E1394 interface unit 21 outputs a signal for competition for the right to use the bus called normal arbitration to the host bus. If the arbitration is won, a transfer request signal is transmitted to the receiving device, and data is exchanged while performing handshake with the receiving device. In this mode, the result of arbitration is determined by the priority of each device, so that devices with lower priorities cannot always be connected when necessary. Therefore, a certain data transfer rate cannot always be satisfied. Asynchronous mode transfer is performed in the remaining asynchronous mode transfer cycle after the completion of the isochronous mode transfer.

As described above, in the isochronous mode, data is transmitted by broadcast transfer in order to satisfy a certain data transfer rate. Therefore, the data to be transferred is read freely by monitoring and selecting the channel number on the receiving side, and the response of the receiving device to the transferred data, that is, a handshake signal such as an acknowledgment or a response packet does not intervene. For this reason, data transferred in the isochronous mode can be read by any peripheral device, and there is a problem in transfer data security that data cannot be transmitted only to a specific node using this mode.

[0018]

The use of the isochronous mode as described above makes it possible to perform a data transfer which is not influenced by the priority of the connected peripheral devices and which guarantees a constant transfer rate. Since the transfer in the isochronous mode is a broadcast transfer in which handshaking is not performed between the transmitting and receiving devices, data can be read out by all the receiving devices, and the security of the transferred data cannot be ensured. Was.

The present invention has been made to solve such a problem, and enables data transfer with limited receiving devices while guaranteeing a constant data transfer rate between devices connected through a serial interface. The purpose is to provide a data transfer method.

Another object of the present invention is to provide a highly reliable data transfer method that enables more reliable data transfer with limited receiving devices between devices connected via a serial interface.

[0021]

In order to achieve the above object, the present invention provides a method for transferring data between devices connected via a serial interface, according to the present invention. Is encrypted using predetermined related data, and the encrypted data is transferred synchronously and the related data is transferred asynchronously to a specific device.

According to the present invention, the transfer data is encrypted and transferred synchronously, and related data necessary for decrypting the encrypted data is transferred asynchronously to a specific device. Although the encrypted data is received by all devices, the acquisition of related data required to decrypt the encrypted data is limited to only specific devices, so a fixed data transfer by synchronous type transfer that specified the receiving device Data transfer at a rate can be realized, and security can be improved.

According to a second aspect of the present invention, in a data transfer method between devices connected through a serial interface, data to be transferred is arbitrarily selected from a plurality of related data. The encrypted related data is encrypted, and the encrypted data is transferred synchronously and the related data is transferred asynchronously to a specific device.

According to the present invention, since the related data used for encryption can be freely changed, the probability that the related data can be detected by a device other than the specific device specified by the transmitting side is reduced, and the receiving device is specified. The security of the synchronous data transfer can be further enhanced.

According to a third aspect of the present invention, there is provided a method for transferring data between devices connected through a serial interface, wherein the data periodically including a unique bit pattern includes a plurality of related data. One of them
And selectively encrypting the encrypted data, transmitting the encrypted data synchronously, and asynchronously transmitting a plurality of related data to a specific device.

According to the present invention, since the relevant data for decrypting the encrypted data can be specified from the bit pattern of the encrypted data itself on the receiving side, the relevant data can be changed for each synchronous transfer cycle of the encrypted data. As compared with the method of asynchronously transferring related data, restrictions on changing related data can be reduced.

Further, according to the present invention, in a data transfer method between devices connected through a serial interface, data to be transferred is selected from a plurality of related data. The encrypted data is encrypted and transferred synchronously, and a plurality of related data are asynchronously transferred to a specific device. Each time the related data is changed, information on the change of the related data is transmitted to the specified device. It is characterized by asynchronous transfer.

According to the present invention, as in the third aspect of the present invention, when the transmitting side changes the related data during the transfer of the encrypted data, the temporal correspondence between the transfer of the encrypted data and the transfer of the related data is achieved. And it is possible to reduce restrictions on changing related data. Further, according to the present invention, in a data transfer method between devices connected via a serial interface, data to be transferred is selectively used by using one of a plurality of related data. The encrypted data is transferred synchronously, and a plurality of related data are asynchronously transferred to a specific device. When the related data is changed, information on the change of the relevant data is transferred asynchronously to the specific device. Then, a response to the related data change information from the specific device is confirmed, and the related data on the transmission side is changed.

According to the present invention, the related data change timings of the transmitting side and the receiving side can be matched, and
After confirming that the specific device on the receiving side has correctly received the information on the change of the related data, the related device on the transmitting side is changed, so that more reliable data transfer is realized.

Further, according to the present invention, in a data transfer method between devices connected via a serial interface, data to be transferred is selectively selected from one of a plurality of related data. When the related data is changed, the information related to the change of the related data is asynchronously transferred to the specific device. After the pattern transfer, a response to the related data change information from the specific device is confirmed, and after a predetermined time has elapsed, the related data on the transmission side is changed.

According to the fifth aspect of the present invention, if the time from when the response data is received by the transmitting side until the start packet of the next synchronous transfer is output is short, the related data is transferred to the next synchronous transfer cycle. In some cases, it may not be possible to make the change before entering the device in time, but in the present invention, the response from the specific device is confirmed, and after a predetermined time has elapsed, the relevant data on the transmitting side is changed (and Similarly, the specific device on the receiving side also returns the response data and then changes the related data after a predetermined time has elapsed.) Therefore, the synchronous transfer cycle for changing the related data is performed after receiving the response from the receiving device. This can be fixed to the cycle after the predetermined number of cycles, and the timing of changing the related data on the transmission side and the reception side can be more reliably matched.

According to the present invention, in a data transfer method between devices connected via a serial interface, data to be transferred is selected from a plurality of related data. The encrypted data is encrypted and transferred synchronously, a plurality of related data are asynchronously transferred to a specific device, and each time the related data is changed, a predetermined agreement is established with the specific device. It is characterized in that information on a change of related data composed of a bit pattern is transferred synchronously.

According to the present invention, even when transfer data does not include a fixed bit pattern that is periodically repeated, synchronous transfer of related data change information limited to receiving devices can be realized, and the related data change information can be synchronized. By performing the type transfer, the related data can be changed every synchronous transfer cycle of the encrypted data. Thus, the restriction on the change of the related data can be reduced as compared with the method of transferring the related data asynchronously.

Further, according to the present invention, in a data transfer method between devices connected through a serial interface, data is transferred synchronously and a channel used for the synchronous transfer is set. It is characterized in that the channel designation information for designation is asynchronously transferred to a specific device.

According to the present invention, by transferring transfer channel designation information to a specific device asynchronously, it is possible to prevent devices other than the specific device from taking in the transfer data without encrypting the transfer data. it can.

According to a ninth aspect of the present invention, in a data transfer method between devices connected via a serial interface, data is transferred synchronously and a channel used for the synchronous transfer is set. It is characterized in that the channel designation information for designation is asynchronously transferred to a specific device, and after a response to the channel designation information from the specific device is confirmed, the channel on the transmission side is changed.

According to the present invention, the change timing of the transfer channel between the transmitting side and the receiving side can be matched, and it is confirmed that the specific device on the receiving side has correctly received the information regarding the change of the transfer channel. Since the transmission channel of the transmission side is changed after that, more reliable data transfer is realized.

According to a tenth aspect of the present invention, in a data transfer method between devices connected through a serial interface, data is transferred synchronously and a channel used for the synchronous transfer is set. It is characterized in that the channel designation information for designation is asynchronously transferred to a specific device, a response to the channel designation information from the specific device is confirmed, and after a predetermined time has elapsed, the channel on the transmission side is changed.

In the ninth aspect of the present invention, if the time from when the response data is received by the transmission side to when the next synchronous transfer start packet is output is short, the transfer channel is set to the next synchronous transfer cycle. In some cases, it may not be possible to change the transmission channel before entering the network. However, in the present invention, the response from the specific device is confirmed, and the transmission channel on the transmission side is changed after a predetermined time has elapsed (and Similarly, the specific device on the receiving side also returns the response data and then changes the transfer channel after a predetermined time has elapsed.) Therefore, the synchronous transfer cycle for changing the transfer channel is performed after receiving the response from the receiving device. It can be fixed to the cycle after a predetermined number of cycles, the transfer channel change timing between the transmitting side and the receiving side can be more reliably matched, and more reliable data transfer It is realized.

[0040]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing the configuration on the transmitting side of the serial interface / data transfer control system according to the first embodiment.

In this embodiment, a related data storage register 33 and an adder 34 are added to the conventional system shown in FIG.

Before starting the data transfer, the system controller 15 writes the related data used for encrypting the transferred data into the related data storage register 33. When performing data transfer, the system controller 15 reads the data 22 from a buffer memory of a device (not shown) serving as a data generation source in response to a data transfer request signal 28, and inputs the data 22 to the adder 34. The adder 34 adds the data 22 and the related data in the related data storage register 33, for example, and outputs the result to the multiplexer 20 as encrypted data 35.

The system controller 15 controls the input / output data switching register 19 to control the multiplexer 2
0 is switched between the encrypted data 35 and the related data 36 in the related data storage register 33,
The control signal 2 is transmitted to the IEEE1394 interface unit 21.
3, 26 and 27 are output to switch the data transfer mode between the isochronous (synchronous transfer) mode and the asynchronous (asynchronous transfer) mode. That is,
As shown in FIG. 2, control is performed so that the encrypted data is broadcast-transferred on a specific channel (here, channel 2) in the isochronous mode, and related data is transmitted to the specific receiving device in the asynchronous mode. I do.

In FIG. 2, the related data is transferred in the asynchronous mode during the empty period of the isochronous mode transfer cycle of the encrypted data. However, the related mode transfer of the related data is performed before the start of the transfer of the encrypted data. You may go to. FIG. 3 is a diagram showing the configuration of the receiving side of the serial interface / data transfer control system of the present embodiment.

IEEE 1394 interface section 21
Receives the transfer data, it gives an instruction signal 24 regarding the data reception to the system controller 15. When receiving the instruction signal 24, the system controller 15
The register in the EE1394 interface unit 21 is read to determine whether the received data is isochronous data or asynchronous data. The system controller 15 switches the output of the multiplexer 20 through the input / output data switching register 19 based on the determination result so that the encrypted data is latched in the encrypted data latch circuit 39 and the related data is latched in the related data latch circuit 40, respectively.

The adder 34 is provided for the encrypted data latch circuit 3
For example, the associated data latched by the associated data latch circuit 40 is subtracted from the encrypted data latched by 9 to decrypt the encrypted data, and the decrypted data is output to the buffer memory of the receiving device.

As described above, according to the present embodiment, the transfer data is encrypted and transferred in the isochronous mode, and the related data necessary for decrypting the encrypted data is transferred in the asynchronous mode. Therefore, although the encrypted data is received by all the receiving devices, the acquisition of the relevant data required to decrypt the encrypted data is limited to only a specific device. Therefore, data transfer at a constant data transfer rate in the isochronous mode in which the receiving device is specified can be realized, and security can be improved.

Next, a second embodiment of the present invention will be described.

FIG. 4 is a diagram showing the configuration on the transmitting side of the serial interface / data transfer control system according to the second embodiment.

In this embodiment, a multiplexer 42 for switching related data and a related data switching register 43 are added to the configuration of the first embodiment shown in FIG. A plurality of types of related data are written in the related data storage register 33 before the start of data transfer.

The system controller 15 selects any relevant data 41 from a plurality of types of relevant data written in the relevant data storage register 33, and selects an adder 34.
The multiplexer 42 is controlled through the associated data switching register 43 so as to output the data to the multiplexer 20.

The transfer data 22 is encrypted by the adder 34 using the related data 41 selected by the multiplexer 42, and is transmitted through the multiplexer 20 to the IEEE1394.
The data is output to the interface section 21 and transferred as encrypted data in the isochronous mode. The related data 41 selected by the multiplexer 42 is transferred in the asynchronous mode.

The serial interface of the present embodiment
The configuration and operation of the receiving side of the data transfer control system are the first.
The description is omitted because it is the same as that of the first embodiment.

According to the present embodiment, since the related data can be changed during the transfer of the encrypted data, the probability that the related data can be detected by a device other than the specific device designated by the transmitting side is reduced, and The security of data transfer in the isochronous mode in which a device is specified can be further enhanced.

Next, a third embodiment of the present invention will be described.

For example, reproduction data of a CD, DVD, etc.
Data having a unique bit pattern such as synchronous data appears periodically. When predetermined related data is added to such unique bit pattern data, the data of the unique bit pattern portion becomes bit pattern data corresponding to the related data.

In this embodiment, for example, as shown in FIG.
Three types of related data A, B, and C are prepared in advance, data is encrypted using any of the related data, and the encrypted data is transferred in the isochronous mode. As described above, since the encrypted data periodically includes the portion 47 of the unique bit pattern corresponding to the related data, the receiving side detects the portion 47 to obtain the encrypted data decryption data. Related data can be specified.

The serial interface of the present embodiment
The transmitting side of the data transfer control system is almost the same as that of the second embodiment shown in FIG. 4, but the related data A, B and C held in the related data storage register are transferred before the encrypted data is transferred. The second embodiment differs from the second embodiment in that data is transferred to a specific device in the asynchronous mode.

Next, the receiving side of this embodiment will be described with reference to FIG.

When various related data are received by the IEEE 1394 interface unit 21, the system controller 15 causes the related data latch circuit 40 to latch the related data in the input / output data switching register 19.
The switching of the multiplexer 20 is controlled through the switch. Thereafter, the system controller 15 reads each related data latched by the related data latch circuit 40, and sets a unique bit pattern (for example, CD or DV) for each related data.
A bit pattern corresponding to the related data is created as comparison data by, for example, addition with a synchronization data bit pattern such as D, and the comparison data for each related data is written to the comparison data storage register 48.

Thereafter, when the system controller 15 determines that the encrypted data has been received by the IEEE1394 interface unit 21, the multiplexer through the input / output data switching register 19 causes the encrypted data to be latched by the encrypted data latch circuit 39. 20 is switched and controlled. Thereafter, the comparison circuit 49 compares the encrypted data latched by the encrypted data latch circuit 39 with each comparison data written in the comparison data storage register 48. Here, if a part of the encrypted data matches one of the comparison data, it can be specified that the related data corresponding to the matched comparison data is the related data for decrypting the encrypted data.

The system controller 15 specifies the related data for decrypting the encrypted data in this manner, and sends the relevant data from the plurality of related data stored in the related data latch circuit 40 to the adder 34. The multiplexer 51 is switched and controlled through the related data switching register 50 so as to output the data.

The adder 34 is provided for the encrypted data latch circuit 3
9 from the encrypted data latched in
The encrypted data is decrypted by subtracting the related data selected through, and the decrypted data is output to the buffer memory of the receiving device.

In the second embodiment, when the related data is changed during the transfer of the encrypted data on the transmission side, it is necessary to take time correspondence between the transfer of the encrypted data and the transfer of the related data. Although data modification involves various restrictions, in the present embodiment, the related data for decrypting the encrypted data can be specified from the bit pattern of the encrypted data itself on the receiving side. Restrictions on changing related data can be eliminated, for example, related data can be changed every type transfer cycle.

Next, a fourth embodiment of the present invention will be described.

FIG. 7 is a diagram showing the configuration on the transmitting side of the serial interface / data transfer control system according to the fourth embodiment.

In this embodiment, a related data change information storage register 52 is added to the system of the second embodiment shown in FIG. In the related data change information storage register 52, related data change information indicating change of related data on the transmission side together with identification information of related data of a change destination is written in advance. The system controller 15 transfers each related data held in the related data storage register 33 to the specific device in the asynchronous mode before the start of the transfer of the encrypted data or in the isochronous mode transfer cycle of the encrypted data.

When the system controller 15 wishes to change the related data during the transfer of the encrypted data, the system controller 15 changes the output of the multiplexer 20 from the encrypted data of the adder 34 to any related data change information in the related data change information storage register 52. And the data transfer mode is switched from the isochronous mode to the asynchronous mode, and the related data change information is transferred to the specific device in the asynchronous mode.

Next, the receiving side of this embodiment will be described with reference to FIG.

During the transfer of the encrypted data, the IEEE 1394
The related data change information received by the interface unit 21 is latched by the related data change information latch circuit 53. Immediately thereafter, the system controller 15 reads the related data change information latched by the related data change information latch circuit 53.

Here, it is assumed that a plurality of pieces of related data have already been latched in the related data latch circuit 40, and one of the related data has been selected by the multiplexer 56 as related data for decrypting encrypted data. Upon receiving the relevant data change information, the system controller 15 specifies the relevant data after the change from among the relevant data in the relevant data latch circuit 40 based on the relevant data change information, and uses the relevant data as an adder. The switching of the multiplexer 56 is controlled through the associated data switching register 50 so as to change the data to be output to the.

The related data after the change may be transferred to the receiving side any time before the related data for decrypting the encrypted data is actually selected.

As described above, according to the present embodiment, the third
As in the first embodiment, when the transmission side changes the related data during the transfer of the encrypted data, there is no need to take time correspondence between the transfer of the encrypted data and the transfer of the related data. Can be reduced.

Next, a fifth embodiment of the present invention will be described with reference to FIG.

In the fourth embodiment, the asynchronous
Notification of related data change information by mode
Although the relevant data for encryption is changed immediately after the request to the 94 interface unit 21, there is no guarantee that the transfer of the relevant data change information in the asynchronous mode is necessarily performed before the change of the relevant data on the transmission side. If the related data change information is transferred after the related data is changed on the transmitting side, the encrypted data cannot be correctly restored on the receiving side. Further, the transmitting side does not know whether the relevant data change information is correctly received by the receiving side.

Therefore, in this embodiment, a response data latch circuit 57 is added to the configuration on the transmission side of the fourth embodiment shown in FIG. Upon receiving the notification of the related data change information, the receiving side returns the response data to the transmitting side. The transmitting side latches the response data in the response data latch circuit 57.

The system controller 15 on the transmitting side confirms the presence or absence of the arrival of the response data by the instruction signal 24 from the IEEE 1394 interface unit 21. When confirming the arrival of the response data, the response data latched by the response data latch circuit 57 Read. Then, the system controller 15 determines whether or not the receiving side has correctly received the relevant data change information from the response data. If it determines that the relevant data change information has been correctly received, the system controller 15 uses it for encryption in the next isochronous mode transfer cycle. The related data is changed, and the data encrypted by the related data is transferred in the isochronous mode.

Therefore, according to the present embodiment, the relevant data change timings of the transmitting side and the receiving side can be matched, and the transmitting side must confirm that the relevant data change information has been correctly received. Since the related data is changed, more reliable data transfer is realized.

Next, a sixth embodiment of the present invention will be described with reference to FIG.

In the fifth embodiment, if the time from when the response data is received by the transmitting side in the asynchronous mode until the start packet in the next isochronous mode is output is short, the related data is transmitted to the next isochronous mode. • Changing before entering the mode transfer cycle may not be timely.

Therefore, the present embodiment is different from the fifth embodiment shown in FIG. 9 in that a start packet monitoring circuit 58 for monitoring a start packet in the isochronous mode is provided.
A cycle number measuring circuit 59 for counting the number of isochronous mode transfer cycles passed by the output from the start packet monitoring circuit 58 is added.

When the system controller 15 confirms from the response data that the receiving side has correctly received the related data change information, it issues an operation command to the cycle number measuring circuit 59. In response to this operation command, the cycle number measuring circuit 59 starts counting the number of isochronous mode transfer cycles using the output of the start packet monitoring circuit 58 as a clock. When the number of cycles in the isochronous mode transfer reaches a predetermined value, the cycle number measuring circuit 59 notifies the system controller 15 of the fact. The system controller 15 that has received this notification switches and controls the multiplexer 42 through the related data switch register 43 so as to change the related data used for encryption.

On the other hand, on the receiving side, similarly, after returning the response data, the counting of the number of isochronous mode transfer cycles is started. Is changed according to the related data change information.

Therefore, according to the present embodiment, the related data change timings of the transmitting side and the receiving side can be more reliably matched, and more reliable data transfer is realized. Next, a seventh embodiment of the present invention will be described.

FIG. 11 is a diagram showing a configuration on the transmitting side according to the seventh embodiment.

The present embodiment provides a system that allows related data change information to be transferred in an isochronous mode. A fixed bit pattern storage register 60 is added to the configuration of the second embodiment shown in FIG. It becomes. The transfer of the encrypted data and the related data is performed in the isochronous mode and the asynchronous mode as in the second embodiment. The related data is changed in the following procedure.

The system controller 15 stores the fixed bit pattern of the related data change information, which has been predetermined with a specific device, in the fixed bit pattern storage register 6.
Write to 0. The arrangement of the fixed bit pattern of the related data change information between the devices is achieved, for example, by previously transferring the fixed bit pattern of the related data change information from the transmitting side to the specific receiving device in the asynchronous mode. You. Also, the system controller 15
Transfers the related data held in the related data storage register 33 to a specific device in the asynchronous mode before the start of the transfer of the encrypted data or in the isochronous mode transfer cycle of the encrypted data.

When it is desired to change the related data, the system controller 15 transmits the transfer mode switching control signals 23, 26 and 27 to the IEEE1394 interface unit 21 to set the isochronous mode as the transfer mode and to set the fixed bit pattern. The input / output data switching register 19 is set to transfer the data of the storage
The multiplexer 20 is controlled through

Thereafter, the system controller 15 reads the relevant data of the destination from the relevant data storage register 33 and controls the multiplexer 42 through the relevant data switching register 43 so as to output the data to the adder 34. Thus, encrypted data is obtained from the adder 34 using the changed related data, and the encrypted data is
The data is transferred in the isochronous mode by the interface unit 21.

Next, the receiving side of this embodiment will be described with reference to FIG.

When the system controller 15 detects that the transfer mode of the received data is the isochronous mode, the system controller 15 inputs the transferred data to the encrypted data latch circuit 39 and the fixed bit pattern detection circuit 61 so as to output the data. The multiplexer 20 is controlled through the output switching register 19.

The fixed bit pattern detection circuit 61 determines whether or not the transfer data has a unique bit pattern corresponding to the related data change information determined between the transmitting and receiving devices in advance, and determines the unique bit pattern. If so, the system controller 15 is notified of the fact.

The system controller 1 receiving this notification
5 changes the related data for decrypting the encrypted data in accordance with the related data change information indicated by the unique bit pattern, that is, reads the relevant data from the relevant data latch circuit 40 and outputs it to the adder 34. ,
Multiplexer 5 through related data switching register 50
Control 1

Thus, according to the present embodiment, even when the transfer data does not include a fixed bit pattern that is periodically repeated, it is possible to realize the isochronous mode transfer of the related data change information limited to the receiving device, and to change the related data. Since information is transferred in the isochronous mode, related data can be changed every isochronous mode transfer cycle of the encrypted data. Can be reduced.

Next, an eighth embodiment of the present invention will be described.

FIG. 13 is a diagram showing the configuration on the transmitting side of the serial interface control system of this embodiment.

In the present embodiment, an adder for encrypting data to be transferred is not required, but a transfer channel change for storing information for designating / changing a channel for transferring data in the isochronous mode. It has an information storage register 62. The specification and change of the transfer channel are performed in the following procedure.

The system controller 15 writes channel change information in the transfer channel change information storage register 62 in advance. The system controller 15 is IEEE
Control signals 23, 2
6 and 27, the transfer mode is set to the asynchronous mode, and the multiplexer 20 via the input / output data switching register 19 transfers the channel change information of the transfer channel change information storage register 62 in the asynchronous mode. Control. When the transfer of the channel change information is completed, the system controller 15 issues a request for changing the transfer mode to the isochronous mode to the IEEE1394 interface unit 21 and a request for changing the transfer channel. afterwards,
The output of the multiplexer 20 is changed from the channel change information in the transfer channel change information storage register 62 to the data in the buffer memory, and the data is transferred in the isochronous mode.

Next, the receiving side of this embodiment will be described with reference to FIG.

During reception of the transfer data, the system controller 15 transmits the data arrival signal 2 in the asynchronous mode.
4 is received, the input / output switching register 1
9 to switch the output of the multiplexer 20 to the channel change information latch circuit 63 side. When the system controller 15 detects the channel change information from the channel change information latch circuit 63, the system controller 15 transmits control signals 23, 26, and 27 requesting the change of the reception channel to the IEEE1394 interface unit 21 and controls the input / output switching register 19. To switch the output of the multiplexer 20 to the buffer memory bus 22 side.

As described above, in the present embodiment, by transferring the change information of the transfer channel to only a specific receiving device in the asynchronous mode, devices other than the specific device specified by the transmitting side can be transmitted without encrypting data. It is possible to prevent the transfer data from being captured.

Next, a ninth embodiment of the present invention will be described with reference to FIG.

In the eighth embodiment, the notification of the channel change information in the asynchronous mode is transmitted by the IEEE13.
94, the transfer channel of the transmission side is changed immediately after the request to the interface unit 21, but there is no guarantee that the transfer of the channel change information in the asynchronous mode is necessarily performed before the change of the transfer channel of the transmission side. If the transfer of the change information is performed after the change of the transfer channel on the transmission side, the reception side will receive data of the wrong transfer channel. Also, the transmitting side does not know whether the receiving side has correctly received the channel change information.

Therefore, in this embodiment, a response data latch circuit 57 is added to the configuration of the eighth embodiment shown in FIG. Upon receiving the notification of the change information of the transfer channel, the receiving side returns response data indicating that the notification has been received to the transmitting side. The transmitting side latches the response data in the response data latch circuit 57.

The system controller 15 on the transmitting side determines whether or not response data has arrived from the receiving side according to IEEE1394.
After confirming with the instruction signal 24 from the interface unit 21 and confirming the arrival of the response data, the response data latched by the response data latch circuit 57 is read. Then, the system controller 15 on the transmitting side determines whether or not the receiving side has correctly received the transfer channel change information from the read response data. If the receiving side determines that the transfer channel change information has been correctly received, the next isochronous mode transfer is performed. The transfer channel is changed in a cycle, and data is transferred using this transfer channel.

Therefore, according to the present embodiment, it is possible to make the transmission channel change timings of the transmission side and the reception side coincide with each other, and that the specific device on the reception side has correctly received the information regarding the change of the transfer channel. Since the transmission channel on the transmitting side is changed after confirming the above, more reliable data transfer is realized.

Next, a tenth embodiment of the present invention will be described with reference to FIG.
This will be described below.

In the ninth embodiment, if the time from when the transmitting side receives the response data in the asynchronous mode until the start packet in the next isochronous mode is output is short, the transfer channel is set to the next isochronous mode. • Changing before entering the mode transfer cycle may not be timely.

Therefore, the present embodiment corresponds to the ninth embodiment shown in FIG.
The start packet monitoring circuit 58 for monitoring the start packet in the isochronous mode is different from the configuration of the embodiment.
And a cycle number measuring circuit 59 for counting the number of isochronous mode transfer cycles passed by the output from the start packet monitoring circuit 58.

When the system controller 15 confirms from the response data that the receiving side has correctly received the transfer channel change information, it issues an operation command to the cycle number measuring circuit 59. In response to this operation command, the cycle number measuring circuit 59 starts counting the number of isochronous mode transfer cycles using the output of the start packet monitoring circuit 58 as a clock. When the number of cycles in the isochronous mode transfer reaches a predetermined value, the cycle number measuring circuit 59 notifies the system controller 15 of the fact. The system controller 15 having received this notification rewrites the transfer channel change information of the channel change information storage register 62 so as to change the transfer channel.

On the other hand, on the receiving side, similarly, after returning the response data, the number of isochronous mode transfer cycles is started, and when the value reaches a predetermined value, the receiving channel is changed according to the transfer channel change information. change.

Therefore, according to the present embodiment, the timing of changing the transfer channel between the transmitting side and the receiving side can be more reliably matched, and more reliable data transfer is realized.

[0114]

As described above, according to the first aspect of the present invention, data to be transferred is encrypted and transferred synchronously, and related data necessary for decrypting the encrypted data is asynchronously transmitted to a specific device. By the type transfer, the encrypted data can be received by all devices, but the acquisition of related data required to decrypt the encrypted data is limited to only the specific device, so the synchronization that specified the receiving device Data transfer at a constant data transfer rate by die transfer can be realized, and security can be improved.

According to the second aspect of the present invention, since the related data used for encryption can be changed freely, the probability that the related data can be detected by a device other than the specific device designated by the transmitting side is reduced, and the receiving device Can further enhance the security of the synchronous data transfer.

According to the third aspect of the present invention, the related data for decrypting the encrypted data can be specified from the bit pattern of the encrypted data itself on the receiving side. It is possible to reduce restrictions on changing related data as compared with a method of transferring related data asynchronously, for example, by changing the related data.

According to the fourth aspect of the present invention, a plurality of related data are asynchronously transferred to a specific device, and every time the related data is changed, information relating to the change of the relevant data is asynchronously transferred to the specific device. Thus, similarly to the invention of claim 3, when the related data is changed during the transfer of the encrypted data on the transmitting side, there is no need to take time correspondence between the transfer of the encrypted data and the transfer of the related data. It is possible to reduce restrictions on changing related data.

According to the fifth aspect of the present invention, when the related data is changed, information relating to the change of the related data is asynchronously transferred to the specific device, and then a response to the related data change information from the specific device is confirmed. Related data on the sending side, so that the related data change timing on the sending side and the receiving side can be matched, and that the specific device on the receiving side has correctly received the information on the related data change Since the related data on the transmitting side is changed after that, more reliable data transfer is realized.

According to the sixth aspect of the present invention, the synchronous transfer cycle for changing related data can be fixed to a cycle after a predetermined number of cycles after receiving a response from the receiving device. Of the related data can be more surely matched.

According to the seventh aspect of the present invention, even when transfer data does not include a fixed bit pattern that is periodically repeated, synchronous transfer of related data change information limited to receiving devices can be realized. As compared with the method of asynchronously transferring related data, it is possible to reduce restrictions on changing related data, for example, related information can be changed every synchronous transfer cycle of encrypted data by synchronously transferring information.

According to the eighth aspect of the invention, the transfer information is asynchronously transferred to a specific device, thereby preventing a device other than the specific device from taking in the transfer data without encrypting the transfer data. can do.

According to the ninth aspect of the present invention, the transmission channel change timing of the transmission side and the reception side can be made coincident with each other, and the specific device on the reception side correctly receives the information on the change of the transfer channel. Since the transmission channel on the transmitting side is changed after confirming the above, more reliable data transfer is realized.

According to the tenth aspect of the present invention, the synchronous transfer cycle for changing the transfer channel can be fixed to a cycle after a predetermined number of cycles after receiving the response from the receiving device. The timing of changing the transfer channel with the side can be more reliably matched, and more reliable data transfer is realized.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a transmission side of a serial interface / data transfer control system according to a first embodiment of the present invention;

FIG. 2 is a diagram showing an example of data transfer in the system of FIG. 1;

FIG. 3 is a diagram showing a configuration of a receiving side of the system of FIG. 1;

FIG. 4 is a diagram illustrating a configuration on a transmission side according to a second embodiment;

FIG. 5 is a diagram showing a data encryption method according to a second embodiment;

FIG. 6 is a diagram illustrating a configuration of a receiving side according to a third embodiment;

FIG. 7 is a diagram illustrating a configuration on a transmission side according to a fourth embodiment;

FIG. 8 is a diagram illustrating a configuration of a receiving side according to a fourth embodiment;

FIG. 9 is a diagram illustrating a configuration on a transmission side according to a fifth embodiment;

FIG. 10 is a diagram illustrating a configuration on a transmission side according to a sixth embodiment;

FIG. 11 is a diagram illustrating a configuration of a transmission side according to a seventh embodiment;

FIG. 12 is a diagram illustrating a configuration of a receiving side according to a seventh embodiment;

FIG. 13 is a diagram illustrating a configuration on a transmission side according to an eighth embodiment;

FIG. 14 is a diagram illustrating a configuration on a receiving side according to an eighth embodiment;

FIG. 15 is a diagram illustrating a configuration of a transmission side according to a ninth embodiment;

FIG. 16 is a diagram illustrating a configuration of a transmission side according to a tenth embodiment.

FIG. 17 is a diagram showing a configuration of a DVD data reproduction system.

FIG. 18 is a diagram showing a configuration of a transmission side of a conventional serial interface / data transfer control system.

FIG. 19 is a diagram showing a data transfer example of a conventional serial interface data transfer control system.

[Explanation of symbols]

 15 System controller 19 Input / output data switching register 20 Multiplexer 21 IEEE 1394 interface unit 33 Related data storage register 34 Adder 39 Encrypted data latch circuit 40 Related data latch circuit 42 multiplexer 43 related data switching register 48 comparison data storage register 49 comparison circuit 50 related data switching register 51 multiplexer 52 related data change information storage register 53 related data change information Latch circuit 56 Multiplexer 57 Response data latch circuit 58 Start packet monitoring circuit 59 Cycle number measurement circuit 60 Fixed bit pattern storage register 61 Fixed bit pattern detection circuit 62 Transfer channel change Update information storage register 63 Channel change information latch circuit

Claims (10)

[Claims] 1. A method for transferring data between devices connected through a serial interface, wherein data to be transferred is encrypted using predetermined related data, and the encrypted data is synchronously transferred and the related data is specified. A data transfer method characterized by performing asynchronous transfer to a device. 2. A method for transferring data between devices connected through a serial interface, wherein data to be transferred is encrypted using related data arbitrarily selected from among a plurality of related data, and the encrypted data is encrypted. A data transfer method, wherein the related data is transferred asynchronously to a specific device while performing synchronous transfer. 3. A data transfer method between devices connected via a serial interface, wherein data including a unique bit pattern is encrypted by selectively using one of a plurality of related data. A data transfer method comprising: synchronously transferring encrypted data and asynchronously transferring the plurality of related data to a specific device. 4. A data transfer method between devices connected via a serial interface, wherein data to be transferred is encrypted by selectively using one of a plurality of related data, and the encrypted data is synchronized. Transferring the plurality of related data to a specific device asynchronously, and transferring information relating to the change of the related data to the specific device each time the related data is changed. . 5. A data transfer method between devices connected via a serial interface, wherein data to be transferred is encrypted by selectively using one of a plurality of related data, and the encrypted data is synchronized. Transfer and asynchronously transfer the plurality of related data to a specific device, and when changing the related data, asynchronously transfer information on the change of the related data to the specific device, and then transfer the related data from the specific device. A data transfer method comprising: confirming a response to data change information and changing related data on a transmission side. 6. A data transfer method between devices connected through a serial interface, wherein data to be transferred is encrypted by selectively using one of a plurality of related data, and the encrypted data is synchronized. Transfer and asynchronously transfer the plurality of related data to a specific device, and, when changing the related data, asynchronously transfer information related to the change of the related data to the specific device. A data transfer method comprising: confirming a response to data change information; and changing related data on a transmission side after a predetermined time has elapsed. 7. A data transfer method between devices connected via a serial interface, wherein data to be transferred is encrypted by selectively using one of a plurality of related data, and the encrypted data is synchronized. Transfer and asynchronously transfer the plurality of related data to a specific device, and every time the related data is changed, information on the change of the related data consisting of a bit pattern predetermined with the specific device is transmitted. A data transfer method characterized by synchronous transfer. 8. A data transfer method between devices connected through a serial interface, wherein data is transferred synchronously and channel designation information for designating a channel used for the synchronous transfer is asynchronously transmitted to a specific device. A data transfer method characterized by transferring. 9. A data transfer method between devices connected via a serial interface, wherein data is transferred synchronously and channel designation information for designating a channel used for the synchronous transfer is asynchronously transmitted to a specific device. A data transfer method, comprising: transferring the data, confirming a response to the channel designation information from the specific device, and changing the channel on the transmission side. 10. A data transfer method between devices connected via a serial interface, wherein data is transferred synchronously and channel designation information for designating a channel used for the synchronous transfer is asynchronously transmitted to a specific device. A data transfer method, comprising: transmitting a response to the channel designation information from the specific device; and changing a channel on the transmission side after a predetermined time has elapsed.