JP2006040167A - Bus arbitration circuit, information processing device, and program and recording medium for the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a bus arbitration circuit that can arbitrate a bus such that a synchronous device capable of repeatedly transmitting data strings forming synchronous data requiring band guarantee can transmit the synchronous data more reliably. <P>SOLUTION: When detecting the transmission of synchronous data by an external bus I/F 20, the bus arbitration circuit 16 decides an arbitration start time point earlier than a predicted data transmission start time point of the next data string of the synchronous data, according to prediction information stored in a register 33, and starts arbitrating the bus to give a use right to the external bus I/F 20 at the arbitration start time point even if the external bus I/F 20 does not request a use right. The bus use right can be thus given to the external bus I/F 20 without delay earlier than by arbitration started at a bus use right request of the external bus I/F 20. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention is suitably used, for example, when processing data such as video / audio that requires transfer timing and transfer band guarantee, and can repeatedly transmit a data string constituting synchronous data requiring band guarantee. The present invention relates to a bus arbitration circuit capable of arbitrating a bus so that a synchronous device can transmit synchronization data more reliably, an information processing apparatus including the bus arbitration circuit, and a program and a recording medium for realizing the bus arbitration circuit.

  In order to exchange data between devices, a system in which a bus is shared between a plurality of devices and each device transmits and receives data via the bus is widely used. Information processing apparatuses including a bus arbitration circuit for arbitrating rights are also widely used.

  Hereinafter, the operation of the internal bus in the information processing apparatus disclosed in Patent Document 1 described later will be described with reference to FIG.

  In FIG. 5, an information processing apparatus 100 is an information processing apparatus capable of processing real-time data that requires a guaranteed transfer band, and includes a CPU 111, a host bus 112, a memory 113, a host-PCI bridge 114, and a PCI bus. 115, a bus arbitration circuit 101, a disk I / F 102, and IEEE1394 I / Fs 103 to 104.

  Further, the HDD 110 is connected to the disk I / F 102. A digital TV tuner 111 is connected to the IEEE 1394 I / F 103 via the IEEE 1394 bus 108. Further, a DVCR (Digital Video Cassete Recorder) 23 is connected to the IEEE 1394 I / F 104 via an IEEE 1394 bus 109. Further, the disk I / F 102 and the IEEE 1394 I / F 103 to 104 have timers 105 to 107, respectively.

  The CPU 111 is a means for performing data processing and calculation. The host bus 112 is an internal bus that connects the CPU 111 and the memory 113 and can transfer data at high speed. The host-PCI bridge 114 is a control device that controls data transfer between the CPU 111, the memory 113, and the PCI bus 115. The memory 113 is a device that records a program and data to be processed by the CPU 111, a temporary work area of the program, and the like.

  The PCI bus 115 is a bus inside an information processing apparatus shared by various devices, and the bus arbitration circuit 101 is in response to a use request of the PCI bus 115 from each device connected to the PCI bus 115. This is a bus arbitration unit that grants a bus use right to one device selected by a certain algorithm.

  The timer means 105 to 107 count the time that each device is using the PCI bus 115 in units of the clock of the PCI bus 115, and the maximum time that the PCI bus 115 can be used at one time is described in units of the clock of the PCI bus 115. Means with preset values.

  The disk I / F 102 is an interface for connecting a PCI bus and a mass storage device such as a CD or an HDD. The IEEE1394 I / Fs 103 to 104 are IEEE1394-compliant interfaces that connect the PCI bus 115 and the IEEE1394 bus 108.

  In addition, when IEEE 1394 requires real-time performance such as sequentially reproducing video while transferring, it is possible to connect a device that can secure and transfer a bandwidth necessary for data transfer between connected devices. It is a standard for interfaces and buses.

  In the following, such data requiring real-time property (data requiring bandwidth guarantee) is referred to as synchronization data, and a device that can transfer the synchronization data is referred to as a synchronization device. Note that the synchronization device according to the present embodiment periodically transfers a certain amount of data when transmitting the synchronization data. A device that transfers data that does not require a guaranteed transfer bandwidth is called an asynchronous device, and data that does not require a guaranteed transfer bandwidth is called asynchronous data.

Next, an operation when such a conventional information processing apparatus receives a digital broadcast by the digital TV tuner 111 and records the received AV data by the DVCR 123 will be described.
In digital broadcasting, AV data is transmitted on a broadcast wave from a broadcast station using a transport packet of an MPEG2 transport stream.

  The digital TV tuner 111 receives and demodulates this broadcast wave. Then, the digital TV tuner 111 sequentially sends the demodulated AV data to the IEEE 1394 bus 108.

  IEEE 1394 specifies that the time is divided into time slots of 125 μsec. A device connected to the IEEE 1394 bus 108 can send a certain amount of synchronization data only once in this time slot. Therefore, the transfer amount of data that can be sent in a certain period is guaranteed. As described above, according to IEEE 1394, the synchronization data can be normally transferred without omission.

  The IEEE1394 I / F 103 receives AV data sent from the digital TV tuner 111 and temporarily stores it in a buffer.

  Further, the IEEE 1394 I / F 103 requests a bus use right from the bus arbitration circuit 101. The bus arbitration circuit 101 performs arbitration and gives a bus use right to the IEEE1394 I / F 103. Hereinafter, the operation in which the bus arbitration circuit 101 arbitrates the PCI bus 115 will be described in detail.

  Assume that the disk I / F 102 and the IEEE 1394 I / F 103 are devices that desire to use the PCI bus 115 (hereinafter referred to as master devices). The disk I / F 102 and the IEEE 1394 I / F 103 issue a bus use request to the bus arbitration circuit 101 through a signal line REQ.

  The bus arbitration circuit 101 receives a bus use request from each master device. When two or more master devices request the right to use the PCI bus 115 at the same time, it is determined to which master device the right to use the bus is given. Then, the master device that permits the use of the bus is notified that the use of the PCI bus 115 is permitted through a signal line called GNT. REQ and GNT connect each device and the bus arbitration circuit 101 in a point-to-point manner, and the bus arbitration circuit 101 performs bus arbitration using this set of signal lines.

  The bus arbitration circuit 101 performs arbitration according to a cyclic algorithm or the like that equalizes the number of times of bus use permission when receiving bus use requests from two or more master devices at the same time.

  As a result of the bus arbitration by the bus arbitration circuit 101, it is assumed that the IEEE 1394 I / F 103 has obtained permission to use the PCI bus 115, that is, becomes an initiator of the PCI bus 15. Then, the timer 106 starts counting the clock of the PCI bus 115. Until the count value of the timer 106 becomes equal to the preset value that the timer 106 has in advance, the IEEE 1394 I / F 104 sequentially reads the AV data stored in the buffer, specifies the address of the IEEE 1394 I / F 103, AV data is sequentially sent to the PCI bus 115. In other words, the initiator transmits data with the maximum time that the count value of the timer 106 becomes equal to the preset value.

  Here, the preset values of the timers 105 to 107 are determined based on the ratio of the transfer band to be guaranteed for one synchronization device desired to be transferred to the total transferable band of the PCI bus 115. The ratio of the preset value to the sum of the preset values of the timers of all the synchronous devices and asynchronous devices that are desired to be transferred is set to be equal or larger. By determining in this way, the transfer bandwidth required by the IEEE 1394 I / F 103 can be ensured.

  By predetermining preset values of the timers 105 to 107 so as to satisfy such conditions, the transfer bandwidth required by the IEEE 1394 I / F 103 is guaranteed.

  On the other hand, the IEEE 1394 I / F 104 receives AV data sent from the IEEE 1394 I / F 103 to the PCI bus 115 and temporarily stores it in a buffer.

  The AV data stored in the buffer is sequentially sent to the IEEE 1394 bus 109, and the DVCR 23 sequentially records the received AV data on the tape medium.

In this way, the bus arbitration circuit 101 arbitrates so that the number of times each device uses the PCI bus 115 is equal, and the CPU 111 adjusts the preset values of the timers 105 to 107 of each device. The transfer amount required for the transfer of AV data by the IEEE 1394 I / F 103 or the like is guaranteed.
JP 2001-117861 A (publication date: April 27, 2001)

  However, in the information processing apparatus described above, the right to use the bus given to a synchronous device such as IEEE1394 I / F to which synchronous data is to be transferred is irrelevant to the timing at which the synchronous device transfers data. There is a problem that jitter occurs in transfer, real-time characteristics are impaired, reproduction quality is deteriorated in the case of AV data, and a data transfer band cannot be ensured as intended.

  For example, in the case of IEEE1394 I / F, synchronous data is transferred at a constant rate every 125 μs. Even if the synchronous data to be transferred is prepared, the use right is assigned to the asynchronous device at that time, and the data is transferred. If it is in the middle, the transfer of the synchronous data is waited until the transfer of the asynchronous data is completed. In the worst case, the transfer of the synchronous data after the next 125 μs is impossible. Although there is a method of increasing the size of the buffer in order to minimize the influence due to the occurrence of jitter, in this case, there is a problem that the delay time of data transfer is increased and the operability is lowered.

  The present invention has been made in view of the above problems, and an object of the present invention is to enable a synchronization device that can repeatedly transmit a data string constituting synchronization data requiring bandwidth guarantee to transmit synchronization data more reliably. The present invention relates to a bus arbitration circuit capable of arbitrating a bus, an information processing apparatus including the bus arbitration circuit, and a program and a recording medium for realizing the bus arbitration circuit.

  In order to solve the above-described problem, the bus arbitration circuit according to the present invention has a right to use a bus shared by a plurality of devices including a synchronization device that can repeatedly transmit a data string constituting synchronization data requiring bandwidth guarantee. In a bus arbitration circuit having a bus arbitration unit for arbitrating, the bus arbitration unit includes a storage unit in which prediction information for predicting a next data transmission start time by the synchronization device is stored in advance. When detecting the transmission of the synchronous data, based on the prediction information stored in the storage means, determine the arbitration start time before the prediction result of the data transmission start time of the data sequence of the next synchronous data, Even if the use right is not requested by the synchronization device, the use for giving the use right to the synchronization device from the start of the arbitration. It is characterized in that to start the arbitration process of the scan.

  The prediction information is information for predicting the next data transmission start time by the next synchronization device. For example, when the synchronization device periodically transmits a data string, the cycle is preferably used. The As an example of this case, when the synchronization device periodically transmits a data string based on the time measurement result of the timer, or the data received by the synchronization device is stored in the buffer and the accumulated amount of the buffer is a predetermined threshold value. In the configuration in which the data is transferred to the bus when the data rate becomes, the speed of the received data is constant. Further, in the prediction information, the synchronization device makes the average value of the time intervals between the transmission start points of the data string constant according to a predetermined algorithm, and at least a part of each time interval is the other value. When the time intervals are controlled so as to be different from the time intervals, information on the algorithm may be used.

  In the above configuration, the synchronization device repeatedly transmits a data string constituting the synchronization data when transmitting the synchronization data requiring bandwidth guarantee. On the other hand, when the bus arbitration unit of the bus arbitration circuit detects the transmission of the synchronization data by the synchronization device, the bus arbitration unit predicts the data transmission start time of the data string of the next synchronization data based on the prediction information stored in the storage unit in advance. Determine the mediation start time before the result. Further, the bus arbitration means starts the bus arbitration process for giving the right to use the synchronization device from the start of the arbitration even if the usage right is not requested by the synchronization device.

  In this configuration, the bus arbitration means starts the arbitration process from the arbitration start time point. Therefore, when the synchronous device repeatedly transmits the data string and transmits the synchronous data, the synchronous device actually requests the right to use the bus. The arbitration process can be started from an earlier time point. Therefore, compared to a configuration in which the synchronization device actually requests the bus use right and then starts the arbitration process, the bus arbitration circuit gives the bus right to the synchronization device at an earlier time without delay. And the bus can be arbitrated so that the synchronization device can transmit synchronization data more reliably. As a result, it is possible to realize a system capable of transmitting synchronous data, such as AV data, which requires a strong real-time property without any trouble.

  In addition to the above configuration, the prediction information may be information indicating a cycle in which the synchronous device transmits a data string. In this configuration, since the arbitration start time before the prediction result of the next data transmission start time is determined based on the prediction information indicating the cycle, the synchronization device periodically transmits the data string of the synchronization data. It can be suitably used for the configuration.

  Furthermore, in addition to the above configuration, the time difference between the prediction result at the data transmission start time of the data sequence of the next synchronization data and the arbitration start time is set larger than the time required for the arbitration process, and the bus The arbitration means, when detecting transmission of synchronous data by the synchronous device, sends a permission signal for giving the right to use the bus to the synchronous device before the synchronous device requests the right to use the bus. It may be output.

  According to this configuration, since the permission signal is given to the synchronization device before the synchronization device actually requests the right to use the bus, the synchronization device permits the use of the bus without waiting time. Obtainable. As a result, the bus arbitration circuit can give the right to use the bus at an earlier time without further delay, and the synchronization device can arbitrate the bus so that the synchronization data can be transmitted more reliably.

  In addition to the above configuration, the bus arbitration unit may give the permission signal to the synchronization device for a time indicated by preset bus use permission time information. In this configuration, the permission signal is given to the synchronization device for a time indicated by preset bus use permission time information. Therefore, by setting information corresponding to the period that the synchronization device should occupy when transmitting the data string in order to guarantee the bandwidth as the bus use permission time information, the bus arbitration circuit causes the bus to be transmitted to the synchronization device during the period. Can be occupied, and the bus can be arbitrated so that the synchronous device can transmit synchronous data more reliably.

  Further, in addition to the above configuration, the bus arbitration unit monitors the state of the bus to detect whether or not the synchronization device is actually transmitting a data sequence, and the synchronization device transmits the data sequence. You may control the length of the period which gives the said permission signal to a synchronous device so that the sum total of the period actually transmitted may become the time which preset bus use permission time information shows.

  In this configuration, the length of the period during which the permission signal is given to the synchronization device is controlled to be the sum of the periods during which the synchronization device actually transmits the data string. Therefore, by setting information corresponding to the period that the synchronization device should occupy when transmitting the data string in order to guarantee the bandwidth as the bus use permission time information, the bus arbitration circuit causes the bus to be transmitted to the synchronization device during the period. Can be occupied, and the bus can be arbitrated so that the synchronous device can transmit synchronous data more reliably.

  In addition, since the bus arbitration means monitors the state of the bus and detects whether the synchronous device is actually transmitting a data string, the synchronous device actually transmits the data string. Regardless of whether or not the synchronization device is configured to provide a permission signal to the synchronization device for a certain period, the synchronization device can arbitrate the bus so that the synchronization data can be transmitted more reliably.

  Further, in addition to the above configuration, the bus arbitration unit monitors the state of the bus and detects the data amount of the data string actually transmitted by the synchronous device this time, and according to the detection result, The bus use permission time information may be updated.

  In this configuration, since the bus use permission time information is updated according to the data amount of the data string actually transmitted by the synchronous device this time, the data amount of the data string repeatedly transmitted by the synchronous device is Even if it fluctuates to some extent, it is possible to change the period during which the use permission of the bus is given to the synchronous device according to the fluctuation. As a result, the bus arbitration circuit can arbitrate the bus so that the synchronization device can transmit synchronization data more reliably.

  Further, in addition to the above configuration, the bus arbitration means outputs a bus transfer stop signal to a device other than the synchronous device that is using the bus at that time when the arbitration start time is reached. Data transfer may be stopped.

  According to this configuration, when the arbitration start time is reached, a bus transfer stop signal is output to a device other than the synchronous device that is using the bus at that time, so that data transfer by the device can be stopped. it can. As a result, the bus arbitration circuit grants the bus usage right to the synchronization device at an earlier time without delay, compared to the configuration in which the synchronization device actually requests the bus usage right before starting the arbitration process. And the bus can be arbitrated so that the synchronization device can transmit synchronization data more reliably.

  Further, in addition to the above-described configuration, the bus arbitration unit may grant the use permission of the bus in a plurality of times in response to a request for the right to use the bus from the synchronous device. In this configuration, the bus use permission is given in a plurality of times in response to one request for the right to use the bus from the synchronous device. Therefore, the length of the use permission continuously given to the synchronous device can be shortened as compared with the configuration in which the use permission of the bus is given once for each request of the bus use right, and other devices can shorten the bus use right. It is possible to shorten the time from when the usage right is requested until the usage permission is given.

  In addition to the above-described configuration, the bus arbitration unit may calculate an elapsed time from when the right to use the bus from a device other than the synchronous device is requested when the synchronous device has obtained the right to use the bus. When the elapsed time exceeds a predetermined bus use permission time, the right to use the bus of the synchronous device is temporarily released for a preset time, and the right to use the bus is granted to the device. May be given.

  In this configuration, if the elapsed time from the request to use the bus from a device other than the synchronous device exceeds the bus use permission time, the bus use right is temporarily given to the device. The time from when the device requests the right to use the bus until the use permission is granted can be kept within the maximum allowable time.

  Further, in addition to the above configuration, when two or more synchronization devices are connected to the bus, the bus arbitration means determines the arbitration start time for the synchronization device having the shortest data transfer cycle, The bus arbitration process for giving the right of use to the synchronous device may be started from the arbitration start time.

  In this configuration, for the synchronous device having the shortest data transfer cycle, the arbitration start time is determined based on the prediction information, and the arbitration process from the arbitration start time is performed. Therefore, for the specific synchronization device where the period of data transfer is the shortest, and therefore the most required among the plurality of synchronization devices to give the right to use the bus without delay at a faster point in time. At a faster time, the right to use the bus can be granted without delay. As a result, the bus arbitration circuit can arbitrate the bus so that the specific synchronization device can transmit synchronization data more reliably.

  In addition to the above-described configuration, the bus arbitration unit may perform the arbitration for any one synchronization device when two or more synchronization devices having the same data transfer cycle are connected to the bus. The start time is determined, and the arbitration processing of the bus for giving the right of use to the synchronous device is started from the arbitration start time, and the bus use permission for the time required for data transfer of the synchronous device is given to the synchronous device. After giving, before granting bus use permission to devices other than the respective synchronization devices, bus use permission may be given to another synchronization device in a predetermined order.

  In this configuration, after giving the synchronization device a bus use permission for a time required for data transfer of the synchronization device to a certain synchronization device, before giving the bus use permission to a device other than each of the synchronization devices, Usage permission is granted to other synchronization devices. Therefore, the bus arbitration circuit can give permission to use over the other synchronous devices over the devices other than the synchronous devices, so that these synchronous devices can transmit the synchronous data more reliably. Can arbitrate the bus.

  In order to solve the above problems, an information processing apparatus according to the present invention includes a bus arbitration circuit having the above-described configuration, a bus in which usage rights by a plurality of connected devices are arbitrated by the bus arbitration circuit, and the bus And a setting means for setting the prediction information in the bus arbitration circuit based on the detection result.

  According to this configuration, the setting means detects the characteristics of the synchronous device connected to the bus, and the prediction information of the bus arbitration circuit is set based on the detection result, so that it is currently connected to the bus. The prediction information can be changed according to the characteristics of the synchronized device. As a result, the bus arbitration circuit realizes an information processing device that can arbitrate the bus and transmit synchronization data more reliably so that the synchronization device currently connected to the bus can transmit synchronization data more reliably. it can.

  By the way, each means of the information processing apparatus may be realized by hardware, or may be realized by causing a computer to execute a program. Specifically, the program according to the present invention is a computer program connectable to a bus arbitration circuit and a bus whose usage rights by a plurality of connected devices are arbitrated by the bus arbitration circuit, The arbitration circuit includes bus arbitration means for arbitrating a right to use a bus shared by a plurality of devices including a synchronization device capable of repeatedly transmitting a data string that constitutes synchronization data that requires bandwidth guarantee, and the bus arbitration means When detecting the transmission of the synchronous data by the synchronous device, the data of the data string of the next synchronous data based on the prediction information set in advance for predicting the next data transmission start time by the synchronous device The arbitration start time before the transmission start time prediction result is determined, and the use right is not requested by the synchronization device. In addition, from the start of the arbitration, the bus arbitration process for giving the right to use the synchronous device is started, and the program detects the characteristics of the synchronous device connected to the bus and outputs the detection result. Based on this, the setting means for setting the prediction information in the bus arbitration circuit is a program for operating the computer. The program is recorded on the recording medium according to the present invention.

  When the program is executed by the computer, a device having the computer, a bus, and a bus arbitration circuit operates as the information processing device. Therefore, like the information processing apparatus, the information processing apparatus that can arbitrate the bus and transmit the synchronization data more reliably so that the synchronization device currently connected to the bus can transmit the synchronization data more reliably. Can be realized.

  According to the present invention, the right to use the bus can be given to the synchronization device at an earlier time without delay, and the bus can be arbitrated so that the synchronization device can transmit the synchronization data more reliably. Therefore, for example, the present invention can be widely and suitably used for various systems capable of transmitting various types of synchronous data via a bus, including AV systems that transmit AV data that requires a strong real-time property via a bus.

[First embodiment]
Hereinafter, embodiments of the present invention will be described.
First, a first embodiment will be described with reference to FIGS.

  FIG. 1 is a block diagram showing a configuration of an information processing apparatus 1 including an internal bus bandwidth control unit according to the first embodiment of the present invention. In FIG. 1, an information processing apparatus 1 includes a CPU 11, a host bus 12, a memory 13, a host-internal bus bridge 14, an internal bus 15, a bus arbitration circuit 16, an Ethernet (registered trademark) I / F 17, a graphic controller 18, and an MPEG decoder. 19 and an external bus I / F 20. A display 21 is connected to the graphic controller 18. Further, a DVCR 23 is connected to the external bus I / F 20 via the external bus 22. The internal bus 15 corresponds to the bus described in the claims, and the external bus I / F 20 corresponds to the synchronous device.

  In the information processing apparatus 1 according to the present embodiment, a PCI (Peripheral Component Interconnect) bus is adopted as the internal bus 15, and an IEEE (American Institute of Electrical and Electronics Engineers) 1394 bus is adopted as the external bus 22. Yes. In this case, the host-internal bus bridge 14 and the external bus I / F 20 are a host-PCI bridge and an IEEE 1394 I / F, respectively.

  The CPU 11 is a means for performing data processing and computation, and can perform data processing and computation in accordance with a program stored in a storage device accessible by the CPU 11 such as the memory 13 or a hard disk (not shown). Note that when the CPU 11 accesses the storage device, for example, it may be directly accessed via the host bus 11 or, for example, via the host bus 11, the host-internal bus bridge 14, and the internal bus 15. The storage device may be indirectly accessed by instructing access to a hard disk as a storage device to a hard disk IF (not shown).

  The host bus 12 is a bus provided in the information processing apparatus 1 and capable of transferring data at high speed, and connects the CPU 11 and the memory 13. The host bus 12 is generally faster than the internal bus 15 shared by devices such as interfaces. The memory 13 is a device that records a program and data to be processed by the CPU 11, a temporary work area of the program, and the like. The host-internal bus bridge 14 is a device that controls data transfer between the CPU 11 and the memory 13 and the internal bus 15. In the present embodiment, the memory 13 is directly connected to the host bus 12, but may be connected by other methods as long as the CPU 11 can access the memory 13. As an example, a memory controller is built in the host-internal bus bridge 14 and may be connected to the host-internal bus bridge 14.

  The internal bus 15 is a bus inside the information processing apparatus 1 shared by various devices, and a device that has obtained the right to use the bus can control the internal bus 15 and transfer data.

  The bus arbitration circuit 16 can grant a bus use right to one device selected by a certain algorithm in response to a request for using the internal bus 15 from each device connected to the internal bus 15. Further, the bus arbitration circuit 16 can also operate as means for controlling the bandwidth of the internal bus 15 that can process data such as video and audio that require transfer timing and transfer bandwidth guarantee. The bus arbitration circuit 16 corresponds to the bus arbitration means described in the claims.

  Specifically, as will be described in detail later, the bus arbitration circuit 16 according to the present embodiment attempts to transmit data requiring bandwidth guarantee by periodically requesting a bus use right among the above devices. The device can estimate the next time to request the bus use right based on the predetermined prediction information, and the bus use right arbitration process can be started prior to the time. Note that the prediction information is information for predicting when the device next requests the right to use the bus, and is set in advance based on the identification of the device. As the prediction information, as will be described in detail later, for example, when the device transmits data that requires bandwidth guarantee, a cycle of transferring a data string (a cycle for requesting a bus use right) and the like can be given. It is done.

  In the following, such data requiring real-time property (data requiring bandwidth guarantee) is referred to as synchronization data, and a device that can transfer the synchronization data is referred to as a synchronization device. Note that the synchronization device according to the present embodiment periodically transfers a certain amount of data when transmitting the synchronization data. A device that transfers data that does not require a guaranteed transfer bandwidth is called an asynchronous device, and data that does not require a guaranteed transfer bandwidth is called asynchronous data.

  As a result, when the synchronization data is transmitted by the synchronization device, the bus arbitration circuit 16 can start the arbitration process at a time before the time when the synchronization device actually requests the bus use right. . Therefore, the bus arbitration circuit 16 can give the bus use right to the synchronous device more quickly than the configuration in which the arbitration process is started after the bus use right is requested from the synchronous device. As a result, it is possible to guarantee the synchronous data bandwidth more reliably.

  Further, in the bus arbitration circuit 16 according to the present embodiment, information (bus use permission time information) indicating a period during which the bus use right is given to the synchronous device is also set in advance. The bus use right can be given to the synchronous device for a period based on the permission time information. In the present embodiment, as will be described in detail later, as the bus use permission time information, a value corresponding to the band information required for the synchronization data is set.

  As a result, the bus arbitration circuit 16 can more reliably give the right to use the bus to the synchronous device for a period required by the synchronous device, and can guarantee the band of the synchronous data more reliably.

  Any device may be set in the bus arbitration circuit 16 as long as the above information is set before the synchronization data is transferred, or may be always stored in the bus arbitration circuit 16. In the present embodiment, the CPU 11 that operates according to the program stored in the above-described storage device sets the above information corresponding to the characteristics of the synchronous device in the bus arbitration circuit 16 via the host bus 12.

  In FIG. 1, as an example, the case where the bus arbitration circuit 16 is an independent device different from the host-internal bus bridge 14 (in the case of a separate chip) is illustrated, but the host-internal bus bridge is illustrated. It may be built in 14 chips. In this case, the number of chips constituting the information processing apparatus 1 can be reduced. When the host-internal bus bridge 14 incorporating the existing bus arbitration circuit is used in the configuration provided separately from the host-internal bus bridge 14 having the configuration shown in FIG. 14 is used by invalidating the bus arbitration circuit built in 14.

  The Ethernet I / F 17 is an interface for connecting to an IP (Internet Protocol) network by a twisted pair cable, and the information processing apparatus 1 can be connected to the Internet, a PC, a server, or the like via an IP network.

  The graphic controller 18 is means for drawing image data at high speed and displaying the image data on the display 21. The graphic controller 18 has a video input interface, and the image data created by the CPU 11 and the video input from the video input interface are placed at arbitrary positions. It can be displayed superimposed.

  The MPEG decoder 19 is means for separating and expanding AV data compressed in the MPEG format, and can display the expanded video on the display 21 via the graphic controller 18. The MPEG decoder 19 can output the audio expanded by the MPEG decoder 19 to the audio input terminal of the display 21 or another amplifier (not shown) via the DAC.

  The external bus I / F 20 is an interface that connects the internal bus 15 and the external bus 22. In the present embodiment, IEEE 1394 is adopted as the external bus 22, and therefore an interface conforming to IEEE 1394 is adopted as the external bus I / F 20. The DVCR 23 is connected to the external bus 22 and is a digital video cassette recorder that records and reproduces AV data.

  In addition, the external bus 22 secures a band necessary for data transfer between connected devices when real-time performance is required, for example, when sequentially reproducing images while transferring. A bus that can be. In the present embodiment, an IEEE 1394 bus is adopted as an example of the external bus 22. Note that IEEE 1394 is a standard for device connection interfaces and buses.

  With respect to the present embodiment, an operation when reproducing AV data compressed in the MPEG2 format stored in the DVCR 23 on the display 21 will be described.

  Hereinafter, before explaining the arbitration operation of the bus arbitration circuit 16, an outline of AV data transfer will be briefly described. In order to display the AV data stored in the DVCR 23 on the display 21, procedures such as control and authentication of the DVCR 23, AV data list display and selection of reproduction data are necessary. Therefore, the description of the detailed description is omitted, and only the AV data transfer operation will be described.

  That is, when the DVCR 23 transmits AV data to the external bus I / F 20 via the external bus 22, the external bus I / F 20 stores the received AV data in a buffer (not shown).

  More specifically, in the present embodiment, since the external bus 22 is an IEEE 1394 bus, the following processing is performed. That is, in the IEEE 1394 bus, any of the devices on the bus plays the role of an isochronous resource manager. The isochronous resource manager controls the isochronous transfer that is the IEEE1394 synchronous data transfer. When any of the devices on the bus (DVCR 23 in this case) requests the isochronous transfer, the isochronous resource manager Assign an isochronous transfer channel to.

  When a channel is assigned, the DVCR 23 divides the AV data requested to be transferred from the information processing apparatus 1 and adds, for example, information necessary for isochronous transfer such as a channel number assigned to each, It is sent to the IEEE1394 bus as an isochronous packet. In IEEE 1394, a device that transmits synchronous data is defined so as to periodically transmit a fixed amount of isochronous packets, and the total amount of packets transmitted in each cycle is determined by the bit rate of AV data to be reproduced. Here, in IEEE1394, the period is defined as 125 μsec.

  Further, the IEEE 1394 I / F as the external bus I / F 20 receives the isochronous packet transmitted from the DVCR 23 by identifying it from the channel number added thereto, removes the information for isochronous transfer on the IEEE 1394 bus, and temporarily buffers it. To store.

  As described above, when AV data is transmitted to the external bus I / F 20 via the external bus 22 and stored in a buffer (not shown), the external I / F 20 uses the bus of the internal bus 15 to the bus arbitration circuit 16. Request rights.

  The bus arbitration circuit 16 arbitrates the right to use the bus of the internal bus 15, and gives the external bus I / F 20 permission to use the internal bus 15 at an appropriate timing, as will be described in detail later.

  On the other hand, while the right to use the internal bus 15 is given, the external bus I / F 20 transfers the data stored in the buffer (not shown) via the internal bus 15 to the transmission destination (in this case, an MPEG decoder). 19).

  The above processing, that is, the bus use right request by the external bus I / F 20, the bus use right arbitration processing by the bus arbitration circuit 16, the use right grant to the external bus I / F 20 by the bus arbitration circuit 16, and the external bus I / F Thereafter, the data transfer by F20 is repeated until the transmission of the AV data is completed, and more specifically, until the reproduction of the AV data stored in the DVCR 23 on the display 21 is stopped by the CPU 11.

  On the other hand, the MPEG decoder 19 receives AV data sent to the internal bus 15 from the external bus I / F 20, temporarily stores it in a buffer (not shown), and converts the AV data stored in the buffer into video data, audio data. Divide into data. Further, the MPEG decoder 19 performs decompression processing on the separated video data and audio data, respectively, the video data is reproduced on the display 21 via the graphic controller 18, and the audio data is not shown. Output via the DAC.

  Here, the bus arbitration circuit 16 predicts the timing of the bus use right request repeated by the external bus I / F 20, and before the next bus use right request is issued from the external bus I / F 20, Arbitration processing for giving the bus use right to the I / F 20 is started, and the use permission of the internal bus 15 is given to the external bus I / F 20 before the bus use right request is issued.

  Hereinafter, the configuration and operation of the bus arbitration circuit 16 will be described in detail with reference to FIGS. 2 and 3. That is, FIG. 2 is a block diagram showing a detailed configuration of the bus arbitration circuit 16. As shown in FIG. 2, the bus arbitration circuit 16 includes a REQ detection unit 30, a GNT transmission unit 31, a bus usage right selection unit (bus arbitration unit) 32, a register (storage unit) 33, and a PCI bus monitoring unit 34. Yes.

  The REQ detection unit 30 is a part that detects the input of the REQ signal from each device of the internal bus 15 (REQ1 to REQ4 in the example of FIG. 2), and includes an Ethernet I / F 17, a graphic controller 18, an MPEG decoder 19, and an external bus. It is connected to each device of the I / F 20 in a point-to-point manner. The REQ signal is a signal indicating whether or not each device requests a bus use right. When each device requests a bus use right, the device outputs a REQ signal indicating validity.

  The GNT sending unit 31 is connected to each device of the internal bus 15 in a point-to-point manner. In order to notify permission of use of the internal bus 15 to a certain device, the Ethernet I / F 17 and the graphic controller 18 are used. The GNT signal (GNT1 to GNT4 in the example of FIG. 2) is output to each device of the MPEG decoder 19 and the external bus I / F 20. The GNT signal is a signal indicating whether or not the bus arbitration circuit 16 gives each device permission to use the internal bus 15, and the GNT sending unit 31 grants permission to use a certain device to the internal bus 15. When given, a GNT signal indicating validity is output to the device, and a GNT signal indicating invalidity is output to the remaining devices.

  The internal bus monitoring unit 34 is a part that monitors the state of the internal bus 15, and monitors a signal indicating the state of the internal bus 15 (for example, in the case of the internal bus 15, PCI clock, IRDY, FRAME, etc.) The state of the internal bus 15 can be grasped. Since the internal bus monitoring unit 34 only needs to be able to grasp the state of the internal bus 15, it is not necessary to connect all the signal lines of the internal bus 15.

  Note that each device connected to the REQ detection unit 30 and each device connected to the GNT transmission unit 31 are the same, and the connection between these devices and the internal bus 15 is illustrated in FIG. Was omitted.

  Further, the bus arbitration circuit 16 according to the present embodiment is provided with a register 33, which is used for the bus usage right selection unit 32 to predict when the synchronization device next requests the bus usage right. Prediction information can be stored.

  The register 33 can store information (bus use permission time information) indicating a period during which a bus use right should be given to the synchronous device.

  In the present embodiment, among the information necessary for the operation of the bus usage right selection unit 32, as a prediction information, a cycle in which the synchronous device requests the bus usage right (that is, a cycle in which the synchronous device transmits a data string). ) Information is stored. Further, in the present embodiment, band information of synchronization data (for example, AV data) transmitted by the synchronization device is stored as the bus use permission time information.

  Further, the CPU 11 can read and write the register 33 via the host bus 12, and can write the prediction information and the bus use permission time information in the register 33. These pieces of information are information determined based on characteristics of the synchronization device, that is, characteristics that define the operation and function of the synchronization device. The characteristics include, for example, whether the device is a device that transfers AV data or a device that communicates with a standard communication standard.

  Note that when the characteristics of the synchronization device are fixed, the CPU 11 may always write constant information determined based on the characteristics as the information, but the CPU 11 according to the present embodiment, for example, Based on which device the data transfer is instructed (in this example, the DVCR 23 is instructed to transfer the AV data), the characteristics of the synchronous device are detected, and information corresponding to the characteristics is detected. Is set in the register 33.

  As described above, the CPU 11 according to the present embodiment detects the characteristics of the synchronous device connected to the internal bus 15, and sets the prediction information in the register 33 of the bus arbitration circuit 16 based on the detection result. ing. Therefore, the prediction information can be changed according to the characteristics of the synchronous device currently connected to the internal bus 15. As a result, the bus arbitration circuit 16 can arbitrate the internal bus 15 so that the synchronization device currently connected to the internal bus 15 can transmit the synchronization data more reliably, and can transmit the synchronization data more reliably. The information processing apparatus 1 can be realized.

  Furthermore, the bus usage right selection unit 32 determines the following depending on the input status of the REQ signal from the REQ detection unit 30, the information set in the register 33, and the state of the internal bus 15 acquired by the internal bus monitoring unit 34. By the method described, a device (device to which usage permission is given) that makes the GNT signal valid is determined.

  Specifically, a counter unit 35 for timing is provided inside the bus use right selection unit 32, and the bus use right selection unit 32 is provided after the synchronous device requests the bus use right. You can count the period and the time since the right to use the bus to the synchronization device. The case where the synchronization device is the external bus I / F 20 will be described in more detail as an example. The bus usage right selection unit 32 uses the counter Cp provided in the counter unit 35 to generate a signal REQ4 from the external bus I / F 20. It is possible to measure the time from when the REQ detection unit 30 detects that is effective. The bus use right selection unit 32 is a time after the bus use right is given to the synchronous device by the counter Cr provided in the counter unit 35, in this example, the signal GNT4 to the external bus I / F 20 is valid. It is possible to measure the time since the REQ detection unit 30 has detected that

  Note that the counters Cp and Cr may be configured by separate counter circuits, for example, as long as the counters Cp and Cr can be counted at a predetermined cycle, or storage areas corresponding to the counters Cp and Cr are provided. The unit 35 may change the count value stored in each storage area at a predetermined cycle.

  Further, the bus use right selection unit 32 predicts the next time when the synchronous device requests the bus use right based on the prediction information stored in the register 33, and predetermines from the predicted time. The arbitration process can be started at a point just before the period. The arbitration process is the same as the process that is performed when the synchronous device actually requests the bus use right. For example, the process for canceling the use permission of the bus use right given to a device other than the sync device. Alternatively, there is a process for instructing the device that has been given the right to use the bus to stop the operation.

  Further, the bus use right selection unit 32 performs, for example, a GNT signal (in this case, a GNT signal given to the synchronous bus (in this case, the external bus I / F 20) only during the period indicated by the bus use permission time information stored in the register 33. , GNT4) can be enabled, etc. to give the bus usage right to the synchronous device.

  The counter unit 35 may have any configuration as long as it can measure the length of each period, but the counter unit 35 according to the present embodiment has a clock of the internal bus 15 (in this example, a PCI clock). The time is counted by counting on the basis of.

  The operation of the information stored in the register 33 and the bus use permission time information 32 based thereon will be described in more detail. In this embodiment, the IEEE 1394 I / F is adopted as the external bus I / F 20, The IEEE 1394 I / F also requests the right to use the bus every 125 μs in order to store synchronous data in the buffer every 125 μs. Further, as described above, the counter unit 35 provided in the bus use right selection unit 32 counts the clock of the internal bus 15 and counts it.

  Along with this, the CPU 11 converts the information of the period (125 μsec) into the count number based on the PCI clock as the internal bus 15 in advance as the prediction information, and the bus arbitration circuit 16. Stored in the register 33.

  For example, when the PCI clock is 33 MHz, the value of the clock count is 4166. Therefore, the CPU 11 stores the value (4166) in the register 33. Note that the prediction information stored as the clock count counts the period after the synchronous device (in this example, the external bus I / F 20) requests the right to use the bus among the counters of the counting unit 35. Used as a preset value of the counter Cp.

  Further, the CPU 11 converts the information on the transfer bandwidth required by the IEEE1394 I / F as the external bus I / F 20 into the usage time of the internal bus 15 required every 125 μsec as the bus use permission time information. The data is stored in the register 33 of the bus arbitration circuit 16. Note that the CPU 11 according to the present embodiment also stores the bus use permission time information in the same manner as the prediction information, with the use time of the internal bus 15 required every 125 μsec as a reference for the PCI clock. Stored in terms of counts. The bus use permission time information stored as the clock count number is obtained after the synchronization device (in this example, the external bus I / F 20) has acquired the bus use right among the counters of the count unit 35. It is used as a preset value of the counter Cr that counts the period.

  For example, when the required transfer bandwidth is 100 Mbps, it is necessary to transfer 12,500 bits every 125 μs. Therefore, when the data width of the PCI bus is 32 bits, the value of the count number stored as the bus use permission information is about 400.

  Here, as described above, the bus arbitration circuit 16 predicts the next time when the synchronous device requests the right to use the bus, so that the time before the time when the synchronous device actually issues the right to use the bus is increased. Specifically, the use permission of the internal bus 15 is given at a time point that is a predetermined period before the predicted value at the time when the synchronization device next requests the bus use right.

  Further, the counter Cr measures the time since the right to use the bus is given to the synchronous device. As will be described later, the bus usage right selection unit 32, when the count value Cr = 0, The use permission of the internal bus 15 for the synchronous device is invalidated.

  Therefore, in the bus use permission time information (about 400 in this example) stored as a preset value of the counter Cr in the register 33, the number of clocks (Cm) indicating the predetermined period is the synchronization device (external This is added to the number of clocks of the usage time of the internal bus 15 required by the bus I / F 20).

  On the other hand, the bus usage right selection unit 32 according to the present embodiment uses the period (125 μsec in this example) stored as the prediction information in the counter Cp when the synchronous device requests the bus usage right. The preset value shown (4166 in this example) can be set. Further, the counter Cp can start counting from the time point and count down its own count value at every count timing indicated by the clock (for example, every rising edge or every falling edge). Further, the bus use right selection unit 32 determines whether or not the count value of the counter Cp matches a predetermined threshold Cm, for example, so that the synchronous device next requests the bus use right. It is possible to determine whether or not a point in time preceding the predicted value at the point in time is a predetermined period. If it is determined that the time has arrived, the bus usage right selector 32 determines that the REQ signal (REQ4 in this case) from the synchronous device (in this case, the external bus I / F 20) is still invalid. When the arbitration process is started by performing the same process as when it is enabled and the arbitration process ends, for example, by enabling the GNT signal (in this case, GNT4) to the synchronous device, The right to use the bus can be given to the synchronous device.

  In addition, the bus usage right selection unit 32 according to the present embodiment performs the above operation when the bus usage right is given to the synchronous device (in this example, when the signal GNT4 to the external bus I / F 20 becomes valid). A preset value (about 400 in the above numerical example) indicating the bus use permission time stored as the bus use permission time information can be set in the counter Cr. Further, the counter Cr starts counting from the time point in the same manner as the counter Cp, and can count down its count value at every count timing indicated by the clock. Also, the bus use right selection unit 32 can determine whether or not the bus use permission time has elapsed by determining whether or not the count value of the counter Cr has become 0, for example. Further, if it is determined that the time has passed, the bus usage right selection unit 32 has given the GNT signal (in this case, GNT4) given to the synchronous device to the synchronous device, for example, by invalidating the GNT signal. Stop granting the right to use the bus. Thus, the synchronization device can open the internal bus 15 and allow other devices to use the internal bus 15.

  In this embodiment, the count is performed every clock of the internal bus 15 (every PCI clock). However, other units may be used as long as the clock has sufficient resolution to measure each of the above periods. Even if one is counted for each clock, the same effect can be obtained.

  Next, details of this operation example will be described with reference to FIG.

  FIG. 3 shows the signals REQ1 to REQ4 input as REQ signals requesting the right to use the bus to the bus arbitration circuit 16 and the GNT signal that the bus arbitration circuit 16 notifies whether the bus can be used or not to the input. It is a timing chart showing an example of a change with the signal of GNT1 to GNT4. In the figure, the valid state of input / output is indicated by a low level of the signal, and the invalid state of input / output is indicated by a high level of the signal. The horizontal axis represents time with T0 as the start time, but the scale is not constant for easy understanding.

  In the period before the external bus I / F 20 as a synchronous device starts transmission of synchronous data (period from T0 to T2), the bus usage right selection unit 32 is an asynchronous device (in this example, the Ethernet I / F 17, The graphic controller 18 and the MPEG decoder 19) are given permission to use the internal bus 15 fairly. For example, at the time of T1, the signal GNT2 is enabled and the bus right is given to the graphic controller 18.

  At time T2, when the validity of the signal REQ4 from the external bus I / F 20 that is a synchronous device is confirmed, the counter Cp of the counter unit 35 in the bus usage right selection unit 33 starts timing. More specifically, the counter Cp starts counting based on the PCI clock, and subtracts 1 from the count value Cp for each count.

  Thereafter, at time T3 after one clock, the bus use right selection unit 33 invalidates the signal GNT2 and validates the signal GNT4 indicating permission to use the bus to the external bus I / F 20. On the other hand, the external bus I / F 20 detects the validity of the signal GNT4 and determines that the use permission of the internal bus 15 has been obtained. At this time, the counter Cr of the counter unit 35 in the bus use right selection unit 33 starts timing. More specifically, the counter Cr starts counting based on the PCI clock, and subtracts 1 from the count value Cr every count.

  The external bus I / F 20 that has acquired the right to use the internal bus 15 is still using the internal bus 15 by the device (the graphic controller 18 in the example of FIG. 3) that had the right to use until the signal GNT4 becomes valid. After the use of the internal bus 15 by the device is finished, the use of the internal bus 15 is started.

  More specifically, since the internal bus 15 according to the present embodiment is a PCI bus, the external bus I / F 20 is connected to the internal bus 15 based on the output state of the IRDY signal and the FRAME signal of the PCI bus. Check if it is in use. When the IRDY signal and the FRAME signal are both invalid, the PCI bus is not used. Therefore, the external bus I / F 20 designates the address of the transfer destination (in this case, the MPEG decoder 19) and sequentially stores the data stored in the buffer as the internal bus 15 when both signals are invalid. Output to the PCI bus.

  On the other hand, the bus use right selection unit 32 of the bus arbitration circuit 16 is from when the signal GNT4 becomes valid until the counter Cr notifies that the time indicated by the bus use permission time information has passed (until T4). In order to ensure the necessary bandwidth of the synchronous device (external bus I / F 20), the signal GNT4 is kept valid even if the signals (REQ1 to REQ3) from other devices become valid. Further, the bus use right selection unit 32 disables the signal GNT4 when the time has elapsed (time T4), and completes the data transmission currently performed by the external bus I / F 20.

  More specifically, the counter unit 35 subtracts 1 from the preset value Cr indicating the necessary transfer band every clock after the signal GNT4 becomes valid, and when the Cr becomes equal to 0 (T4), the bus is used. The right selection unit 32 disables the output of GNT4. As a result, the external bus I / F 20 completes the current data transfer. In addition, the bus usage right selection unit 32 grants the bus use permission until T4 even if the signals REQ1 to REQ3 become valid in the period from T3 to T4 in order to secure the necessary bandwidth of the synchronous device. Absent.

  Here, the counter Cp of the bus arbitration circuit 16 starts counting time T2 when the synchronous device requests the right to use the bus. Further, the bus use right selection unit 32 of the bus arbitration circuit 16 is based on the count value of the counter Cp by a predetermined time before the predicted value when the synchronous device next requests the bus use right. It is determined whether or not the time has come, and the synchronous device starts transmission of AV data from the time when the bus usage right of the synchronous device is released to the time (period T4 to T5). As in the previous period (the period up to T2), the bus use right request by each device is arbitrated.

  More specifically, the bus use right selection unit 32 of the bus arbitration circuit 16 has a period (from T4 to T5) until the external bus I / F 20 that is a synchronous device starts data transfer in the next cycle, that is, The clock Cp of the counter unit 32 subtracts 1 from the count value Cp every clock, and the period until the count value Cp becomes equal to a certain constant value Cm includes all the devices including the external bus I / F 20. For example, the GNT output is fairly enabled by using, for example, a cyclic algorithm. In this period (during the period from T4 to T5), the external bus I / F 20 is in the case where data still remains in the internal buffer, for example, when sudden data transfer other than AV data is required. Furthermore, by enabling the signal REQ4, the right to use the internal bus 15 can be obtained under the same conditions as other devices.

  Further, the bus use right selection unit 32, when the time (T5 time) before the predicted value at the time when the synchronous device next requests the bus use right reaches a time (time T5), the synchronous device (external bus I). Regardless of whether the bus use right is requested from / F20), the arbitration processing of the bus use right of the internal bus 15 is started in the same manner as when the bus use right is requested.

  More specifically, when the count value Cp of the counter Cp becomes equal to the constant value Cm, the bus usage right selection unit 32 makes one of the signals GNT1 to GNT3 to other devices valid. In order to give the right to use the internal bus 15 to the external bus I / F 20, the signal GNT4 is made valid. In the example of FIG. 3, since the signal GNT1 is valid at time T5, the signal GNT1 is invalidated and the signal GNT4 is validated.

  On the other hand, as described above, the external bus I / F 20 tries to obtain the right to use the bus by effectively outputting the REQ signal every predetermined period (in this example, 125 μsec). Therefore, the signal REQ4 is output at time T6 when the above period (in this example, 125 μsec) has elapsed from the time T2.

  Here, as a comparative example, after the bus arbitration circuit receives a request for the right to use the bus from the external bus I / F 20, it arbitrates the right to use the internal bus 15, and after the arbitration is completed, the signal GNT4 is sent to the external bus I / F 20. Is output, a delay associated with the arbitration process occurs.

  However, the bus arbitration circuit 16 according to the present embodiment predicts the time point when the external bus I / F 20 as the synchronization device next requests the bus use right, so that the external bus I / F 20 requests the bus use right. Arbitration processing is started at a time before the time of delivery.

  Therefore, at time T6 when the external bus I / F 20 requests the right to use the bus, the signal GNT4 is already valid. As a result, the external bus I / F 20 can immediately obtain the right to use the internal bus 15.

  When the right to use the internal bus 15 is obtained, the external bus I / F 20 performs the same processing as that at the time T3 and starts data transmission. Specifically, the external bus I / F 20 determines whether or not a device that has a right to use until the signal GNT4 is output is still using the internal bus 15, for example, the IRDY signal of the PCI bus and the FRAME signal. The data transfer is started after the output of the IRDY signal and the FRAME signal is stopped.

  Here, in the bus arbitration circuit 16 according to the present embodiment, the fixed time set by the value Cm is provided in the period between T5 and T6 even if GNT4 becomes effective. This is because a device that has obtained the right to use the bus 15 cannot complete data transfer immediately, and the synchronous device may not be able to start data transfer immediately after obtaining permission to use the internal bus 15. As described above, since the preset value of Cr is added in advance by the value Cm, even if the value Cm is set to a numerical value of 1 or more, the bus usage right selection unit 32 has no trouble. Rather, during the usage time required by the synchronous device (external bus I / F 20), the bus usage right can be given to the synchronous bus.

  In order to immediately start the data transfer of the synchronous device at the start of the cycle, the GNT signal is invalidated, and at the same time, a STOP signal (bus transfer stop signal) for forcibly stopping the bus transfer by the PCI bus monitoring unit 34 is generated. It is also possible to forcibly stop the data transfer of the asynchronous device by enabling it. In this case as well, the synchronization device can be given the right to use the bus without delay at a point earlier than the configuration in which the synchronization device actually requests the right to use the bus and then start the arbitration process. The bus can be arbitrated so that the synchronization device can transmit synchronization data more reliably.

  At the time T6 when the external bus I / F 20 starts the data transfer cycle and the bus usage right is obtained, the bus usage right selection unit 32 resets Cr to a preset value, and, as in the previous cycle, the counter Cr The signal GNT4 is output until the count value Cr becomes 0, and the external bus I / F 20 performs data transfer.

  Thereafter, the same operation is repeated until the CPU 11 stops the reproduction of the AV data stored in the DVCR 23 on the display 21.

  In this manner, the bus arbitration circuit 16 according to the present embodiment predicts the next time when the synchronization device requests the bus use right based on the predetermined prediction information, and determines the predetermined time from that time. Even if the bus use right is not actually requested at the time just before the given period, the same arbitration process as when the bus use right is issued is started and the predetermined bus use permission time information The right to use the bus is given to the synchronous device during the period shown. Therefore, the external bus I / F 20 can transfer AV data to the MPEG decoder 19 at an appropriate timing while always securing a necessary transfer band.

  As described above, transfer of AV data from the external bus I / F 20 to the MPEG2 decoder 19 via the PCI bus as the internal bus 15 is performed after securing the transfer timing and transfer band, so that it is reproduced. There is no degradation of playback quality such as video noise or dropout, audio noise or interruptions.

  In addition, the bus arbitration circuit 16 according to the present embodiment predicts the next time when the synchronization device requests the right to use the bus on the basis of predetermined prediction information, and has a predetermined period from that time. Even when the bus use right is not actually requested at the previous time point, the jitter in data transfer can be suppressed by starting the same arbitration process as when the bus use right is issued. Buffer capacity can be minimized. As a result, the delay from selecting the AV data of the DVCR 23 to actually reproducing it on the display 21 is reduced, and the operability can be prevented from being lowered.

  Here, in order to secure a data transfer band, when setting a necessary timer preset value according to the maximum transferable band of the internal bus 15 such as the PCI bus, the maximum transferable value of the internal bus 15 such as the PCI bus is set. Since the bandwidth changes depending on various conditions such as the load status of the CPU 11 and the occurrence of overhead due to the switching of the bus usage right between the synchronous device and the asynchronous device, the maximum transfer bandwidth that can be transferred by the internal bus 15 such as the PCI bus. The actual value becomes an unintended value, and as a result, there is a problem that it becomes impossible to secure a data transfer bandwidth required for the synchronous data.

  In addition, because there is no upper limit set for the preset value of the timer, the asynchronous device requests the use of the bus while it has the right to use the bus continuously to secure the transfer bandwidth required by the synchronous device. In such a case, there is a problem that the delay until the asynchronous device acquires the right to use the bus becomes so large that it cannot be ignored, and the performance of the entire system is degraded. At this time, if the setting value exceeds the processing timeout of the asynchronous device, there is a risk of causing a fatal error.

  On the other hand, the bus arbitration circuit 16 according to the present embodiment gives the right to use the internal bus 15 to the external bus I / F 20 as the synchronization device for the time indicated by the bus use permission time information. Therefore, unlike the configuration that is set according to the maximum transferable bandwidth of the internal bus 15, the synchronization device can be given the right to use the internal bus 15 only for the time required for the synchronization device to transmit the synchronization data, The time for giving the right to use the internal bus 15 to the synchronization device can be limited to a value sufficient for transmission of the synchronization data by the synchronization device. As a result, it is possible to reduce the possibility of the fatal error and the performance degradation of the entire system.

[Second Embodiment]
Next, a second embodiment will be described. The information processing apparatus 1a of the present embodiment is substantially the same as that of the first embodiment, but the transfer band setting method (bus use permission time information setting method) by the bus arbitration circuit is different.

  Specifically, in the information processing apparatus 1 a according to the present embodiment, a bus arbitration circuit 16 a is provided instead of the bus arbitration circuit 16. The bus arbitration circuit 16 a has substantially the same configuration as the bus arbitration circuit 16, but a bus use right selection unit 32 a is provided instead of the bus use right selection unit 32. The bus use right selection unit 32a performs substantially the same operation as the bus use right selection unit 32, but the bus use permission time information stored in the register 33 is set to the external bus I / F 20 in the previous cycle. Can be updated based on the amount of data actually transferred. Further, unlike the bus usage right selection unit 32, the bus usage right selection unit 32a is a period in which the external bus I / F 20 is actually transferring based on the monitoring result of the internal bus 15 by the internal bus monitoring unit 34. Only the counter Cr of the counter unit 35 can be timed. As a result, the bus use permission time information can be updated as required by the synchronization device.

  The remaining operation of the bus usage right selection unit 32a, the remaining configuration of the bus arbitration circuit 16a, and the remaining configuration of the information processing device 1a are the same as those in the first embodiment, and thus have the same configuration and function. About the member which has, the same referential mark is attached | subjected and description is abbreviate | omitted.

  Next, the operation of this embodiment will be described.

  At the start of data transfer, the same operation as in the first embodiment is performed. Here, in the first embodiment, for example, according to an instruction from the CPU 11 or the like, the register 33 of the bus arbitration circuit 16 stores in advance information on the transfer band required by the external bus I / F 20 (bus use permission time information). Is stored, and its value is always constant.

  On the other hand, in the present embodiment, the bus usage right selection unit 32a of the bus arbitration circuit 16a actually transfers the external bus I / F 20 in the previous cycle in each transmission cycle of the synchronous data. Based on the amount of data performed, the bus use permission time required to secure a desired transfer bandwidth is calculated and stored in the register 33. As a result, the bus use permission time information in the register 33 is sequentially updated to a value necessary for securing a desired transfer band for each cycle.

  That is, in the period from T2 to T6, which is the first cycle in which the external bus I / F 20 in FIG. 3 performs data transfer, the bus usage right selection unit 32a determines the amount of data actually transferred by the external bus I / F 20 as follows. Calculation is based on the state of the internal bus 15 detected by the internal bus monitoring unit 34. Furthermore, the bus use right selection unit 32a calculates a bus use permission time necessary for transmitting the data amount based on the data amount, and in the second period (period started from the time point T6). It is stored in the register 33 as the bus use permission time information to be used.

  In this embodiment, the bus use permission time information is calculated as the number of clocks based on the clock of the internal bus 15, and the value is used as a preset value of the counter Cr. Accordingly, the bus use right selection unit 32a calculates the bus use permission time information as the number of clocks, and sets it in the counter Cr as a preset value Cr1 indicating the necessary bandwidth in the second period starting from the time point T6. When the internal bus 15 is a PCI bus, both the IRDY signal and the TRDY signal are valid when data is actually transferred. Therefore, the bus use right selection unit 32a can detect a period during which the external bus I / F 20 is actually transmitting data based on the state and time of both signals, and the internal bus can be detected during this period and one clock period. 15, the amount of data actually transferred by the external bus I / F 20 can be detected. Therefore, the bus use permission time information 32a can set the preset value Cr1 based on the data amount.

  After the signal GNT4 is validated, the bus usage right selection unit 32a checks the state of the internal bus 15 based on the monitoring result of the internal bus monitoring unit 34, and when data is actually being transferred. Therefore, the counter Cr of the counter unit 35 is counted down, and the signal GNT4 is kept valid until the count value of the counter Cr set to the preset value Cr1 becomes equal to 0 at the time point T5.

  Thereafter, the bus usage right selection unit 32a sequentially sets the value of Cr (n−1) based on the actual data transfer amount in the (n−1) th cycle in the nth cycle, Secure the transfer bandwidth of the synchronization device. Other operations are the same as those in the first embodiment.

  In this way, the bus arbitration circuit 16a secures the bandwidth of the internal bus 15 based on the data transfer amount actually performed by the synchronization device. As a result, the bus arbitration circuit 16a can stably secure a transfer band required for the synchronization data, and can also effectively use the internal bus 15.

  In addition, the bus arbitration circuit 16a according to the present embodiment monitors the state of the internal bus 15 to detect whether or not the synchronization device is actually transmitting a data string, and the synchronization device detects the data string. The length of the period during which the permission signal is supplied to the synchronization device is controlled so that the total period during which the transmission is actually performed becomes the time indicated by the preset bus use permission time information. Therefore, as compared with the first embodiment, it is possible to give the synchronization device the right to use the internal bus 15 for a time necessary for the synchronization device to transmit the synchronization data, and to the synchronization device. The time for which the right to use the bus 15 is granted can be limited to a value sufficient for transmission of synchronous data by the synchronous device. As a result, it is possible to further reduce the possibility of the fatal error and the performance degradation of the entire system.

[Third embodiment]
Next, a third embodiment will be described. The information processing apparatus 1b of the present embodiment is substantially the same as that of the first embodiment, but is necessary after the bus arbitration circuit limits the bus time continuously secured by the synchronization device. The difference is that arbitration is performed so as to secure the transfer bandwidth.

  Specifically, in this embodiment, in addition to the prediction information and the bus use permission time information stored in the register 33 described above, all of the registers connected to the internal bus 15 are registered in the register 33 of the bus arbitration circuit 16b. The bus usage right waiting time information (bus usage right waiting time information) is stored for the device. The bus use right waiting time is the maximum allowable delay time from when the device requests the bus use right until the right to use the internal bus 15 can be acquired. For example, the bus use right waiting time is based on the clock of the internal bus 15. The number of clocks is stored in the register 33b and used as a preset value. As an example, in the following, it is assumed that the bus usage right waiting time information for the Ethernet I / F 17 is Cd1, the bus usage right waiting time information for the graphic controller 18 is Cd2, and the like.

  Further, in the bus arbitration circuit 16b according to the present embodiment, the counter unit 35 of the bus usage right selection unit 32b corresponds to each device of the internal bus 15 after each device requests the bus usage right. Counters (in this example, Cd1 to Cd3) for measuring time are provided.

  When the REQ detection unit 30 detects the REQ signal from each device, the bus use right selection unit 32b of the bus arbitration circuit 16b instructs the counter corresponding to the device that detected the REQ signal to measure the time. It is determined whether or not the elapsed time from the start of time measurement has exceeded the time indicated by the bus use right waiting time information stored in the register 33b, and if this time is exceeded, the bus use right is given to the synchronous device. Even if it is given, the bus use right can be temporarily given to a device whose elapsed time exceeds the bus use right waiting time. Note that the time for temporarily giving the bus use right to the device is a time that does not affect even if the data transfer is interrupted. For example, the CPU 11 writes the data to the register 33b and selects the bus use right in advance. Is set in the section 32b.

  In the present embodiment, the counters Cd1 to Cd3 count and count the clock (PCI clock) of the internal bus 15 in the same manner as the counters Cp and Cr described above. The bus use right selection unit 32b writes preset values to the clocks Cd1 to Cd3 at the start of timing, instructs the clocks Cd1 to Cd3 to count down, and the count values of the clocks Cd1 to Cd3 become zero. Whether or not the elapsed time has exceeded the bus use right waiting time is determined. Accordingly, in the present embodiment, a member that sets a value in the register 33b (for example, the CPU 11 or the bus use right selection unit 32b) is similar to the counters Cp and Cr described above, and the bus use right waiting time. Is converted into the number of clocks and written to the register 33b as bus use right waiting time information.

  As with the counters Cp and Cr, these counters Cd1 to Cd3 may also be configured from separate counter circuits, for example, as long as they can be counted at predetermined intervals, and correspond to the counters Cd1 to Cd3. A storage area is provided, and the count unit 35 may change the count value stored in each storage area at a predetermined cycle.

  The remaining operation of the bus usage right selection unit 32b, the remaining configuration of the bus arbitration circuit 16b, and the remaining configuration of the information processing device 1b are the same as those in the first or second embodiment, and thus the same configuration. And about the member which has a function, the same referential mark is attached | subjected and description is abbreviate | omitted.

  Next, the operation of this embodiment will be described with reference to FIG.

  FIG. 4 is a timing chart showing an example of changes in the signals REQ1 to REQ4 input to the bus arbitration circuit 16b and the signals GNT1 to GNT4 output from the bus arbitration circuit 16b in response to the input, as in FIG. It is.

  At time T11, when the synchronization device enables the signal REQ4 to start data transfer, the bus arbitration circuit 16b has already enabled the signal GNT4 in the same manner as in the first or second embodiment. ing. Therefore, the external bus I / F 20 immediately starts data transfer.

  When the signal REQ4 becomes valid, the counter Cp of the counter unit 35 starts counting (clocking), and 1 is subtracted from the count value Cp every count. In addition, since GNT4 is already effective in T11, the count-down (clocking) of the counter Cr has already started.

  At time T12, the signal REQ1 is validated in order for the Ethernet I / F 17 to start data transfer via the internal bus 15 for some reason such as reception of data. However, the bus arbitration circuit 16b gives the right to use the internal bus 15 to the external bus I / F 20, and is set to a value (in this case, 0) for securing the transfer band required by the count value of the counter Cr. Since it has not reached, the signal GNT1 is left invalid. Therefore, the counter unit 35 instructs the counter Cd1 for measuring the time from when the signal REQ1 becomes valid to start the countdown.

  At time T13, when the maximum allowable delay time until acquisition of the bus usage right of the Ethernet I / F 17 is reached, the count value Cd1 of the counter Cd1 becomes equal to 0, and the bus usage right selection unit 32b causes the Ethernet I / F 17 to use the bus. It is determined that the bus use right waiting time has elapsed since the request for the right was issued. Accordingly, the bus use right selection unit 32b does not have to have passed the bus use permission time since the bus use right has been given to the synchronous device, that is, even if the count value Cr of the counter Cr has not reached zero. The signal GNT4 is invalidated and the signal GNT1 is validated. At the same time, the bus use right selection unit 32b interrupts the countdown (time count) of the counter Cr. On the other hand, the Ethernet I / F 17 starts data transfer because the signal GNT1 becomes valid.

  At time T14 when one clock or a preset period has elapsed from the time T13, the bus use right selection unit 32b invalidates the signal GNT1 and validates the signal GNT4 again. The preset time is a time that does not affect even if the synchronous device interrupts data transfer, and is determined at the time of initial setting based on the characteristics of each device connected to the internal bus 15. ing.

  Since the signal GNT1 becomes invalid, the Ethernet I / F 17 interrupts the use of the internal bus 15 after transferring a certain amount of data. The external bus I / F 20 confirms that the internal bus 15 is not being used, and starts data transfer.

  Thereafter, the same operation is repeated until the count value Cr of the counter Cr reaches 0 at time T16. During this time, the signal REQ2 is valid at the time point T15, but when the count value Cr of the counter Cr reaches 0, the count value Cd2 of the counter Cd2 has not become 0. 32b leaves the signal GNT2 invalid.

  Other operations are the same as those in the first and second embodiments.

  As described above, the bus arbitration circuit 16b according to the present embodiment performs the arbitration in consideration of the maximum allowable delay time of all the devices, thereby securing the transfer band required for the synchronization data, while maintaining the system. Overall performance degradation can be avoided.

  In the third embodiment, the bus use right to the synchronous device is temporarily released by the maximum allowable bus use wait time of the asynchronous device other than the preset synchronous device. In 16b, the right to use the bus may be given multiple times regardless of the waiting time.

  In this case, permission to use the internal bus 15 is given in a plurality of times in response to a request for the right to use the bus from the synchronous device. Therefore, the length of the use permission continuously given to the synchronous device can be shortened as compared with the configuration in which the use permission of the internal bus 15 is given once for each request for the bus use right. The time from requesting the right to use the bus until the use permission is granted can be shortened.

  In addition, the bus arbitration circuit 16b according to the present embodiment, when the synchronous device has obtained the right to use the internal bus 15, a device other than the synchronous device (such as an asynchronous device or a synchronous device that has not obtained the right to use). ) To measure the elapsed time since the right to use the internal bus 15 is requested, and if the elapsed time exceeds a predetermined bus use permission time, the synchronous device is temporarily set for a preset time. The right to use the internal bus 15 is released, and the right to use the internal bus 15 is given to the device.

  As described above, when the elapsed time from the request for the right to use the internal bus 15 from a device other than the synchronous device exceeds the bus use permission time, the right to use the internal bus 15 is temporarily given to the device. Therefore, the time from when another device requests the right to use the internal bus 15 until the use permission is given can be kept within the maximum allowable time.

  Therefore, it is possible to suppress a decrease in the performance of the entire system due to a delay in permission to use other devices. In addition, since delays in use permission can be suppressed, the following problems, that is, problems that cause a fatal error when the delay exceeds the device processing timeout, will occur. Can be prevented.

  In the first to third embodiments, the case where the number of synchronization devices provided in the internal bus 15 is one (only the external bus I / F 20) has been described as an example. The number is not limited to the above, and a plurality of numbers may be used. For example, when there are two or more synchronous devices on the internal bus 15 such as when both the MPEG2 decoder 19 and the external bus I / F 20 are synchronous devices, the timing of the device having a short data transfer cycle can be adjusted. It is determined that the demand for is larger. Therefore, the synchronous device having the shortest data transfer cycle is the target for the bus arbitration circuit 16 (16a and 16b) to match the transfer timing.

  In this configuration, for the synchronous device having the shortest data transfer cycle, the arbitration start time is determined based on the prediction information, and the arbitration process from the arbitration start time is performed. Therefore, for a specific synchronization device that has the shortest cycle of data transfer, and therefore is most required among the plurality of synchronization devices to give the right to use the internal bus 15 at a faster time point without delay. At a faster time, the right to use the internal bus 15 can be given without delay. As a result, the bus arbitration circuit 16 (16a and 16b) can arbitrate the internal bus 15 so that the specific synchronization device can transmit synchronization data more reliably.

  Further, when there are two or more synchronous devices having the same data transfer cycle, the bus arbitration circuit 16 (16a and 16b) grants the use permission of the internal bus 15 in accordance with the transfer timing to one of the synchronous devices. . Further, the bus arbitration circuit 16 (16a, 16b) provides the bus to the asynchronous device after granting the use of the internal bus 15 so that the synchronous device that has obtained use of the internal bus 15 secures the data transfer bandwidth. Before granting the use permission, the use permission of the internal bus 15 is immediately given to another synchronization device according to a predetermined order. At this time, the predetermined order is an order determined in consideration of the operation of the entire system, such as the contents of data transfer and the characteristics of each device, and the bus arbitration circuits 16 (16a and 16b) are determined in advance. The order in which the use permission is given may be determined based on the operation of the entire system according to the procedure described above, or when the operation of the entire system is predicted in advance, a certain order determined according to the prediction result You may give permission to use.

  In this configuration, after giving the synchronization device a bus use permission for a time required for data transfer of the synchronization device to a certain synchronization device, before giving the bus use permission to a device other than each of the synchronization devices, Usage permission is granted to other synchronization devices. Therefore, the bus arbitration circuit 16 (16a and 16b) can give the use permission in preference to the other synchronization devices over the devices other than the synchronization devices, and the synchronization devices can synchronize more reliably. The internal bus 15 can be arbitrated so that data can be transmitted.

  The PCI bus in each of the above embodiments is an example of the bus of the present invention, and is shared by synchronous devices and asynchronous devices. Each device makes a bus use request to the bus arbitration means when transferring data. The bus arbitration means only needs to be a bus that grants the use permission of a bus to a certain device based on a certain algorithm.

  In each of the above embodiments, the time difference between the prediction result at the time of starting data transmission of the data string of the next synchronization data and the time when the bus arbitration circuit starts arbitration is set to be larger than the time required for the arbitration process. The bus arbitration circuit outputs a permission signal (GNT) for giving the right to use the internal bus 15 to the synchronous device before the synchronous device requests the right to use the internal bus 15. However, it is not limited to this.

  Even if the time difference is smaller than the value set in each of the embodiments, before the synchronous device actually requests the right to use the internal bus 15, the bus arbitration circuit sends the synchronous device to the synchronous device. The same effect can be obtained if it is set to a value at which the arbitration process for giving the bus use right can be started.

  However, as in each of the above embodiments, a time difference is set, and if the bus arbitration circuit outputs a permission signal (GNT) before the request for the right to use the bus, the right to use the bus is not delayed for the synchronization device. Can be given.

  Further, in each of the above embodiments, the case where the prediction information is a period has been described as an example, but the present invention is not limited to this. If the next data transmission start time by the next synchronization device can be predicted, the same effect can be obtained with other information. As an example, according to a predetermined algorithm, the synchronization device makes the average value of the time intervals between the transmission start points of the data string constant, and at least a part of each time interval is different from the other time intervals. In addition, in the case of controlling each time interval, information on the algorithm may be used.

  However, as in the above embodiments, for example, when the synchronization device periodically transmits a data string, the period is preferably used as the prediction information. As an example of this case, when the synchronization device periodically transmits a data string based on the time measurement result of the timer, or the data received by the synchronization device is stored in the buffer and the accumulated amount of the buffer is a predetermined threshold value. In the configuration in which the data is transferred to the bus when the data rate becomes, the speed of the received data is constant.

  Furthermore, a program recording medium that records all or part of a program for executing all or part of the information processing apparatus of the present invention also belongs to the present invention.

  Specifically, in each of the above embodiments, each member constituting the bus arbitration circuit (16, 16a, 16b) is realized only by hardware, and a member that sets information such as prediction information in the bus arbitration circuit in advance. However, the present invention is not limited to the case where the CPU 11 executes the program. Instead of the CPU 11, it may be realized by hardware that performs the same operation as the CPU 11. Moreover, you may implement | achieve all or one part of each member implement | achieved only with hardware with the combination of the program for implement | achieving the function mentioned above, and the hardware (computer) which performs the program.

  When implemented using software, an arithmetic means comprising a CPU or hardware capable of executing the functions described above executes program code stored in a storage device such as a ROM or RAM, and an input / output circuit (not shown) The bus arbitration circuit according to each of the above embodiments can be realized by controlling peripheral circuits such as the above.

  In this case, it can also be realized by combining hardware that performs a part of the processing and the arithmetic means that executes the program code for controlling the hardware and the remaining processing. The arithmetic means may be a single unit, or a plurality of arithmetic means connected via a bus inside the apparatus or various communication paths may execute the program code jointly.

  The program code itself that can be directly executed by the computing means, or a program as data that can be generated by a process such as decompression described later, stores the program (program code or the data) in a recording medium, A recording medium is distributed, or the program is distributed by being transmitted by a communication means for transmitting via a wired or wireless communication path, and is executed by the arithmetic means.

  In addition, when transmitting via a communication path, each transmission medium which comprises a communication path propagates the signal sequence which shows a program, and the said program is transmitted via the said communication path. Further, when transmitting the signal sequence, the transmission device may superimpose the signal sequence on the carrier by modulating the carrier with the signal sequence indicating the program. In this case, the signal sequence is restored by the receiving apparatus demodulating the carrier wave. On the other hand, when transmitting the signal sequence, the transmission device may divide and transmit the signal sequence as a digital data sequence. In this case, the receiving apparatus concatenates the received packet groups and restores the signal sequence. Further, when the transmission apparatus transmits a signal sequence, the signal sequence may be multiplexed with another signal sequence and transmitted by a method such as time division / frequency division / code division. In this case, the receiving apparatus extracts and restores individual signal sequences from the multiplexed signal sequence. In any case, the same effect can be obtained if the program can be transmitted via the communication path.

  Here, it is preferable that the recording medium for distributing the program is removable, but it does not matter whether the recording medium after distributing the program is removable. In addition, the recording medium can be rewritten (written), volatile, or the recording method and shape as long as a program is stored. Examples of recording media include tapes such as magnetic tapes and cassette tapes, magnetic disks such as floppy (registered trademark) disks and hard disks, CD-ROMs, magneto-optical disks (MO), mini-discs (MD) and digital A disk such as a video disk (DVD) may be mentioned. The recording medium may be a card such as an IC card or an optical card, or a semiconductor memory such as a mask ROM, EPROM, EEPROM, or flash ROM. Or the memory formed in calculating means, such as CPU, may be sufficient.

  The program code may be a code for instructing the arithmetic means of all the procedures of the processes, or a basic program capable of executing a part or all of the processes by calling according to a predetermined procedure. If (for example, an operating system or a library) already exists, a part or all of the entire procedure may be replaced with a code or a pointer that instructs the arithmetic means to call the basic program.

  The format for storing the program in the recording medium may be a storage format that can be accessed and executed by the arithmetic means, for example, as in a state where the program is stored in the real memory, or is stored in the real memory. Installed in the local recording medium from the storage format after being installed in a local recording medium (for example, real memory or hard disk) that is always accessible by the computing means, or from a network or a transportable recording medium The previous storage format may be used. Further, the program is not limited to the compiled object code, but may be stored as source code or intermediate code generated during interpretation or compilation. In any case, the above calculation is performed by a process such as decompression of compressed information, decoding of encoded information, interpretation, compilation, linking, allocation to real memory, or a combination of processes. If the means can be converted into an executable format, the same effect can be obtained regardless of the format in which the program is stored in the recording medium.

  As described above, the information processing apparatus including the bandwidth control unit for the internal bus according to the present invention includes one or more synchronizations that periodically transfer a certain amount of data via a bus shared by a plurality of devices. An information processing apparatus including a device retains a data transfer period and a necessary data transfer band that are set in advance based on characteristics of the synchronization device, and transfers the data of the synchronization device to a certain synchronization device. A bus arbitration means for giving a bus use permission for a time required for the synchronization device to the synchronous device before detection of the bus use request at a timing when the bus use request is output from the synchronous device, which is predicted from a set cycle. It is characterized by that.

  Further, in the information processing apparatus having the internal bus bandwidth control means according to the present invention, the bus use permission time given by the bus use permission given by the bus arbitration means is the same as that when the bus is used in the previous cycle. It is characterized in that the device is given so as to be equal to or larger than the bus use time actually used.

  Further, the information processing apparatus including the internal bus bandwidth control unit according to the present invention is configured such that when the bus arbitration unit receives a timing at which a bus use request is output from a synchronous device predicted from a set cycle, The data transfer of the asynchronous device using the bus at the time is interrupted by a bus transfer stop signal.

  Also, in the information processing apparatus having the internal bus bandwidth control means according to the present invention, the bus arbitration means gives the bus use permission in a plurality of times for one bus use request from the synchronous device. It is characterized by that.

  The information processing apparatus having the bandwidth control means for the internal bus according to the present invention may be configured such that, when the bus arbitration means further connects an asynchronous device to the bus, the maximum bus usage right allowed by the asynchronous device. When the waiting time is set in advance and the synchronous device has obtained the right to use the bus, if the waiting time for the asynchronous device's bus usage right becomes the set value, the bus usage right of the synchronous device is temporarily set for the preset time. And the right to use the bus is given to the asynchronous device.

  The information processing apparatus having the bandwidth control means for the internal bus according to the present invention may be configured such that the bus arbitration means has the shortest data transfer cycle when two or more synchronization devices are connected to the bus. A bus use permission is given to a device before a timing at which a bus request is output from the synchronous device.

Further, in the information processing apparatus including the bandwidth control means for the internal bus according to the present invention, when the bus arbitration means is connected to the bus with two or more synchronous devices having the same data transfer cycle, A bus use permission is given to any one of the synchronization devices before the timing at which the bus request is output from the synchronization device, and the bus use permission for the time required for data transfer of the synchronization device is given to the synchronization device. According to the present invention, the bus use permission is given to another synchronous device according to a predetermined order before the bus use permission is given to the asynchronous device. Bus arbitration means that processes synchronized data such as video and audio that need to be guaranteed predicts when the bus use request is output, and from the predicted timing The by previously giving a bus use permission to the synchronization device applicable, the use of immediate bus when the bus use request has occurred enables, it is possible to transfer without delay data.

  According to the present invention, the right to use the bus can be given to the synchronization device at an earlier time without delay, and the bus can be arbitrated so that the synchronization device can transmit the synchronization data more reliably. Therefore, for example, the present invention can be widely and suitably used for various systems capable of transmitting various types of synchronous data via a bus, including AV systems that transmit AV data that requires a strong real-time property via a bus.

It is a block diagram which shows the principal part structure of the information processing apparatus which concerns on 1st implementation of this invention. It is a block diagram which shows the principal part of the detailed structure of the bus arbitration circuit which concerns on 2nd implementation of this invention. It is a timing chart which shows the change of the input-output signal of the bus arbitration circuit which concerns on 1st implementation of this invention. It is a timing chart which shows the change of the input-output signal of the bus arbitration circuit which concerns on 3rd implementation of this invention. It is a block diagram which shows the structure of the conventional information processing apparatus.

Explanation of symbols

1, 1a, 1b Information processing apparatus 11 CPU (setting means)
12 Host bus 13 Memory 14 Host-internal bus bridge 15 Internal bus (bus)
16 Bus arbitration circuit 17 Ethernet I / F (device)
18 Graphic controller (device)
19 MPEG decoder (device)
20 External bus I / F (synchronous device)
32 / 32a / 32b Bus usage right selector (bus arbitration means)
33 / 33b register (storage means)

Claims (14)

In a bus arbitration circuit having bus arbitration means for arbitrating a right to use a bus shared by a plurality of devices including a synchronization device capable of repeatedly transmitting a data string that constitutes synchronization data requiring bandwidth guarantee,
Comprising storage means for storing prediction information for predicting the next data transmission start time by the synchronization device;
When the bus arbitration means detects transmission of synchronous data by the synchronous device, based on the prediction information stored in the storage means, the bus arbitration means is more than the prediction result at the data transmission start time of the data string of the next synchronous data. Determining the previous arbitration start time, and starting the arbitration process of the bus for giving the use right to the synchronization device from the arbitration start time even if the use right is not requested by the synchronization device; A featured bus arbitration circuit.   2. The bus arbitration circuit according to claim 1, wherein the prediction information is information indicating a cycle in which the synchronous device transmits a data string. The time difference between the prediction result of the data transmission start time of the data sequence of the next synchronization data and the arbitration start time is set to be larger than the time required for the arbitration process,
When the bus arbitration means detects the transmission of the synchronization data by the synchronization device, the bus arbitration means sends a permission signal for giving the right to use the bus before the synchronization device requests the right to use the bus. 2. The bus arbitration circuit according to claim 1, wherein the bus arbitration circuit outputs to a device.   4. The bus arbitration circuit according to claim 3, wherein the bus arbitration means gives the permission signal to the synchronous device for a time indicated by preset bus use permission time information.   The bus arbitration means monitors the state of the bus to detect whether the synchronous device is actually transmitting a data string, and during the period during which the synchronous device is actually transmitting the data string. 4. The bus arbitration circuit according to claim 3, wherein a length of a period during which the permission signal is supplied to the synchronous device is controlled so that the total is a time indicated by preset bus use permission time information.   The bus arbitration unit monitors the state of the bus, detects the data amount of the data string actually transmitted by the synchronous device this time, and updates the bus use permission time information according to the detection result. 6. The bus arbitration circuit according to claim 4 or 5, wherein:   When the arbitration start time is reached, the bus arbitration means outputs a bus transfer stop signal to a device other than the synchronous device that is using the bus at that time, and stops data transfer by the device. The bus arbitration circuit according to claim 1.   2. The bus arbitration circuit according to claim 1, wherein the bus arbitration unit gives permission to use the bus in a plurality of times in response to a request for the right to use the bus from the synchronous device.   The bus arbitration means counts an elapsed time since the right to use the bus from a device other than the synchronous device is requested when the synchronous device has acquired the right to use the bus. When a predetermined bus use permission time is exceeded, the bus use right of the synchronous device is temporarily released for a preset time, and the bus use right is given to the device. Item 2. The bus arbitration circuit according to Item 1.   When two or more synchronization devices are connected to the bus, the bus arbitration unit determines the arbitration start time for the sync device having the shortest data transfer cycle, and starts the arbitration from the arbitration start time. 2. The bus arbitration circuit according to claim 1, wherein arbitration processing of the bus for giving a right to use is started.   When two or more synchronous devices having the same data transfer cycle are connected to the bus, the bus arbitration unit determines the arbitration start time for any one of the synchronous devices, and performs the arbitration. After starting the arbitration processing of the bus for giving the right of use to the synchronous device from the start time, and giving the synchronous device the bus use permission for the time required for the data transfer of the synchronous device, the synchronous device 2. The bus arbitration circuit according to claim 1, wherein the bus use permission is given to another synchronous device in a predetermined order before the bus use permission is given to the other devices. A bus arbitration circuit according to claim 1;
A bus in which the right to use by a plurality of connected devices is arbitrated by the bus arbitration circuit;
An information processing apparatus comprising: a setting unit configured to detect characteristics of a synchronous device connected to the bus and set the prediction information in the bus arbitration circuit based on a detection result. A computer program connectable to a bus arbitration circuit and a bus whose use right by a plurality of connected devices is arbitrated by the bus arbitration circuit,
The bus arbitration circuit includes a bus arbitration unit that arbitrates a right to use a bus shared by a plurality of devices including a synchronization device capable of repeatedly transmitting a data string that constitutes synchronization data that requires bandwidth guarantee.
The bus arbitration means, when detecting the transmission of the synchronous data by the synchronous device, based on the prediction information set in advance for predicting the next data transmission start time by the synchronous device, The arbitration start time before the prediction result at the data transmission start time of the data string is determined, and the use right is given to the synchronization device from the arbitration start time even if the use right is not requested by the synchronization device And start the bus arbitration process for
The program is a program for operating the computer as setting means for detecting characteristics of a synchronous device connected to the bus and setting the prediction information in the bus arbitration circuit based on a detection result. A program characterized by   A recording medium on which the program according to claim 13 is recorded.

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