JPH10223868A - Non-volatile semiconductor storage device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a non-volatile semiconductor storage device where a source line can be lessened in resistance without increasing implanted ions and pilled aluminum in amount. SOLUTION: A non-volatile semiconductor memory device is equipped with a groove 14 which is formed as deep as LS1 along a word line by engraving the side face of a semiconductor substrate on the source side of a word line WL in a self-aligned manner and the source region 41 of a memory element M1 which is originally as long as LS but lengthened by a length LS1 ×2 and exposed on the surface of the groove 14, wherein the source region 41 is as long as LS if the groove 14 is not provided, and LS1 denotes the length of a part 41b formed on both the sides of the groove 41. An isolating oxide film 11 is removed from the surface of the substrate 1, the source regions 41 are electrically connected with each other with impurity regions 121 formed as deep as the depth LS1 of the groove 14, and a source line SL1 laid vertical to the direction of channels comprises the source regions 41 and the impurity regions 121.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device and a method of manufacturing the same, and more particularly, to a structure in which a source region of a memory element is extended by a groove provided in a substrate. About what you have.

[0002]

2. Description of the Related Art A DINOR (Divided NOR) flash memory, which is an example of a conventional nonvolatile semiconductor memory device, will be described below with reference to FIGS. A conventional DINOR type flash memory is described in, for example, IEICE Technical Report Vol.93 No.74 P15
-20, Onoda et al.

FIG. 13 is a schematic circuit diagram showing a memory cell array in an arbitrary block of a conventional DINOR type flash memory. In FIG. 13, M (m, n) denotes m rows in the memory cell array, The storage element is located in the n-th column, its gate electrode is connected to the word line WL (m) in the m-th row, and its drain region is in the bit line BL in the n-th column.
(N), and its source region is connected to the source line SL. For example, a chip having a degree of integration of about 16 Mbit usually includes 64 word lines WL and 2048 bit lines BL per block.
Here, as shown in the figure, the source regions of all the storage elements in one block are connected to the source line SL.

FIG. 14 is a plan view of a main part showing the structure of a memory cell array of a conventional DINOR type flash memory, and shows the positions of drain and source regions 3 and 4 of a memory element M, word lines WL and source lines SL. In order to make the relationship clear, the illustration of the sub-bit line 10 is omitted and the positional relationship of each region under the interlayer insulating film 9 is shown. FIGS. 15A, 15B and 15C are cross-sectional views taken along lines AA, BB, and CC of FIG. 14, respectively.

[0005] In FIG. 14 and FIG.
Semiconductor substrate composed of a silicon substrate, 2 is a semiconductor substrate 1
Is a P-type well formed on one main surface of the substrate. Reference numeral 3 denotes a drain region of the storage element M, which is formed on the main surface of the semiconductor substrate 1 so as to be surrounded by the P-type well 2 and to be exposed on the surface of the substrate 1. Reference numeral 4 denotes a source region of the storage element M, which is formed on the main surface of the semiconductor substrate 1 like the drain region 3 so as to be surrounded by the P-type well 2 and to be exposed on the surface of the substrate 1, and Impurity regions 12 formed at positions where the isolation oxide film 11 has been removed from the surface of the substrate 1 are electrically connected to each other, and together with the impurity regions 12, constitute a source line SL wired in a direction perpendicular to the channel direction. .

Reference numerals 5 to 8 denote members constituting the gate electrode of the storage element M. Specifically, reference numeral 5 denotes a gate insulating film made of a tunnel oxide film formed on the main surface of the semiconductor substrate 1, and 6 denotes a polycrystalline silicon film or an amorphous silicon film formed on the gate insulating film 5. A floating gate (hereinafter, referred to as “FG”) made of a conductive film such as a film;
Is a gate interlayer film formed on FG6, for example, T
A three-layer laminated film (hereinafter, referred to as “ONO film”) including EOS (Tetraethoxysilane), a silicon nitride film, and TEOS, and a control gate (hereinafter, referred to as a polycrystalline silicon film) 8 formed on the ONO film 7. "CG") and constitutes a part of the word line WL wired vertically in the channel direction.

Reference numeral 9 denotes an interlayer insulating film formed on the word line WL, the source line SL, the isolation oxide film 11, and the drain region 3 so as to cover them. Reference numeral 10 denotes an electrical connection between the drain region 3 and the connection surface 3a. Are connected in the channel direction. Reference numeral 11 denotes an isolation oxide film formed on the semiconductor substrate 1 and configured to electrically isolate the storage elements M from each other, for example, a LOCOS oxide film. Here, a part of the FG 6 extends on the isolation oxide film 11 via the gate insulating film 5. Also, impurity region 1
The isolation oxide film 11 formed on the substrate 2 is removed, and a substrate recess 1a is formed at a position where the isolation oxide film 11 is removed.

Next, the conventional DI constructed as described above
FIG. 1 shows a method of manufacturing a NOR flash memory.
6 will be described. FIG. 16 is a cross-sectional view of a main part showing a method of manufacturing a conventional DINOR type flash memory, in the order of steps, with respect to a cross section taken along line AA of FIG.

First, as shown in FIG. 16A, a P-type well 2 is formed on one main surface of a semiconductor substrate 1 made of, for example, a P-type silicon substrate, and then a LOCOS isolation film 11 is formed.
Is formed at a desired position, and a gate insulating film 5 is formed on the main surface of the substrate 1 by, for example, a thermal oxidation method.
A first conductive film 6a made of, for example, a polycrystalline silicon film or an amorphous silicon film or the like to be G6 is deposited using a CVD method, and is patterned into a desired shape using a normal photoengraving technique. Defines the length in the direction perpendicular to the channel direction.

Subsequently, on the entire surface of the semiconductor substrate 1, TEOS, a silicon nitride film and a TEO
An ONO film is formed by sequentially depositing three layers of S.
On the film 7, a second conductive film 8a to be a CG 5, for example, a polycrystalline silicon film or a compound film of polycrystalline silicon and a high melting point metal is deposited by a CVD method.

Thereafter, the gate insulating film 5, the first conductive film 6a, the ONO film 7, and the second conductive film 8a formed on the substrate 1 are patterned into desired shapes by photolithography. However, the patterning here is performed only on the drain region 3 side, and is not performed on the source region 4 side. Next, using the patterned gate electrode as a mask, for example, phosphorus or arsenic ions are implanted into the main surface of the semiconductor substrate 1 to form the drain region 3.

Next, as shown in FIG. 16B, the source regions 4 of the respective storage elements M are arranged in a direction perpendicular to the channel direction on the surface of the semiconductor substrate 1 (in FIG. 16, in a direction perpendicular to the paper). Part and source region 4 of each storage element M
A resist mask 13 having an opening on isolation oxide film 11 for isolating a portion to be formed is formed on second conductive film 8a.

Next, as shown in FIG. 16C, the first and second conductive films 6a and 8a are processed by anisotropic etching using the resist mask 13 to form an FG6.
And the CG 8 are formed, and the isolation oxide film 11 is removed so that a portion serving as the source region 4 of each storage element M arranged in a direction perpendicular to the channel direction is connected, and the semiconductor covered with the isolation oxide film 11 is formed. The surface of the substrate 1 is exposed.
Hereinafter, this anisotropic etching is referred to as SAS (self-aligned source) etching.

Next, phosphorus or arsenic ions are implanted using the resist mask 13 to form the source region 4.
At this time, on the surface of the semiconductor substrate 1 exposed by the SAS etching step and in the vicinity thereof, the source region 4 of each storage element M arranged in a direction perpendicular to the channel direction is covered with the semiconductor substrate 1 covered with the isolation oxide film 11. The source line SL having a connected structure is formed by the impurity region 12 formed on the surface and in the vicinity thereof. After the above ion implantation,
The resist mask 13 is removed.

Thereafter, an interlayer insulating film 9 is deposited on the entire surface of the semiconductor substrate 1, a connection hole is formed in the connection surface 3a on the surface of the drain region 3 by photolithography, and a conductive hole is formed on the entire surface of the semiconductor substrate 1. The sub-bit line 10 is formed by forming a layer and patterning, and by applying an appropriate heat treatment, a DINOR type flash memory having the structure shown in FIGS. 14 and 15 is obtained.

[0016]

However, in the above-mentioned nonvolatile semiconductor memory device, since the resistance value of the source line SL is large, the read operation of the memory element M (P
(when a log or erase state is detected), the read operation becomes unstable, resulting in a problem of lack of reliability.

More specifically, the resistance of the source line SL is generally about 100 ohms per sheet. For example, the length of one cell in the channel direction is 1.5 μm. When the width of SL is 0.3 μm, 5 sheets per cell (= 1.5 / 0.3)
As a result, each cell has a resistance of about 500 ohms.

In the read operation of the memory element M (m, n), for example, as shown in FIG. 17, when a high-speed read operation is performed using a single-ended sense amplifier SA, a read current of 30 to It is necessary to supply a current of about 50 μA to the storage element M (m, n).
If the connection is made using only the source line SL formed on the surface of the substrate 1 as described above, the diffusion resistance R (m, n) becomes parasitic, and the potential drop due to the diffusion resistance R (m, n) is caused by the storage element M The (m, n) read operation is disturbed.

Specifically, for example, when 16 cells are connected only by the source line SL, the diffusion resistance parasitic on the source line SL is about 8 k ohm (= 500 ohm × 16 cells), and the read current is 30 μA. Then, the potential drop in the source line SL is 0.24 V (= 8 k ohm × 3).
0 μA). Here, at the time of reading, since a voltage of about 1 V is generally applied to the bit line BL, a potential drop of about 25% occurs due to the diffusion resistance in the source line SL.

The threshold voltage of the storage element increases due to the potential drop as described above, that is, the back gate effect (also referred to as “substrate effect” or “substrate bias effect”) due to the reverse bias voltage applied to the substrate. I will. For this reason, even in a memory element that has been normally written and erased, the threshold voltage thereof is erroneously read, and as a result, a reading operation becomes unstable and a problem of lack of reliability has occurred.

In order to solve the above problems, it is necessary to reduce the resistance of the source line SL.

For this purpose, for example, the source lines SL may be connected every few cells by stakeout using low-resistance wires such as aluminum wires. However, if the ratio of the stakeout is increased, the area of the memory cell region is increased by the area of the stakeout portion, and as a result, the chip area is increased and the chip cost is increased accordingly. A new problem arises.

On the other hand, the concentration of ions implanted into the source line SL may be increased. However, in this case, since the source region 4 extends in the channel direction, punch-through tends to occur. That is, when a potential is applied to the drain region 3, a new problem occurs that the depletion layer of the drain is connected to the depletion layer of the source inside the substrate 1.

The present invention has been made in view of the above points, and is a non-volatile memory capable of realizing a lower resistance of the source line without increasing both the ion implantation amount and the aluminum stake amount as compared with the conventional case. It is an object of the present invention to obtain a nonvolatile semiconductor memory device.

[0025]

According to the present invention, there is provided a nonvolatile semiconductor memory device comprising: a first conductive layer formed on one main surface of a semiconductor substrate via a first insulating film; A second conductive layer formed on the layer with a second insulating film interposed therebetween, and a first conductive layer formed so as to oppose the main surface of the semiconductor substrate under the first conductive layer. A plurality of storage elements each having a source and drain region of a mold, a groove formed on the main surface of the semiconductor substrate, and extending each of the plurality of source regions of the plurality of storage elements; Formed on the main surface of the semiconductor substrate,
A first conductivity type impurity region that electrically connects the plurality of source regions included in the plurality of storage elements to each other.

A first conductivity type buried buried in the main surface of the semiconductor substrate so as to be partially exposed at the bottom of the groove and electrically connecting a plurality of source regions of a plurality of storage elements to each other. It has an impurity layer.

Further, the impurity region is a buried impurity layer.

Further, the buried impurity layer is formed in a channel direction.

In the source region extended by the groove,
The portion formed at the bottom of the groove has a higher impurity concentration than the portion formed at the side edge of the groove.

A punch-through suppressing region of a conductivity type different from the first conductivity type is formed on the main surface of the semiconductor substrate and surrounds a portion formed on a side edge of the groove in the source region extended by the groove. It is provided.

According to the method of manufacturing a nonvolatile semiconductor memory device of the present invention, a gate electrode is formed on one main surface of a semiconductor substrate, and the gate electrode is opposed to the main surface of the semiconductor substrate below the gate electrode. In a method for manufacturing a nonvolatile semiconductor memory device including a storage element having source and drain regions formed and a groove formed on a main surface of the semiconductor substrate and extending the source region, the main surface of the semiconductor substrate is provided. Forming a conductive layer serving as the gate electrode thereon, and performing anisotropic etching on the conductive layer using a mask having an opening over a portion serving as the source region of the semiconductor substrate; Exposing, exposing the exposed semiconductor substrate by anisotropic etching using the mask to form the groove, and ion using the mask. The inlet is intended to include a step of forming the source region.

[0032]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. FIG. 1A is a main part plan view showing the structure of the memory cell array of the nonvolatile semiconductor memory device according to Embodiment 1 of the present invention, and shows the drain and source regions 3, 41 of the memory element M1, the word line WL, In order to clarify the positional relationship with the source line SL1, the illustration of the sub-bit line 10 is omitted, and
The positional relationship of each region below the interlayer insulating film 9 is displayed.
FIG. 1B is a cross-sectional view taken along the line AA of FIG.

In FIG. 1, reference numeral 1 denotes a semiconductor substrate formed of, for example, a P-type silicon substrate, and reference numeral 2 denotes a P-type well formed on one main surface of the semiconductor substrate 1. Reference numeral 3 denotes a drain region of the memory element M1, which is formed on the main surface of the semiconductor substrate 1 so as to be surrounded by the P-type well 2 and to be exposed on the surface of the substrate 1.

Reference numerals 5 to 8 denote members constituting the gate electrode of the storage element M1. Specifically, 5 is a semiconductor substrate 1
A gate insulating film formed of a tunnel oxide film formed on the main surface of the gate insulating film; and a floating gate (6) formed on the gate insulating film 5 and formed of a conductive film such as a polycrystalline silicon film or an amorphous silicon film. Hereinafter, referred to as “FG”),
Reference numeral 7 denotes a gate interlayer film formed on the FG 6, for example, a three-layer laminated film (hereinafter, referred to as "ONO film") composed of TEOS, silicon nitride film, and TEOS, and 8 an ONO film 7.
A control gate (hereinafter, referred to as “CG”) formed of, for example, a polycrystalline silicon film formed thereon, and constitutes a part of a word line WL wired perpendicularly to a channel direction.

9 is formed on the word line WL, the source line SL1, the isolation oxide film 11 and the drain region 3 so as to cover them, for example, BPSG (Boro-phosphor).
an interlayer insulating film made of a silicon oxide film such as an oxide glass or TEOS. Reference numeral 10 denotes a sub-bit line electrically connected to the drain region 3 at the connection surface 3a, which is wired in the channel direction. 11
Is an isolation oxide film formed on the semiconductor substrate 1 and made of, for example, a LOCOS oxide film for electrically isolating the storage elements M1 from each other. Reference numeral 14 denotes a semiconductor with respect to the source side surface of the word line WL. This is a groove having a depth Ls ₁ formed along the word line WL by excavating the substrate 1.

Reference numeral 41 denotes a P-type well 2 on the main surface of the semiconductor substrate 1.
And a portion formed on both side edges of the groove by the groove 14 than the length Ls of the groove 14 without the groove 14, that is, the length Ls of the portion 41 a formed at the bottom of the groove 14. 41b is a source region of the storage element M1 which is extended by the length Ls ₁ × 2 and is exposed on the surface of the groove 14. Moreover, the source region 41 is formed by removing the isolation oxide film 11 on the surface of the substrate 1 and further forming the impurity region 121 at a position deeper by the depth Ls ₁ of the groove 14.
, And together with the impurity region 121, constitutes a source line SL1 that is wired perpendicularly to the channel direction.

Next, a method of manufacturing the non-volatile semiconductor memory device thus configured will be described with reference to FIG. FIG. 2 shows a method of manufacturing a nonvolatile semiconductor memory device, and FIG.
4A to 4C are cross-sectional views of relevant parts shown in the order of steps for a cross section taken along line AA of FIG.

First, as shown in FIG. 2A, a P-type silicon substrate is formed on one main surface of a semiconductor substrate 1, for example.
A mold well 2 is formed, and then a LOCOS isolation film 11 is formed at a desired position. Next, a gate insulating film 5 is formed on the main surface of the substrate 1 by, for example, a thermal oxidation method, and FG is formed thereon.
For example, a first conductive film 6a made of, for example, a polycrystalline silicon film or an amorphous silicon film or the like is deposited by a CVD method, and is patterned into a desired shape using a normal photolithography technique. Defines the length in the direction perpendicular to the channel direction.

Subsequently, a TEOS, a silicon nitride film, and a TEO
An ONO film is formed by sequentially depositing three layers of S.
On the film 7, a second conductive film 8a to be a CG 5, for example, a polycrystalline silicon film or a compound film of polycrystalline silicon and a high melting point metal is deposited by a CVD method.

After that, the gate insulating film 5, the first conductive film 6a, the ONO film 7 and the second conductive film 8a formed on the substrate 1 are patterned into desired shapes by photolithography. However, the patterning here is performed only on the side where the drain region 3 is formed, and is not performed on the side where the source region 41 is formed. Next, using the gate end patterned here as a mask, for example, phosphorus or arsenic ions are implanted to form a drain region 3.

Next, as shown in FIG. 2B, a direction perpendicular to the channel direction on the surface of the semiconductor substrate 1 (in FIG. 2,
The resist mask 13 opening on the portion serving as the source region 41 of each storage element M1 and the isolation oxide film 11 separating the portion serving as the source region 41 of each storage element M1 arranged in a direction perpendicular to the paper surface). Is formed on the semiconductor substrate 1.

Next, as shown in FIG. 2C, FG is performed by anisotropic etching using the resist mask 13.
6 and CG 8 were formed, and the isolation oxide film 11 was removed so that the portion serving as the source region 41 of each storage element M1 arranged in a direction perpendicular to the channel direction was connected, and the isolation oxide film 11 was covered. The surface of the semiconductor substrate 1 is exposed.

Hereinafter, this anisotropic etching is referred to as SAS (self-aligned source) etching. By this SAS etching, the first and second conductive films 6a and 8a are processed, and FG6 and CG8 are formed.

Subsequently, as shown in FIG. 2D, the exposed substrate 1 is moved to a depth L by using a resist mask 13.
s ₁ only excavated to form a groove 14, the resist mask 13
Are ion-implanted, for example, with phosphorus or arsenic at an angle with respect to the normal direction of the substrate 1 so that the source regions 4 of the storage elements M1 arranged in the direction perpendicular to the channel direction
1 and impurity regions 12 electrically connecting them to each other
1 are formed at the bottom and side edges of the groove 14. As a result, the source region 41 is covered with the surface of the semiconductor substrate 1 covered with the isolation oxide film 11 and the impurity region 1 formed in the vicinity thereof.
21, the source region 41 and the impurity region 1 are connected.
21 are formed. After the ion implantation, the resist mask 13 is removed.

Thereafter, an interlayer insulating film 9 made of, for example, BPSG or TEOS is deposited on the entire surface of the semiconductor substrate 1 by using the CVD method, and an anisotropic etching technique (etch back) is performed.
Or CMP (Chemical mechanical)
The surface is flattened using a polishing technique, and then a connection hole is formed in the connection surface 3a on the surface of the drain region 3 by a photoengraving technique. Further, a conductive layer is formed on the entire surface of the semiconductor substrate 1 and is patterned into a desired shape to form the sub-bit line 10, and
By applying an appropriate heat treatment, a nonvolatile semiconductor memory device having the structure shown in FIG. 1 is obtained.

In the first embodiment, since the source region 41 is extended by the groove 14 as described above, the width of the source line SL1 is increased accordingly, and the number of sheets per unit cell is reduced. As a result, the resistance of the source line SL1 can be reduced. Specifically, as shown in the first embodiment, in the case of providing the groove 14 of the depth Ls _1, when the Lw the length in the direction perpendicular to the channel direction of the cells, number of sheets in the conventional Is Lw / Ls, but in the present embodiment, it is reduced to Lw / (Ls + 2 × Ls ₁ ).

Therefore, the ion implantation amount,
The resistance of the source line can be reduced without increasing the amount of stake of aluminum, so that the punch-through resistance can be maintained and improved, the chip area can be reduced, and the chip cost can be reduced accordingly. Thus, there is an effect that the reading operation can be stabilized.

In the above case, the storage element M1
Is an N-channel type, and FIGS. 2 (a) and 2 (d)
In the step shown by, boron or BF ₂ may be ion-implanted instead of phosphorus, arsenic, or the like. In this case, the N (and P) type region shown in FIG. The source and drain regions and the well can be formed in the shape changed to the mold, and therefore, the same effect as described above can be obtained.

Embodiment 2 Embodiment 2 of the present invention
Is different from the first embodiment in that, of the source region extended by the groove, the portion formed at the bottom of the groove has a higher impurity concentration than the portion formed at the side edge of the groove. The only difference is that the second embodiment is the same as the first embodiment.

FIG. 3 is a fragmentary cross-sectional view showing the structure of the nonvolatile semiconductor memory device according to the second embodiment of the present invention. The structure of this device is different from the structure of the nonvolatile semiconductor memory device shown in FIG. 1 of the first embodiment in that the source region 42 of each storage element M2 extended by the groove 14 includes:
The portion 42a formed at the bottom of the groove 14
An impurity region having a higher impurity concentration than the portion 42b formed on the side edge of the region and electrically connecting the source regions 42 (a region indicated by reference numeral 121 in FIG. 1).
Also, similarly to the source region 42, the portion formed at the bottom of the groove 14 has a higher impurity concentration than the portion formed at the side edge of the groove 14, and the source line ( (Wiring indicated by reference numeral SL1 in FIG. 1)
Are formed, and the other points are the same as the structure of the nonvolatile semiconductor memory device shown in FIG.

Next, a description will be given of a method of manufacturing the nonvolatile semiconductor memory device having the above-described configuration. Although the method for manufacturing the nonvolatile semiconductor memory device according to the second embodiment takes different steps from the steps shown in FIG. 2D in the first embodiment, other steps are the same as those shown in FIG. It includes the same steps as those of the manufacturing method according to the first embodiment.

Specifically, as shown in FIG. 4, a part 42b of the source region is formed at a depth from the surface of the substrate 1 such that it contributes to punch-through resistance so as to have the same impurity concentration as the conventional one. On the other hand, a part 4 of the source region having a high impurity concentration is formed at a position deep enough not to contribute to punch-through resistance, that is, at the bottom of the groove 14 dug to a sufficient depth.
2a is formed.

Here, as a method for setting different impurity concentrations between the side edge and the bottom of the groove 14, first, ion implantation having an angle with respect to the normal direction of the substrate 1 is performed, and then, By performing ion implantation in the normal direction, the concentration of the source region 42a at the bottom of the groove can be set to a desired concentration.

In the second embodiment, from the viewpoint of punch-through resistance, the impurity concentration of the source region has an upper limit and it is difficult to lower the resistance of the source line. Since the impurity concentration of the portion 42a of the source region formed at the bottom of the trench 14 dug to a sufficient depth is increased irrespective of the above, the resistance of the source line can be reduced as compared with the first embodiment. Further, it is possible to achieve the same effect as that of the first embodiment.

Embodiment 3 Embodiment 3 of the present invention
Is an impurity region formed on the main surface of the semiconductor substrate so as to surround the source region and having a conductivity type different from the conductivity type of the source region (hereinafter, “punch-through suppression region”). The only difference is that the present embodiment is provided. The other points are the same as in the first embodiment.

FIG. 5 is a cross-sectional view of a main part showing a structure of a nonvolatile semiconductor memory device according to Embodiment 3 of the present invention.
The structure of this device is different from the structure of the nonvolatile semiconductor memory device shown in FIG.
Only in that a P-type punch-through suppressing region 15 having a higher impurity concentration than the P-well 2 is formed so as to surround the periphery of each source region 41 of each storage element M3 on the main surface of the storage element M3. In other respects, the structure is the same as that of the nonvolatile semiconductor memory device shown in FIG.

Next, a description will be given of a method of manufacturing the nonvolatile semiconductor memory device having the above-described configuration. Although the method for manufacturing the nonvolatile semiconductor memory device according to the third embodiment takes different steps from the steps shown in FIG. 2D in the first embodiment, the other steps are the same as those in FIG. It includes the same steps as those of the manufacturing method according to the first embodiment.

Specifically, as shown in FIG. 6, after or immediately before ion implantation for forming the source region 41,
Under the implantation conditions (implantation energy, ion species, etc.) such that the range of the implanted ions to the semiconductor substrate 1 is larger than that of the ion implantation for forming the source region 41, the P well 2
The punch-through suppressing region 15 is formed by performing P-type ion implantation so as to have a higher impurity concentration.

In the third embodiment, the source region 4
Since the P-type punch-through suppressing region 15 having a higher impurity concentration than the P-well 2 is formed so as to surround the periphery of the P well 1, the extension of the depletion layer from the drain region 3 is reduced as compared with the first embodiment. Embodiment 1 can be suppressed.
It is possible to have the same effect as the effect in the above.

In the third embodiment, the punch-through suppressing region 15 is formed so as to surround the entire periphery of the source region 41, but only the portion 41b formed on the side edge of the source region is surrounded. As described above, the punch-through suppression region may be formed, and more specifically, a part 41 of the source region may be formed.
Only the part of b, which affects the punch-through resistance and is formed at a position shallow from the surface of the substrate 1, may be surrounded by the punch-through suppressing region. In this case, the same effect as described above is obtained. It will be.

Embodiment 4 Embodiment 4 of the present invention
The third embodiment is different from the third embodiment in that, in the same manner as in the second embodiment, the portion formed at the bottom of the groove in the source region extended by the groove is the portion formed at the side edge of the groove. The only difference is that the impurity concentration is higher than that of the third embodiment, and the other points are the same as those of the third embodiment.

FIG. 7 is a fragmentary cross-sectional view showing a structure of a nonvolatile semiconductor memory device according to Embodiment 4 of the present invention. The structure of this device is different from the structure of the nonvolatile semiconductor memory device shown in FIG. 5 of the third embodiment in that the source region 42 of each storage element M4 extended by the groove 14 includes:
The portion 42a formed at the bottom of the groove 14
An impurity region having a higher impurity concentration than the portion 42b formed on the side edge of the region and electrically connecting the source regions 42 (a region indicated by reference numeral 121 in FIG. 1).
Similarly to the source region 42, the only difference is that the portion formed at the bottom of the groove 14 has a higher impurity concentration than the portion formed at the side edge of the groove 14. Is similar to the structure of the nonvolatile semiconductor memory device shown in FIG.

Next, a description will be given of a method of manufacturing the nonvolatile semiconductor memory device thus configured. Although the method of manufacturing the nonvolatile semiconductor memory device according to the fourth embodiment takes different steps from the steps shown in FIG. 6 in the third embodiment, the other steps are the same as those in the third embodiment. It includes the same steps as the method.

More specifically, as shown in FIG. 8, a portion 42b of the source region is formed at a depth from the surface of the substrate 1 such that it contributes to punch-through resistance so as to have the same impurity concentration as the conventional one. On the other hand, a part 4 of the source region having a high impurity concentration is formed at a position deep enough not to contribute to punch-through resistance, that is, at the bottom of the groove 14 dug to a sufficient depth.
2a is formed.

Here, as a method of setting different impurity concentrations at the side edge and the bottom of the groove 14, first, ion implantation having an angle with respect to the normal direction of the substrate 1 is performed, and then, By performing ion implantation in the normal direction, the concentration of the source region 42a at the bottom of the groove can be set to a desired concentration.

In the fourth embodiment, from the viewpoint of punch-through resistance, the impurity concentration of the source region has an upper limit, and it is difficult to reduce the resistance of the source line. Since the impurity concentration of the portion 42a of the source region formed at the bottom of the trench 14 dug to a sufficient depth is increased irrespective of the above, the resistance of the source line can be reduced as compared with the third embodiment. And more
It is possible to suppress not only the extension of the depletion layer from the drain region 3 but also the extension of the depletion layer from the source region 42. In addition, the same effect as that of the third embodiment can be obtained. It becomes possible.

In the fourth embodiment, the punch-through suppressing region 15 is formed so as to surround the entire periphery of the source region 42, but only the portion 42b formed on the side edge of the source region is surrounded. As described above, the punch-through suppressing region may be formed, and more specifically, a part 42 of the source region may be formed.
Only the part of b, which affects the punch-through resistance and is formed at a position shallow from the surface of the substrate 1, may be surrounded by the punch-through suppressing region. In this case, the same effect as described above is obtained. I can do it.

Embodiment 5 Embodiment 5 of the present invention
Is embedded in the main surface of the semiconductor substrate so as to be partially exposed at the bottom of the groove, and electrically connects a plurality of source regions included in a plurality of storage elements to each other with respect to the first embodiment. The only difference is that a buried impurity layer formed in the channel direction of the same conductivity type as the source region is provided, and the other points are the same as in the first embodiment.

FIG. 9A is a main part plan view showing a structure of a memory cell array of a nonvolatile semiconductor memory device according to a fifth embodiment of the present invention, in which drain and source regions 3 and 43 of storage element M5 and word lines are shown. Line WL and source line SL2
In order to clarify the positional relationship with
Are omitted, the positional relationship of each region below the interlayer insulating film 9 is displayed, and in addition, the buried impurity layer 16 is also displayed. FIG. 9B is a sectional view taken along line AA of FIG. 9A.

As shown in FIG. 9, the structure of the nonvolatile semiconductor memory device according to the present embodiment is different from that of the first embodiment shown in FIG.
Is buried in the main surface of the semiconductor substrate 1 so that a part 16a is exposed at the bottom of the groove 14, and a part 43 of the source region formed at the bottom of the groove 14
a, comprising a buried impurity layer 16 formed in the channel direction, a plurality of source regions 43 arranged in a direction perpendicular to the channel direction, and a plurality of source regions 43 electrically connected to each other. The buried impurity layer 16 serves not only as a source line SL2 but also as a wiring formed perpendicularly to the channel direction, which is formed by the impurity region 122 formed on the side edge and bottom of the groove 14 to be connected. It just differs in what it does, and in other respects,
The structure is the same as that of the nonvolatile semiconductor memory device shown in FIG.

Specifically, as shown in FIG.
In the section taken along the line A, the groove 14 (depth D ₁ ) is formed deeper than the distance Lb ₁ from the surface of the semiconductor substrate 1 to the upper end of the buried impurity layer 16. The deepest part of the part 43 b of the formed source region is constituted by the buried impurity layer 16. Here, the depth at which the buried impurity layer 16 is formed (the distance Lb1 from the surface of the semiconductor substrate 1 to the upper end of the buried impurity layer 16) affects the punch-through resistance. It is deep enough not to be.

Next, a method of manufacturing the nonvolatile semiconductor memory device having the above-described structure will be described with reference to FIG. The method of manufacturing the nonvolatile semiconductor memory device according to the fifth embodiment takes different steps from the steps shown in FIGS. 2A and 2D in the first embodiment. It includes the same steps as those in the manufacturing method according to the first embodiment shown in FIG.

Specifically, as shown in FIG.
It differs from the process shown in FIG. 2A only in the following points. First, after a P-type well 2 is formed on one main surface of a semiconductor substrate, a resist mask having a wiring shape extending in the channel direction including a position where a source region 43 on the surface of the substrate 1 is formed in a subsequent step is formed. It is formed on a semiconductor substrate 1.

Next, using this mask, phosphorus or arsenic is implanted using an energy higher than that used for forming the drain region 3, and an N-type buried impurity layer 16 is formed at the upper end of the substrate. so as to be located at a depth Lb ₁ from 1 surface to form in the P-type well 2. In particular,
For example, in order to form the upper end portion of the buried impurity layer 16 so as to be located at a depth of 0.2 μm from the surface of the substrate 1, ion implantation may be performed using an implantation energy of about 360 keV.

Thereafter, the resist mask is removed.
The process after the removal of the mask includes the LOCOS separation film 11
And the subsequent steps are as described with reference to FIG.

As shown in FIG. 10B, FIG.
It differs from the process shown in (d) only in the following points. First, using the resist mask 13, the substrate 1 exposed in the step of FIG. 2C is excavated to a depth greater than the depth Lb ₁ , that is, a depth D ₁ to form a groove 14. 1
While leaving 3, ion implantation of phosphorus or arsenic having an angle with respect to the normal direction of the substrate 1 is performed, and the side edge of the groove 14 has substantially the same impurity concentration as the buried impurity layer 16.
The source regions 43 of the respective storage elements M5 arranged in the direction perpendicular to the channel direction are formed, and the impurity regions 122 electrically connecting them are formed at the bottom and side edges of the trench. As a result, the source line SL is formed by the source region 43 and the impurity region 122 formed on the surface of the semiconductor substrate 1 covered with the isolation oxide film 11 and in the vicinity thereof.
2 is formed. After that, that is, the removal of the resist mask 13 is as described in FIG.

In the fifth embodiment, part of buried impurity layer 16 forms part 43a of the source region, and buried impurity layer 16 is formed of a plurality of storage elements M5 arranged in the channel direction. Plays a role as a source line SL2 for electrically connecting the source regions 43 included in the source lines 43. Therefore, the resistance of the source line SL2 can be reduced by the area of the buried impurity layer 16 as compared with the first embodiment. It is possible to achieve the same effect as that of the first embodiment.

In the fifth embodiment, buried impurity layer 16 (source region 43a formed at the bottom of trench 14)
And the impurity concentration of the source region 43b formed on the side edge of the groove 14 is substantially equal to the impurity concentration of the buried impurity layer 16 irrespective of punch-through resistance, as in the second embodiment. The concentration may be higher. In this case, the resistance of the source line can be further reduced.

Further, similarly to the third embodiment, a punch-through suppressing region of a conductivity type different from that of source region 43 may be formed so as to surround the periphery of source region 43b formed on the side edge of groove 14. And, more specifically, a portion 43 of the source region.
Only the part of b that is formed at a position shallow from the surface of the substrate 1 and affects the punch-through resistance may be surrounded by the punch-through suppression region. In this case, the punch-through resistance is further improved. be able to.

As in the fourth embodiment, after the impurity concentration of the buried impurity layer 16 is further increased, the punch-through is suppressed so as to surround the periphery of the source region 43b formed on the side edge of the groove 14. A region may be formed.

Embodiment 6 FIG. Embodiment 6 of the present invention
Is different from the first embodiment in that a part of the source region and the impurity region formed at the bottom of the trench is perpendicular to the channel direction of the same conductivity type as the source region, buried in the main surface of the semiconductor substrate. Only the difference is that the buried impurity layer is formed in the first embodiment, and the other points are the same as in the first embodiment.

FIG. 11A is a main part plan view showing the structure of the memory cell array of the nonvolatile semiconductor memory device according to the sixth embodiment of the present invention. The drain and source regions 3, 44 of the memory element M6 and the word are shown. Line WL and source line SL
In order to clarify the positional relationship with the sub bit line 1,
0 is omitted, the positional relationship between the respective regions under the interlayer insulating film 9 is displayed, and in addition, the buried impurity layer 17 is also displayed. Further, FIG. 11B is a diagram showing A-
FIG. 3 is a sectional view taken along line A.

As shown in FIG. 11, the structure of the nonvolatile semiconductor memory device according to the present embodiment is different from the structure of the device shown in FIG. And an N-type buried impurity layer 17 formed along the groove 14 perpendicularly to the channel direction, and the buried impurity layer 17 is exposed at the bottom of the groove 14 to form the source line SL.
3 and a source region 4 of each of the plurality of storage elements M6 arranged vertically in the channel direction.
4 is electrically connected, and the other points are the same as the structure of the nonvolatile semiconductor memory device shown in FIG.

Specifically, as shown in FIG.
In the cross section taken along the line AA, the groove 14 (depth D ₂ ) is formed deeper than the distance Lb ₂ from the surface of the semiconductor substrate 1 to the upper end of the buried impurity layer 17. The deepest part of the part 44b of the source region formed at the bottom is formed by the buried impurity layer 17. Further, a part 44 a of the source region formed at the bottom of the groove 14 is also constituted by the buried impurity layer 17.

The depth at which the buried impurity layer 17 is formed (the distance Lb ₂ from the surface of the semiconductor substrate 1 to the upper end of the buried impurity layer 17) affects the punch-through resistance. Is deep enough that it does not affect

Next, a method of manufacturing the nonvolatile semiconductor memory device thus configured will be described with reference to FIG. The manufacturing method of the nonvolatile semiconductor memory device according to the sixth embodiment takes different steps from the steps shown in FIGS. 2A and 2D in the first embodiment, but the other steps are as follows. It includes the same steps as those in the manufacturing method according to the first embodiment shown in FIG.

More specifically, as shown in FIG.
It differs from the process shown in FIG. 2A only in the following points. First, after a P-type well 2 is formed on one principal surface of a semiconductor substrate, a resist mask 18 having an opening in a wiring shape extending perpendicularly to a channel direction is formed at a position along a groove 14 to be formed in a subsequent step. 1.

Next, using this mask 18, phosphorus or arsenic is implanted using an energy higher than the implantation energy used in forming the drain region 3, and the N-type buried impurity layer 17 is formed at the upper end. It is formed in the P-type well 2 so as to be located at a depth Lb ₂ from the surface of the substrate 1. Specifically, for example, in order to form the upper end portion of the buried impurity layer 17 so as to be located at a depth of 0.2 μm from the surface of the substrate 1, ion implantation is performed using an implantation energy of about 360 keV. Good.

After that, the resist mask 18 is removed. The process after the removal of the mask 18, that is, the process of forming the LOCOS isolation film 11 and the subsequent processes are shown in FIG.
It is as explained in.

Further, as shown in FIG.
It differs from the process shown in (d) only in the following points. First, using the resist mask 13, the substrate 1 exposed in the step of FIG. 2C is excavated to a depth greater than the depth Lb ₂ , that is, a depth D ₂ to form a groove 14. 1
3 is ion-implanted with phosphorus or arsenic at an angle with respect to the normal direction of the substrate 1 to have an impurity concentration substantially equal to that of the buried impurity layer 17 on the side edge of the groove 14.
The source regions 44 of the respective storage elements M6 arranged in a direction perpendicular to the channel direction are formed. As a result, first, FIG.
Embedded impurity region 17 formed in the process indicated by
And the impurity region including the source region 44 formed on the side edge of the groove in this step forms the source line SL3. After that, that is, the removal of the resist mask 13 is as described in FIG.

In the sixth embodiment, a part of the buried impurity layer 17 forms a part 44a of the source region, and the buried impurity layer 17 is formed of a plurality of memory cells arranged vertically in the channel direction. Source region 44 of each element M6
As a source line SL3 for electrically connecting the source line SL3 to the source line SL3, the resistance of the source line SL3 can be reduced by the area of the buried impurity layer 17 as compared with the first embodiment.
Moreover, it is possible to have the same effect as the effect in the first embodiment.

In the sixth embodiment, buried impurity layer 17 (source region 44a formed at the bottom of trench 14)
And the impurity concentration of the source region 44b formed on the side edge of the groove 14 is substantially equal to the impurity concentration of the buried impurity layer 17 irrespective of punch-through resistance, as in the second embodiment. The concentration may be higher. In this case, the resistance of the source line can be further reduced.

Similarly to the third embodiment, a punch-through suppressing region of a conductivity type different from that of source region 44 may be formed so as to surround source region 44b formed on the side edge of groove 14. And, more specifically, a portion 44 of the source region.
Only the part of b that is formed at a position shallow from the surface of the substrate 1 and affects the punch-through resistance may be surrounded by the punch-through suppression region. In this case, the punch-through resistance is further improved. be able to.

Further, similarly to the fourth embodiment, after the impurity concentration of the buried impurity layer 17 is further increased, the punch-through is suppressed so as to surround the source region 44b formed on the side edge of the groove 14. A region may be formed.

[0095]

According to the present invention, there is provided a nonvolatile semiconductor memory device comprising: a first conductive layer formed on one main surface of a semiconductor substrate via a first insulating film; and a first conductive layer formed on the first conductive layer. A second conductive layer formed with the second insulating film interposed therebetween, a first conductive type source formed opposite the main surface of the semiconductor substrate below the first conductive layer, and A plurality of storage elements each having a drain region, a groove formed on the main surface of the semiconductor substrate, and extending each of the plurality of source regions of the plurality of storage elements; And a first conductivity type impurity region formed on the main surface and electrically connecting the plurality of source regions of the plurality of storage elements to each other. Without increasing the amount, Resistance between the memory regions can be realized, so that the punch-through resistance can be maintained and improved, the chip area can be reduced, and the chip cost can be reduced accordingly, and the read operation can be stabilized. Becomes possible.

A first conductivity type buried buried in the main surface of the semiconductor substrate so as to be partially exposed at the bottom of the groove and electrically connecting a plurality of source regions of a plurality of storage elements to each other. Since the semiconductor device includes the impurity layer, the resistance between the source regions can be further reduced by the electrical connection using the buried impurity layer.

In the source region extended by the groove,
The portion formed at the bottom of the groove has a higher impurity concentration than the portion formed at the side edge of the groove. The resistance can be reduced, and the punch-through resistance can be improved by the portion formed on the side edge of the groove.

A punch-through suppressing region of a conductivity type different from the first conductivity type is formed on the main surface of the semiconductor substrate and surrounds a portion formed on a side edge of the groove of the source region extended by the groove. As a result, the punch-through resistance can be further improved.

A method of manufacturing a nonvolatile semiconductor memory device according to the present invention is characterized in that a gate electrode formed on one main surface of a semiconductor substrate and a main electrode of the semiconductor substrate are opposed under the gate electrode. In a method for manufacturing a nonvolatile semiconductor memory device including a storage element having source and drain regions formed and a groove formed on a main surface of the semiconductor substrate and extending the source region, the main surface of the semiconductor substrate is provided. Forming a conductive layer serving as the gate electrode thereon, and performing anisotropic etching on the conductive layer using a mask having an opening over a portion serving as the source region of the semiconductor substrate; Exposing, exposing the exposed semiconductor substrate by anisotropic etching using the mask to form the groove, and ion using the mask. The input, since a step of forming the was the source region, the non-volatile semiconductor memory device manufactured using this method as compared to conventional ion implantation amount,
The resistance between the above source regions can be reduced without increasing the amount of piled aluminum, so that the punch-through resistance can be maintained and improved, the chip area can be reduced, and the chip cost can be reduced accordingly. In addition, the read operation can be stabilized.

[Brief description of the drawings]

FIGS. 1A and 1B are a main part plan view and a cross-sectional view illustrating a structure of a memory cell array of a nonvolatile semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a fragmentary cross-sectional view showing a method of manufacturing the nonvolatile semiconductor memory device according to Embodiment 1 of the present invention in the order of steps.

FIG. 3 is a fragmentary cross-sectional view showing a structure of a nonvolatile semiconductor memory device according to Embodiment 2 of the present invention;

FIG. 4 is a fragmentary cross-sectional view showing one step of a method for manufacturing a nonvolatile semiconductor memory device in Embodiment 2 of the present invention.

FIG. 5 is a fragmentary cross-sectional view showing a structure of a nonvolatile semiconductor memory device according to Embodiment 3 of the present invention;

FIG. 6 is a fragmentary cross-sectional view showing one step of a method for manufacturing a nonvolatile semiconductor memory device in Embodiment 3 of the present invention.

FIG. 7 is a fragmentary cross-sectional view showing a structure of a nonvolatile semiconductor memory device according to Embodiment 4 of the present invention;

FIG. 8 is an essential part cross sectional view showing one step of a method for manufacturing a nonvolatile semiconductor memory device in Embodiment 4 of the present invention.

FIG. 9 is a plan view and a cross-sectional view of main parts showing a structure of a memory cell array of a nonvolatile semiconductor memory device according to a fifth embodiment of the present invention.

FIG. 10 is a fragmentary cross-sectional view showing each step of the method for manufacturing the nonvolatile semiconductor memory device in Embodiment 5 of the present invention.

FIGS. 11A and 11B are a main part plan view and a sectional view showing a structure of a memory cell array of a nonvolatile semiconductor memory device according to a sixth embodiment of the present invention. FIGS.

FIG. 12 is a fragmentary cross-sectional view showing each step of the method for manufacturing the nonvolatile semiconductor memory device in Embodiment 6 of the present invention.

FIG. 13 is a schematic circuit diagram showing a memory cell array in an arbitrary block of a conventional DINOR type flash memory.

FIG. 14 is a plan view of a principal part showing a structure of a memory cell array of a conventional DINOR type flash memory.

FIG. 15 is a cross-sectional view of a main part showing a structure of a memory cell array of a conventional DINOR type flash memory.

FIG. 16 is a fragmentary cross-sectional view showing a method for manufacturing a conventional DINOR type flash memory in the order of steps;

FIG. 17 is an equivalent circuit of a conventional DINOR type flash memory at the time of reading using a single-ended sense amplifier.

[Explanation of symbols]

1 semiconductor substrate, 3 drain region,
Reference Signs List 5 first insulating film, 6 first conductive layer, 6a conductive layer serving as gate electrode, 7 second insulating film, 8 second conductive layer, 8a conductive layer serving as gate electrode, 13 mask, 14 groove, 15 punch-through suppression region, 16, 17 buried impurity layer, 41, 42, 4
3, 44 source region, 41a, 42a, 43a, 44
a portion formed at the bottom of the groove in the source region, 41b, 4
2b, 43b, 44b portions formed on the side edges of the groove of the source region, 121, 122 impurity regions electrically connecting the source regions to each other;

Claims (7)

[Claims] 1. A first conductive layer formed on one main surface of a semiconductor substrate via a first insulating film, and a first conductive layer formed on the first conductive layer via a second insulating film. 2 conductive layers, and
A plurality of storage elements, each having a first conductivity type source and drain region, formed on the main surface of the semiconductor substrate so as to face below the first conductive layer; and a main surface of the semiconductor substrate. And a groove extending on each of the plurality of source regions of the plurality of storage elements, and a plurality of source regions formed on the main surface of the semiconductor substrate along the grooves and provided on the plurality of storage elements. A nonvolatile semiconductor memory device comprising: a first conductivity type impurity region electrically connected to each other. 2. A buried first conductivity type buried in a main surface of a semiconductor substrate so as to be partially exposed at the bottom of the groove, and electrically connecting a plurality of source regions of a plurality of storage elements to each other. 2. The nonvolatile semiconductor memory device according to claim 1, further comprising an impurity layer. 3. The nonvolatile semiconductor memory device according to claim 2, wherein said impurity region is a buried impurity layer. 4. The nonvolatile semiconductor memory device according to claim 2, wherein said buried impurity layer is formed in a channel direction. 5. The source region extended by the groove, wherein a portion formed at the bottom of the groove has a higher impurity concentration than a portion formed at a side edge of the groove. The nonvolatile semiconductor memory device according to any one of claims 1 to 4. 6. A punch-through suppressing region of a conductivity type different from the first conductivity type, surrounding a portion formed on a main surface of a semiconductor substrate and formed on a side edge of the groove in a source region extended by the groove. The nonvolatile semiconductor memory device according to claim 1, further comprising: 7. A storage element having a gate electrode formed on one main surface of a semiconductor substrate, and a source and drain region formed so as to oppose the main surface of the semiconductor substrate below the gate electrode. A method of manufacturing a nonvolatile semiconductor memory device having a groove formed on a main surface of the semiconductor substrate and extending the source region, wherein a conductive layer serving as the gate electrode is formed on the main surface of the semiconductor substrate. Performing anisotropic etching of the conductive layer using a mask that is opened over the source region of the semiconductor substrate to expose the semiconductor substrate; Forming a trench by excavating the exposed semiconductor substrate by anisotropic etching; and forming the source region by ion implantation using the mask. Method of manufacturing a nonvolatile semiconductor memory device.