JPH10223560A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress a thin-line effect due to a silicide process and to eliminate bridging by selectively forming a metal silicide film on polysilicon, amorphous silicon, or a silicon substrate when forming a metal thin film on the entire surface of a sample by using the chemical vapor deposition method. SOLUTION: LOCOS 2 is formed on an Si substrate 1, a gate oxide film 3 is formed, a polysilicon(PSi) film is deposited, a PSi film and the gate oxide film 3 are collectively etched, and a PSi gate 4 and the gate oxide film 3 are machined to a desired gate pattern. Further, the entire surface of a deposited oxide film is subjected to etchback, thus forming a side wall spacer 5. Then, an impurity ion is implanted and an activation annealing is performed and a diffusion layer 6 is also formed. Then, when a Ti film 7 is formed on the entire surface of a sample by the plasma CVD method, a raw material source for forming the Ti film 7 reacts with silicon, thus selectively forming TiSi2 films 8 and 9 on the diffusion layer 6 and the PSi gate 4.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for forming a metal silicide film using a chemical vapor deposition (CVD) method for a semiconductor device, and a method for manufacturing a semiconductor device using the same.

[0002]

2. Description of the Related Art In a conventional semiconductor device having a salicide structure, a metal thin film is formed by a sputtering method, and a metal silicide film is formed by utilizing a thermal reaction between the metal thin film and silicon. The metal salicide process is
After forming the metal thin film, the first annealing is performed to form a metal silicide film only on the interface between the metal thin film and silicon, and then the unreacted metal thin film on the oxide film is removed by wet etching, and then the second annealing is performed. To form a structurally stable low-resistance metal silicide film. The metal silicide film according to the above-mentioned conventional method has a problem in that a thin line effect such that the gate resistance sharply increases as the gate width is reduced appears.

[0003] For example, "Oguro et al., Analysis of Resistance Anomaly in Thinning of Ti and Ni Silicide, Proceedings of the 41st Joint Lecture on Applied Physics, 29p-ZG-13 (19
94)), the grain size of Ti silicide is 0.1μ.
m and there is a different layer at the grain boundary. Therefore, it is stated that when the gate width becomes as small as this grain size, a layer existing on the grain boundary crosses the gate, and the layer brings about a thin line effect. This is because a Ti film is formed by a sputtering method and then a Ti silicide film is formed by a normal salicide process. It is considered that the Ti silicide film was formed at the crystal grain boundaries during the crystal growth.

In addition, Ouchi et al., TiSi on a fine wire diffusion layer
₂ , phase transition, 41th Applied Physics Alliance Lecture Meeting Preliminary Report, 30a-ZH-3 (1994) ", the effect of stress at the wiring edge is reduced as the line width of Ti silicide becomes narrower. It is reported that the temperature increases and the phase transition temperature from the C49 structure to the C54 structure increases, and it is intended that the relaxation of the stress at the end of the wiring leads to the suppression of the fine wire effect.

[0005] Further, "Inoue et al., Study of Salicide Process Using W / Ti Stacked Structure, Proceedings of the 41st Lecture Meeting on Applied Physics, 30a-ZH-8 (199)
In 4), after forming a W / Ti laminated film, the first annealing for silicidation is performed in an N ₂ atmosphere. It is reported that the W film on the Ti film functions as a barrier layer at the time of the first annealing, and a thin silicide film can be formed, thereby suppressing the fine wire effect. However, since this method uses a W / Ti laminated structure, it is difficult to control the annealing temperature.
There is a high possibility that a ternary silicide film of W, Ti, and Si is formed and the surface morphology is significantly deteriorated.

Also, "Ishigami et al., Study of Ti Salicide Process Using Reduced Pressure N ₂ RTA, Proceedings of the 42nd Joint Lecture on Applied Physics, 28p-K-13 (199)
5) reports that silicide is formed to a smaller line width when the Ti film thickness is smaller, so that it is necessary to reduce the thickness of Ti to suppress the increase in the layer resistance. However, since this method the Ti film thickness is small, Ti during N ₂ first annealing
There is a problem that it is difficult to control the nitridation reaction of Ti and the silicide reaction of Ti.

[0007]

[Problems to be Solved by the Invention] Proceedings of the 41st Joint Lecture Meeting on Applied Physics 1994, 29p-ZG-13
The layer existing in the grain boundary described in the above section is a normal T
i salicide process (Ti film formation, first annealing, T
It is considered that the impurities mixed during the removal of the iN and the unreacted Ti film and the second annealing were precipitated at the crystal grain boundaries of Ti silicide.

In the method according to the present invention, a Ti silicide film is formed simultaneously with the formation of the CVD-Ti film, thereby preventing the above-mentioned impurities from being mixed. In addition, the thin wire effect due to the impurities is suppressed.

[0009] In addition, in the proceedings of the 41st Joint Lecture Meeting on Applied Physics 1994, 30a-ZH-3, Ti
As the line width of the silicide becomes narrower, the influence of the stress at the end of the wiring becomes larger, which indicates that the influence is exerted on the thin line effect. This is also the same as above.
After forming the film by the sputtering method, since the Ti silicide film is formed by the normal Ti salicide process,
It is difficult to alleviate the stress in the thin wire portion.

In the method according to the present invention, a Ti silicide film is formed little by little at the time of forming a CVD-Ti film to avoid local stress concentration at the end of the fine wire.

[0011] In the above-mentioned proceedings of the forty-first edition of the 41st Lecture Meeting on Related Physics in 1994, 30a-ZH-8, Ti
A thicker silicide film, on the other hand,
Proceedings of the JSCE Lecture Meeting 28p-K-1
Reference 3 indicates that a thinner film of Ti silicide is more effective in suppressing the thin line effect. Although the two are contradictory results, it is conceivable that such a result can be obtained depending on the difference in the film quality of Ti, the annealing conditions for silicidation, or the state of the underlying Si. In any case, it is certain that the film thickness of Ti silicide has a great effect on the fine wire effect.

The method according to the present invention makes it possible to easily control the thickness of Ti silicide, and suppresses the thin line effect by optimizing the thickness of Ti silicide.

That is, an object of the present invention is to suppress the thin line effect in the salicide process. Another object of the present invention is to eliminate bridging in the salicide process and to establish a salicide process with high reliability. It is a further object of the present invention to reduce the number of steps as compared with a normal salicide process and to reduce impurities mixed in the process.

[0014]

The above object is achieved by the following constitution.

(1) In a method of manufacturing a semiconductor device, when a metal thin film is formed on the entire surface of a sample using a chemical vapor deposition (CVD) method, a metal silicide is formed only on a polysilicon, amorphous silicon, or Si substrate. A method for manufacturing a semiconductor device, wherein a film is selectively formed.

(2) In a semiconductor device, chemical vapor deposition (CV)
A semiconductor device having a metal silicide film selectively formed on a gate electrode and a source / drain when a metal thin film is formed on the entire surface of a sample by using the method D).

(3) In the method of manufacturing a semiconductor device, the gate electrode is made of polysilicon, or the uppermost layer of the polycide structure is made of polysilicon or amorphous silicon.
A method for manufacturing a semiconductor device, comprising: forming a metal thin film on the entire surface of a sample by a CVD method; and forming a metal silicide film only on an interface between the gate electrode and the metal thin film.

(4) In the method of manufacturing a semiconductor device, the source
A method for manufacturing a semiconductor device, comprising: forming a metal thin film by CVD on an entire surface of a sample on a diffusion layer comprising a drain; and forming a metal silicide film only at an interface between the diffusion layer and the metal thin film.

(5) In the method of manufacturing a semiconductor device, when a metal thin film is formed on the entire surface of a sample by a CVD method, a gate electrode in which the uppermost layer of polysilicon or polycide structure is made of polysilicon or amorphous silicon and the metal thin film A metal silicide film at the same time at the interface between the metal thin film and the interface between the metal thin film and the diffusion layer comprising the source / drain and the metal thin film.

(6) In the method of manufacturing a semiconductor device, the source
Forming a diffusion layer consisting of a drain, forming a gate electrode in which the uppermost layer in the polysilicon or polycide structure is polysilicon or amorphous silicon, and forming a metal thin film by a CVD method. And forming a metal thin film at the interface between the diffusion layer and the metal thin film and at the interface between the gate electrode and the metal thin film when forming the metal thin film by the CVD method.

(7) In the semiconductor device and the method of manufacturing a semiconductor device according to the above (2), (3), (5), and (6), a thin line effect generated when the gate electrode width is 0.5 μm or less is suppressed. .

[0022]

DETAILED DESCRIPTION OF THE INVENTION The present invention is directed to chemical vapor deposition (CVD).
When a metal film is deposited on the entire surface of a sample by a method, a metal silicide film selectively formed on silicon is used. The principle will be described with reference to FIG.

A LOCOS 2 is formed on a Si substrate 1, and a gate oxide film 3 is formed by thermal oxidation. Next, after depositing a polysilicon film, the polysilicon film and the gate oxide film 3 are collectively etched using the resist as a mask, and the polysilicon gate 4 and the gate oxide film 3 are processed into a desired gate pattern. Further, an oxide film is deposited by using the CVD method, and the entire surface of the oxide film is etched back to form the sidewall spacer 5. Next, a diffusion layer 6 is formed by performing impurity ion implantation and activation annealing (FIG. 1A). Incidentally, the polysilicon gate 4 may be a single layer film, or in the case of a laminated film, the uppermost layer may be a polysilicon film or an amorphous silicon film.

A CVD-Ti film 7 is formed on the entire surface of the sample by using a plasma CVD method. At this time, CVD
-The source material for forming the Ti film 7 reacts with silicon, so that T is formed on the diffusion layer 6 and the polysilicon gate 4 respectively.
iSi ₂ films 8 and 9 are selectively formed (FIG. 1)
(B)). Since this utilizes a reaction between an inorganic source containing Ti as a main component and silicon, TiSi is formed on oxide films such as LOCOS2 and sidewall spacers 5.
_{No two} films are formed. The conditions for forming the CVD-Ti film 7 are as follows: the substrate temperature is kept constant at 600 ° C .;
After forming a film with Cl ₄ at 10 sccm, H ₂ at 50 sccm and the pressure in the reaction tank at 0.05 Torr, a TiN film was formed by further adding ammonia gas.

Next, after removing the CVD-Ti film 7 by wet etching with a mixed solution of aqueous hydrogen peroxide and aqueous ammonia, RTA (Rapid Ther) at a temperature of 800 ° C. for 1 minute.
mal Annealing) treatment to make the TiSi ₂ film a low-resistance stable film (FIG. 1 (c)). The wet etching of the CVD-Ti film 7 may be performed after the RTA process.

Conventionally, TiSi ₂ has been produced by a silicidation reaction.
In the case of forming a film, a sputtered Ti film 11 is formed on the entire surface of the sample of FIG. 2A by using a sputtering method (FIG. 2B). Next, as the first annealing, 600
The heat treatment was performed within a temperature range of 750 ° C. to 750 ° C. for 30 seconds to 30 minutes. On the diffusion layer 6 and the polysilicon gate 4
The upper sputtered Ti film 11 becomes TiSi
_x films 12 and 13 are formed (X ≦ 2). At the same time, the sputtered Ti film 11 siphons the Si atoms of the diffusion layer 6 to form TiSi _x on the sidewall spacers 5.
The bridge 14 is formed (FIG. 3A). Short circuits frequently occurred between the polysilicon gate 4 and the diffusion layer 6 due to the TiSi _x bridge 14 on the sidewall spacer 5.

Next, after removing the sputtered Ti film 11 by wet etching, the second annealing is performed at 800 ° C. to 8 ° C.
By performing heat treatment in a temperature range of 50 ° C., TiSi
_{The x} films 12 and 13 are stable TiSi ₂ films 15 and 16 respectively.
(FIG. 3B). However, the TiSi ₂ films 15, 16
It is extremely difficult to remove only the TiSi _x bridges 14 on the side wall spacers 5 while leaving the above, and the problem of short circuit has not been solved.

When the width of the gate electrode is d as shown in FIG. 4, the sheet resistance of the gate increases as the width d of the gate electrode decreases in the conventional salicide process. In particular, when the gate width is as narrow as 0.5 μm or less, the rate of increase in the sheet resistance of the gate is extremely increased (FIG. 5). This is because the sputtered Ti film and the polysilicon gate 4
Forms a TiSi ₂ film by a silicide reaction,
This is because TiSi ₂ crystal growth is hindered in a region where the gate electrode width is small.

In the present invention, a silicide reaction occurs on the polysilicon gate 4 at the same time as the formation of the CVD-Ti film 7, so that the polysilicon layer 4 and the diffusion layer 6 shown in FIG. Short and 0.5 shown in FIG.
Extremely high sheet resistance at a narrow gate electrode width of less than μm can be suppressed.

Next, an embodiment of the present invention will be described with reference to FIG. First, an interlayer insulating film 21 is formed on the sample manufactured in FIG. 1C, and the interlayer insulating film 21 is dry-etched using a resist as a mask to form a desired contact hole 2.
After opening the holes 2, the resist is removed (FIG. 6A).
Next, a CVD-TiN film 23 was formed (FIG. 6B).
Further, a CVD-W film was formed as the first wiring layer 24, and the first wiring layer 24 and the CVD-TiN film 23 were collectively dry-etched using a resist as a mask to obtain a desired pattern (FIG. 6C). Thereby, the contact resistance between the diffusion layer 6 and the first wiring layer 24 could be reduced, and a low contact resistance could be obtained. Further, since the TiSi ₂ film 9 is formed on the polysilicon gate 4, the gate resistance can be reduced.

In addition, the sample of FIG.
The W plugs 31 and 32 can also be formed by using the D method (FIG. 7A). In this case, if the thickness of the W plug is set to the shallow via hole on the polysilicon gate 4, the contact hole on the diffusion layer 6 cannot be completely filled with the W plug. Is effective in ensuring the reliability of the wiring. Next, after forming the barrier metal 33 and the first wiring layer 34, the first wiring layer 34 and the barrier metal 33 are collectively dry-etched into a desired pattern using the resist as a mask (FIG. 7B). The barrier metal 33 at this time may be a TiN film formed by a sputtering method.
-It is desirable to use a TiN film.

Further, with respect to the sample of FIG.
When the W plugs 41 and 42 are formed using the VD method, if the thickness of the W plug is set to the deepest contact hole,
The W plug 42 abnormally grows in the via hole on the gate having a small depth (FIG. 8A). Such a W plug 42
Abnormal growth may cause a short circuit between wirings or between wiring layers, and therefore, it is necessary to remove the protruding portion of the W plug 42. Therefore, chemical mechanical polishing (CMP = Chemi
The projection of the W plug is removed using cal mechanical polishing (FIG. 8B). In addition, as a method of removing the protruding portion of the W plug, an etch-back method can be used other than the CMP. Next, a barrier metal 45 and a first wiring layer 46 are formed, and the first wiring layer 46 and the barrier metal 45 are collectively dry-etched using a resist as a mask to form a desired pattern (FIG. 8C).
As a result, a short circuit between wirings and between wiring layers is eliminated, and the sample can be flattened.

An embodiment of the present invention will be described with reference to FIG. An interlayer insulating film 21 is formed on the sample manufactured in FIG. 1C, and the interlayer insulating film 2 is formed using a resist as a mask.
1 is dry-etched to obtain a desired contact hole 5
After opening the holes 1 and 52, the resist is removed. At this time, when the dry etching selectivity of the TiSi ₂ films 8, 9 with respect to the interlayer insulating film 21 is small, the TiSi ₂ films 8, 9
(See FIG. 9A). When a normal wiring process is performed on this structure, it is considered that the contact resistance between the wiring metal film and the polysilicon gate 4 and the diffusion layer 6 extremely increases.

Therefore, for the structure shown in FIG.
By forming the CVD-Ti film 53, TiSi ₂
TiSi ₂ films 54 and 55 can be formed at the interface between the diffusion layer 6, the polysilicon gate 4, and the CVD-Ti film 53 through which the films 8 and 9 are exposed. Then, CVD-
After forming the TiN film and the first wiring layer 56, the first wiring layer 56, the CVD-TiN film and the CV
The D-Ti film 53 is collectively dry-etched into a desired pattern (FIG. 9B). Thereby, the first wiring layer 5
6 and the contact resistance between polysilicon gate 4 and diffusion layer 6 can be reduced.

Further, with respect to the structure shown in FIG.
A CVD-Ti film 53 is formed (FIG. 10A). At this time, the diffusion layer 6 through which the TiSi ₂ films 8 and 9 penetrate and are exposed.
At the interface between the polysilicon gate 4 and the CVD-Ti film 53, TiSi ₂ films 54 and 55 are selectively formed. Next, the CVD-Ti film 53 is removed with a mixed solution of aqueous hydrogen peroxide and aqueous ammonia (FIG. 10B).

Next, W plugs 61 and 62 are formed on the structure shown in FIG. 10B by using the selective CVD method.
In this case, as in FIG. 7, when the thickness of the W plug is set in the shallow via hole on the polysilicon gate 4, the contact hole on the diffusion layer 6 cannot be completely filled with the W plug. 6 leads to a substantial reduction in the aspect ratio of the contact hole, which is effective in ensuring the reliability of the wiring. Next, after forming the barrier metal 63 and the first wiring layer 64, the first wiring layer 64 and the barrier metal 63 are collectively dry-etched into a desired pattern using the resist as a mask (FIG. 11). In this case, as the barrier metal 63, a TiN film formed by a sputtering method can be used, but it is preferable to use a CVD-TiN film in consideration of film coverage.

In addition, with respect to the structure shown in FIG.
The W plugs 65 and 66 are formed using the same method as in FIG. The W plugs 65 and 66 are obtained by removing the protrusions of the W plug abnormally grown by chemical mechanical polishing (CMP) and flattening the sample. As a result, a short circuit between wirings and between wiring layers can be eliminated. Next, the barrier metal 67 and the first wiring layer 68 are formed, and the first wiring layer 68 and the barrier metal 67 are collectively dry-etched into a desired pattern using the resist as a mask (FIG. 12). The barrier metal 67 at this time is
Since the sample is flattened, Ti
There is no superiority in characteristics whether an N film or a CVD-TiN film is used.

Next, problems after the conventional metal salicide process will be described with reference to FIGS. Diffusion layer 6
A TiSi ₂ film 8 on the polysilicon gate 4 and
After forming 9, an interlayer insulating film 11 is formed, and the interlayer insulating film 11 is dry-etched using the resist as a mask to open contact holes 71 and 72, and then the resist is removed (FIG. 13A). At the time of dry etching of the interlayer insulating film 11, TiSi ₂
When the dry etching selectivity of the films 8 and 9 is small, FIG.
As shown in FIG. 3A, penetration of the TiSi ₂ films 8 and 9 occurs.

In order to further form a TiSi ₂ film on the diffusion layer 6 and the polysilicon gate 4 through which the TiSi ₂ films 8 and 9 have penetrated, conventionally, a Ti (sputter Ti) film must be formed by using a sputtering method. (Fig. 13
(B)). However, when the sputtered Ti film 73 is formed, as shown in FIG. 13B, there is a large difference in thickness between the Ti film at the bottom of the contact hole 71 having a small hole diameter and the Ti film at the bottom of the contact hole 72 having a large hole diameter. Will happen.

The sample shown in FIG. 13B is subjected to a heat treatment for silicidation to form TiSi ₂ films 74 and 75.
Is formed, the unreacted sputtered Ti film 73 is removed by wet etching (FIG. 14). The film thickness of the TiSi ₂ films 74 and 75 formed by such a method depends on the diameter of the contact hole, and the film thickness of the TiSi ₂ becomes smaller as the diameter of the contact hole decreases. Therefore, when the target thickness of the TiSi ₂ film 75 in the contact hole 72 having a large diameter is set to a target thickness, the thickness of the TiSi ₂ film 74 becomes extremely thin.
The contact resistance with the wiring metal film to be formed later cannot be reduced. On the other hand, the contact hole 71 having a small diameter
When the target film thickness of the TiSi ₂ film 74 at
The thickness of the _second film 75 is increased, and the TiSi ₂ film 75 penetrates through the diffusion layer 6 to cause an increase in the diffusion current of the diffusion layer. As described above, when the TiSi ₂ film is formed after the contact hole is formed by the conventional method, the probability of occurrence of a defect depending on the contact hole diameter increases.

Further, problems after the conventional metal salicide process will be described with reference to FIG. In the case where a wiring layer is formed for a sample in which the TiSi ₂ films 8 and 9 have a penetration as shown in FIG. 9A, it is necessary to form a barrier metal 83. Before the formation of the barrier metal 83, wet etching for removing the natural oxide film at the bottom of the contact holes 81 and 82 is required. The contact holes 81 and 8 are formed by this wet etching.
Side etching occurs in the TiSi ₂ films 8 and 9 exposed on the two side walls, and the bottoms of the contact holes 81 and 82 have an overhang shape. Even when the TiSi ₂ films 8 and 9 do not penetrate (FIG. 6A), the TiSi ₂ films 8 and 9 are similarly isotropically etched during the wet etching, and the bottoms of the contact holes 81 and 82 are similarly etched. It becomes overhang shape. When the barrier metal 83 is formed in the contact holes 81 and 82 whose bottoms have an overhanging shape, the barrier metal 83 and the diffusion layer 6 and the barrier metal 83 and the polysilicon gate 4 are formed.
In FIG. 15 (a), the disconnection appears remarkably.

A first wiring layer 84 is formed on a sample having a sectional shape as shown in FIG. 15A, and the first wiring layer 84 and the barrier metal 83 are collectively dry-etched into a desired pattern (FIG. 15). (B)). In this case, the barrier metal 83
And the first wiring layer 84 are formed by a sputtering method.
Insufficient coverage of the wiring layer at the bottoms of the contact holes 81 and 82 occurs, and it is difficult to avoid disconnection.

On the other hand, similarly, contact holes 81, 8
2 Even if an overhang occurs at the bottom, the overhang portion is formed by using the CVD-Ti film 91.
It can be embedded with the Ti film 91 (FIG. 16A).
Next, a CVD-TiN film and a first wiring layer 9 formed by a CVD method
2 is formed and etched into a desired pattern (FIG. 16)
(B)). As a result, the contact holes 81 and 82 can be completely filled with the metal film, and low contact resistance and high reliability can be achieved.

[0044]

According to the present invention, since the silicidation of Ti is performed simultaneously with the deposition of a CVD-Ti film, bridging that occurs between the source / drain and the gate, which is a problem in a normal Ti salicide process, is eliminated. Can be.

Further, in the ordinary Ti salicide process, a thin line effect such that the gate resistance sharply increases as the gate width becomes narrower occurs. However, according to the present invention, the stress in the thin line portion can be relaxed. In addition, since the thickness of Ti silicide can be easily controlled, the thin line effect can be suppressed.

Further, since a good wiring metal film coverage can be obtained in the fine contact hole portion, a highly reliable wiring can be formed.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating the principle of the present invention.

FIG. 2 is a cross-sectional view showing a conventional salicide process.

FIG. 3 is a sectional view showing a conventional salicide process.

FIG. 4 is a cross-sectional view showing a relationship between a conventional gate electrode width and sheet resistance.

FIG. 5 is an explanatory diagram showing a relationship between a conventional gate electrode width and sheet resistance.

FIG. 6 is a cross-sectional view showing a process step of one embodiment according to the present invention.

FIG. 7 is a sectional view showing a process step of a second embodiment according to the present invention.

FIG. 8 is a sectional view showing a process step of a third embodiment according to the present invention.

FIG. 9 is a sectional view showing a process step of a fourth embodiment according to the present invention.

FIG. 10 is a sectional view showing a process step of a fifth embodiment according to the present invention.

FIG. 11 is a sectional view showing a process step of a sixth embodiment according to the present invention.

FIG. 12 is a sectional view showing a process step of a seventh embodiment according to the present invention.

FIG. 13 is a sectional view showing a problem after a conventional metal salicide process.

FIG. 14 is a cross-sectional view showing a problem after a conventional metal salicide process.

FIG. 15 is a sectional view showing a problem after a conventional metal salicide process.

FIG. 16 is a cross-sectional view of one embodiment of the present invention for solving the problem after the conventional metal salicide process.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Si substrate, 2 ... LOCOS, 3 ... Gate oxide film, 4
... polysilicon gate, 5 ... sidewall spacer,
6 diffusion layer, 7 CVD-Ti film, 8, 9 TiSi ₂
film.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Natsuki Yokoyama 1-280 Higashi Koigakubo, Kokubunji-shi, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd. (72) Inventor Yoshiaki Yuyama 5-20-1, Josuihoncho, Kodaira-shi, Tokyo In-house Hitachi, Ltd. (72) Inventor Katsunori Obata 1-280 Higashi Koigakubo, Kokubunji-shi, Tokyo Inside Central Research Laboratory, Hitachi, Ltd.

Claims (7)

[Claims] In a method of manufacturing a semiconductor device, a metal silicide film is selectively formed only on a polysilicon, amorphous silicon, or Si substrate when a metal thin film is formed on the entire surface of a sample by using a chemical vapor deposition method. A method for manufacturing a semiconductor device. 2. In a semiconductor device, when a metal thin film is formed on the entire surface of a sample by using a chemical vapor deposition method, a metal thin film is formed on a gate electrode.
A semiconductor device having a metal silicide film selectively formed on a source / drain. 3. A method of manufacturing a semiconductor device, wherein a metal thin film is formed on the entire surface of a sample by a chemical vapor deposition method on a gate electrode whose gate electrode is made of polysilicon or a top layer of a polycide structure is made of polysilicon or amorphous silicon. Forming a metal silicide film only on the interface between the gate electrode and the metal thin film. 4. A method for manufacturing a semiconductor device, comprising the steps of:
A method for manufacturing a semiconductor device, comprising: forming a metal thin film on a whole surface of a sample by a chemical vapor deposition method on a diffusion layer comprising a drain; and forming a metal silicide film only on an interface between the diffusion layer and the metal thin film. 5. A method of manufacturing a semiconductor device, comprising: forming a metal thin film by chemical vapor deposition on the entire surface of a sample, wherein the uppermost layer of polysilicon or polycide structure is made of polysilicon or amorphous silicon; A method for manufacturing a semiconductor device, comprising: simultaneously forming a metal silicide film at an interface with a metal thin film and at an interface between a diffusion layer comprising a source and a drain and the metal thin film. 6. A method for manufacturing a semiconductor device, comprising:
Forming a diffusion layer consisting of a drain, forming a gate electrode in which the uppermost layer in the polysilicon or polycide structure is polysilicon or amorphous silicon, and forming a metal thin film by chemical vapor deposition. A semiconductor device having a metal thin film formed by a chemical vapor deposition method, wherein a metal silicide film is formed at an interface between the diffusion layer and the metal thin film and at an interface between the gate electrode and the metal thin film. Manufacturing method. 7. The semiconductor device according to claim 3, 5 or 6, wherein a thin line effect generated when the gate electrode width is 0.5 μm or less is suppressed.