JPH10222151A - Scanning type picture generation circuit means - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a scanning type picture generation circuit means being inexpensive and having high performance. SOLUTION: This device is constituted of plural pixel buffer units in which pixel information is stored in a pixel unit respectively, as a buffer means 16. Pixel information is successively stored in pixel unit and in each pixel buffer unit so that a scanning position is made end and buffer capacity is made the head from a scanning position. The pixel buffer unit is switched circulating with a pixel unit so that a pixel information storage position at the end coincides with a pixel information storage position at the head.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a scanning type image generating circuit. More specifically, game equipment, educational equipment, communication equipment, measuring equipment, inspection equipment, advertising equipment, karaoke equipment, word processors, video editing equipment, driving assistance equipment, printing auxiliary equipment, music auxiliary equipment, exercise assistance The present invention relates to circuit means for generating an image on a scanning display used in a device, a device for assisting a disabled person, and the like.

[0002]

2. Description of the Related Art The following means can be mentioned as this kind of conventionally known image generating circuit means.

[0003] The simplest configuration is a system without any buffer. In this method, data is read directly from the memory at the same timing as the display, so that the performance is naturally limited. This is used, for example, for character displays.

As a system having a buffer, there is a system having a line buffer (register) for dividing a horizontal line of an image. In this method, a drawing process is performed during a horizontal blanking period. This is used, for example, for generating a so-called Super Famicom (registered trademark) sprite. The line buffer system includes a single line buffer system and a double line buffer system.

[0005] The single line buffer method is
It has a buffer for one horizontal scanning line.
This method is used, for example, for displaying a sprite in a so-called Super Famicom (registered trademark) or the like, and performs drawing during a horizontal blanking period in order to stabilize display quality. However, the drawing period is only about 1/3 of the display period, and the drawing performance is poor.

On the other hand, the double line buffer system has a buffer for two horizontal lines of scanning lines. This method switches between drawing and display alternately in synchronization with horizontal scanning. It has a longer drawing time than the single line buffer method, so it has excellent drawing performance and should be used for high-performance sprite display. Can be. However, this method has a difficulty in requiring a memory capacity twice that of the single line buffer method. For example, it is employed as a sprite display for arcade game machines.

Alternatively, a single frame buffer system having a buffer for one screen is also known. This method is suitably used for full graphic (bit map) display, and enables drawing independent of a scanning method. However, a large capacity buffer memory is required, and writing is performed during the display period, so that there is a difficulty in lowering the quality of a displayed image. This method is mainly used for displaying a still image in a personal computer / workstation or the like.

[0008] In contrast to the single frame buffer system, a double frame buffer having a buffer for two screens and alternately switching between drawing and display in synchronization with a frame is provided.
Frame buffer schemes are also known. Although this method has a good moving image display quality and can take a long drawing period, it has a difficulty that a very large buffer memory capacity is required. This method is employed for displaying a full graphic moving image on a graphic workstation / 32-bit game machine, for example.

In conventional game machines (so-called NES, super NES (both are registered trademarks)) and the like, character pattern data (array of pixels) and attribute information (character format, palette, etc.) ) Were managed separately. Specifically, text is text memory,
The sprite stores an array of character numbers and an array of character attributes in the sprite memory, and the pattern data is specified in the position indicated by the character number, that is, indirectly specified, whereas the attribute data is the attribute array Was stored directly.

However, on the other hand, many pattern data are managed separately even though they are used in certain attributes. For this reason, the setting of pattern data and the setting of attribute data must be performed separately in the program, which is complicated in program production, and has the drawback that it is not good in terms of processing speed and memory efficiency. there were.

Also, the method of designating a character by a number has the advantage that valid characters can be arranged in all numbers, and when performing full graphics on a text screen using the character method, it is necessary to calculate the storage position of pixels. Although it has the feature of being easy, it has a difficulty that it can be applied only to characters of a common size.

[0012]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and an object thereof is to improve the memory use efficiency and reduce the buffer memory size while maintaining the drawing performance. It is another object of the present invention to provide a scanning image generating circuit having a simple structure.

Still another object of the present invention is to enable high-performance depth control, design without being restricted by the line size, and reduce the buffer memory size in a state of expressing transparency as a color. It is an object of the present invention to provide a scanning image generating circuit which can reduce the number of characters, and which can increase the efficiency (memory capacity and speed) when using characters.

According to a first aspect of the present invention, there is provided a scanning-type image generating circuit for generating an image having a two-dimensional pixel array, comprising a plurality of pixel buffers each storing pixel information in a pixel unit. The pixel information is sequentially stored in the pixel buffer units in units of pixels such that the scanning position is at the end and the buffer capacity from the scanning position is at the beginning, and the scanning position is the next pixel buffer unit. The pixel buffer unit is configured to circulate and switch the pixel buffer unit in pixel units so that the last pixel information storage position becomes the first pixel information storage position when the pixel buffer is moved. The gist is a scanning type image generation circuit means.

The pixel buffer means comprises a plurality of pixel buffers instead of a frame or line unit as in the prior art, and switches them by circulating them, in order to increase the time utilization efficiency of the buffer. It was made. By employing such a pixel buffer means, the buffer can be used effectively and the buffer size can be reduced. Further, since the buffer size can be set independently of the screen size, the buffer size can be freely selected, and the degree of freedom in design can be improved. Furthermore, it is convenient for design that the capacity of the buffer memory is a power of 2, and when the width of the screen is, for example, 320 pixels, the size of the buffer in the line buffer or the frame buffer must be set to this. However, in the case of the present invention, this is not the case, and the degree of freedom in design can be further improved.

A second aspect of the present invention is a scanning-type image generating circuit for generating an image composed of a two-dimensional pixel array. The scanning-type image generating circuit includes a clock generating means, and a horizontal image generating circuit based on a clock generated by the clock generating means. Scanning position generating means for generating a scanning position for performing vertical scanning while repeating one row of scanning; and a plurality of pixel buffers for storing pixel information in units of pixels. Pixel information in units of pixels so that the buffer capacity ahead of
The pixel buffer units are sequentially stored in buffer units, and the pixel buffer units are stored in pixel units so that the last pixel information storage position becomes the first pixel information storage position when the scanning position moves to the next pixel buffer unit. The pixel buffer unit is configured to include a depth buffer that stores a depth value related to the depth of the pixel and a code buffer that stores a code value that is information related to the color of the pixel. Pixel buffer means, and buffer output means for reading the code value at the scan position from the code buffer based on the scan position information from the scan position generation means, and then deleting the contents of the pixel buffer unit. The color of the display pixel based on the code value from the buffer output means Pallet means for converting and outputting information, an object generating means, decomposing the object from the object generating means into pixels, code values relating to the color of the pixels, depth values relating to the depth of the pixels, and positional information of the pixels A pixel generating means for outputting pixel information such as pixel information, and the pixel buffer means is accessed based on scanning position information from the scanning position generating means and pixel position information from the pixel generating means, and from the depth buffer. Pixel rendering means for comparing the depth value of the pixel generation means with the depth value from the pixel generation means, and updating the code value and the depth value of the pixel buffer means with the code value and the depth value from the pixel generation means based on the result. And an access request to the buffer means from the buffer output means and It is an gist scanning image generating circuit means, characterized in that a buffer access arbitration unit for arbitrating access requests to the buffer means from the pixel rendering means.

Here, the clock generating means is means for operating the system, and the scanning position generating means is a means for scanning an image and transmitting the information of the image to the scanning display device in order with the pixel output means. is there. Further, the pixel buffer means has a function of arranging randomly arranged objects and pixels in the order of scanning.
Pixel drawing means and pixel output means
It operates buffer means.

Conventional sprite (one of the objects)
The overlapping condition (priority) was determined in the order of the sprite memory array (so-called NES, Super
In the present invention, NES (both are registered trademarks) provides a depth information to sprites and texts, and adopts a method of controlling the overlap by a pixel buffer means based on this information. The depth buffer is provided here, and the depth buffer method conventionally used in the frame buffer is applied to the pixel buffer means.

Since the depth buffer is employed as described above, it is possible to precisely control the pixel overlap. Since the buffer means is configured in units of a plurality of pixel buffers, it is complicated to physically separate the drawing memory and the display memory. For this purpose, a method of switching between display access and drawing access is adopted. To achieve this, there are two requests: a display request from the buffer output means to the pixel buffer means and a drawing request from the pixel drawing means to the pixel buffer means. Arbitrating the buffer
Access arbitration means is provided.

As described above, by using the access arbitration means and realizing a plurality of buffers by time-sharing use of one memory, the configuration is simplified.

If the pallet means is brought before the pixel buffer means, transparent information can be obtained at the time of drawing. However, the pixel buffer means stores the color information converted by the pallet means. , The capacity increases.

In view of this, a mechanism is provided in which the pallet means is placed after the pixel buffer means, and the transparency can be judged before the pixel buffer means. This makes it possible to realize a transparent color while suppressing an increase in the capacity of the pixel buffer.

By employing the object generation means / pixel generation means (object / pixel conversion), there is an effect that an image can be represented by an object-level description. Furthermore, the use of the palette means has the effect of reducing the size of the hardware before the palette as compared with the case of directly operating with color information, and has the effect of changing the color tone of the image simply by rewriting the palette.

For the purpose of further reducing the buffer memory size and further improving the memory utilization efficiency, the buffer means which stores pixel information of a number smaller than the number of pixels constituting one horizontal row of the image is adopted. Is preferred. As described above, by storing pixel information of a number smaller than the number of pixels constituting one horizontal row of the image as the pixel buffer means, it is possible to obtain a high-quality image with a small buffer size. I can do it. Further, the processing of a portion where one object extends over two lines can be simplified, and the configuration can be simplified.

The buffer size depends on the ability to handle object density biases uniformly. If you want to increase the buffering capacity of the object density, you can increase the buffer size. Here, when a plurality of objects are concentrated in a local area, they overlap with each other and cancel each other out, so that they have little meaning as a picture. In short, objects have more local density limits than global density limits. This means that the buffer size does not need to be
It means that only a part is required. Therefore, a buffer having a small capacity (half a line or less) is sufficient.

The pixel information from the pixel generation means is based on the scanning position information from the scanning position generation means and the position information from the pixel generation means, and only the pixels overlapping the partial image corresponding to the pixel buffer means are obtained. It is preferable to include pixel limiting means for limiting and outputting to the pixel drawing means.

The pixel limiting means prevents pixels not appearing on the screen or pixels not secured in the pixel buffer means from being written to the pixel buffer means. The use of the pixel limiting means has an effect that a screen which can be arranged on the same buffer and whose right end and left end are continuous can be eliminated. It is also possible to supply and draw objects beyond the range of the pixel buffer means. Or,
Even if an object that exceeds the range of the pixel buffer is drawn, aliasing noise does not appear.

Further, it is judged from the scanning position information generated by the scanning position output means whether the object generated by the object generating means overlaps the partial image corresponding to the pixel buffer means, and only the overlapping object is output. It is preferable to include object limiting means.

The object limiting means is means for not supplying all objects from the beginning. That is, even if all objects can be supplied in order, not all of them can be drawn. At a certain moment,
The pixel buffer means is only part of the screen and many objects do not overlap with the pixel buffer means. That is, even if such an object is supplied, it is not written into the pixel buffer means but is simply discarded. Therefore, means for not supplying such an object from the beginning is effective. When the object limiting means is used, only valid objects are supplied at the subsequent stage, so that a limited drawing time can be effectively utilized, and there is an effect that many objects can be drawn on the screen.

The pixel buffer means is realized in three cycles of precharging, reading, comparing and writing by using the fact that reading and writing to the same address are paired. It is preferable to have a speed-up means. By adopting the access speed-up means, even if memories with the same access time are adopted, more drawing times can be secured.
There is an effect that drawing performance can be improved.

The need for the memory access speed-up means is that a buffer having a small capacity has a low ability to equalize the unevenness in the object density, but this is compensated for by increasing the access time of the buffer. This is also because the drawing performance depends on the access time of the buffer memory, so that the highest possible access speed is desired.

Here, since reading and writing to the same address occur in pairs in the buffer memory, the setting of the address and the preparation for data reading (precharge) can be made common by using this. Therefore, it took four cycles to perform precharge, read, precharge / comparison, and write in the past.
By completing the access for one pixel in a total of three cycles of comparison and writing, the access can be speeded up.

[0033] It is preferable that the object generating means comprises a text generating means, a sprite generating means, and an object selecting means for selecting these. By providing such means, there is an effect that objects of different formats can be realized by common hardware. Also, any object that can be decomposed into pixels can be supplied to the pixel buffer means.

A synchronizing signal generating means for generating a synchronizing signal based on the information from the scanning position generating means, and a video for synthesizing the color information from the pallet means and the synchronizing signal from the synchronizing signal generating means and converting it into a composite video signal It is preferable to include signal generation means. By outputting as a video signal, a home television receiver can be used as it is as a display means, and cost and space can be saved.
Also, since the video signal can be recorded by a video recorder, it can be used for a new purpose such as a video editing device (telopper).

A transparent information storage unit for storing a pallet address when a value written in the pallet unit by the control unit is transparent; and a pixel generated by the pixel generation unit. It is desirable to have a transparency control means for judging whether or not the code value is transparent by accessing the transparent information storage means based on the information, and transmitting only non-transparent pixel information to the pixel drawing means.

The reason for providing the transparent control means is as follows. Expressing a transparent color means that the color behind can be seen through. That is, the color "transparent" replaces the color behind it. If transparency is found at the time of output from the pixel buffer means, it is not known how many colors can replace the pixel. Therefore, it is necessary to know the transparency information at the time of drawing in the pixel buffer means, and to control not to draw in the case of transparency.

When the transparency control means is employed, transparency can be recognized as a color which can be written on the palette. Also,
The memory capacity of the palette can be reduced as compared with the method in which the palette is placed before the pixel buffer. Traditionally, transparency has been treated separately from color. According to the present invention, information for writing transparency in the palette is separately stored and controlled in the preceding stage of the pixel buffer, so that it is possible to make it appear as if a color called transparent exists. Also, the method of placing the palette in front of the pixel buffer and realizing transparency as a color increases the capacity of the pixel buffer, but the method of the present invention can be realized without increasing the size of the pixel buffer means.

A third aspect of the present invention includes a pattern data which is a two-dimensional array of pixels and a plurality of pieces of attribute information characterizing the pattern. Header reading means having a character data structure capable of identifying the attached character, inputting information designating the attribute information, and outputting the designated attribute information and information designating a pattern data portion of the character data; The gist of the invention is a scanning-type image generation circuit means having the following.

Conventionally, pattern data and attributes characterizing the pattern have been separately managed. This is because the pattern data, which is the essence of the character, was regarded as important, and the description format and the used color scheme of the pattern were recognized as secondary items (that is, attributes) attached to the pattern. Further, the pattern data of the same format has the same size, so that patterns can be easily managed by numbers, and there is an advantage that when the characters are arranged in order on the screen, the arrangement of the patterns is also arranged in order.

However, in actual use, pattern data has a specified pattern description format such as the number of bits of a pixel or the size of a character, and can be used only in that format. In addition, there are many cases where only one or a few types of color arrangements are used, or where character inversion is not performed. This has a lot of redundancy in describing characters,
This means that there is room to reduce this redundancy.

Further, on the side using the character (object generating means), it is necessary to specify a character pattern and an attribute, which requires a large storage capacity. When a format (attribute) is specified by a register, only one format can be specified on the entire screen, and it is difficult to mix characters of various formats on the screen.

Therefore, in the present invention, a character pattern and its attributes are arranged in a continuous storage area,
Character patterns and attributes can now be specified simply by pointing to the storage location. In addition, in order to cope with several types of variations, a plurality of attributes are included in one character, and a character having a variation can be efficiently described by specifying the position of the corresponding attribute for specifying a character.

As a result, the side using the character needs only the number specifying the character pattern and the address specifying the character for the attribute.
This leads to AM capacity reduction. Furthermore, compared to having to set patterns and attributes in a program, it is only necessary to set the address of the character, so the program size can be reduced, the processing speed can be improved, and the convenience in creating software can be improved. Can be expected.

In addition, compared to a method in which a format (attribute) is specified by a register, characters of a plurality of formats can be mixed in one screen, so that flexibility in designing a screen is improved and at the same time, a minimum capacity capable of describing characters. Format can be used, leading to a reduction in memory capacity.

A fourth aspect of the present invention is to unify a plurality of different character designation formats for designating a character by inputting information indicating a format designating a character and information designating a character represented by the format. The present invention is characterized in that scanning-type image generating circuit means is provided, which comprises character-instruction-format converting means for converting the output into a generic format and outputting the converted character.

In the method of designating a character with attributes as described in the third invention, an address is appropriate. Also, when trying to represent a large number of characters, the number of bits for representing an address pointing to the character inevitably increases. However, the numbering method and the alignment method are useful for applications such as full graphic use and the use of characters using only conventional patterns. further,
Since a simple application does not use so many characters, it is preferable to adopt a character designation format with a smaller number of bits. Therefore, according to the present invention, a conventional method, a new method, or a character designating method having a different number of bits can be selected.

As a result, it is possible to cope with a new expression method without impairing the advantages of the conventional expression method, and it is possible to use a RAM having a smaller capacity depending on the format of character designation.

The character designation format conversion means designates a character with a pointer (address) so that a character with a header or a character having a different size can be designated.

Further, a base register or a segment register array may be provided so that a wide memory space can be pointed by a low bit pointer. Further, a format selection register may be provided so as to be able to switch between these formats and the preceding character number format.

[0050]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the scanning image generating circuit means according to the present invention will be described.

In the block diagram shown in FIG. 1, (1) is a clock generating means. Various square wave oscillators can be used as the clock generation means. Alternatively, a clock may be borrowed from another independent circuit.

The clock generated by the clock generating means (1) is input to the scanning position generating means (2). The scanning position generating means (2) generates scanning position information such that vertical scanning is performed while repeating horizontal scanning of an image based on the clock. The means (2) includes a horizontal and vertical counter. The scanning may be a scanning method for only pixels to be displayed and not having a blanking period.

(3) is an object generating means, which is a text generating means (4) and a sprite generating means (5).
And an object selecting means (6) for selecting these. The text or sprite, which is an object, may be provided with rotation, enlargement, and reduction parameters so that the figure can be deformed. In this case, the deformed shape is calculated, and this is combined with the pixel buffer means (16) described later.
By judging the overlap of the objects, it is possible to limit the objects. The pixel generation means (10), which will be described later, can specify the data of the corresponding pixel by the coordinate calculation.

As the object generated by the object generating means (3), in addition to the above-described text and sprite, geometric figures such as polygons, line segments, arcs, and points can be adapted. Polygons use vertex coordinates as parameters,
The portion surrounded by the vertices is the pixel buffer means (1
The object can be limited by calculating the overlap with 6). In the case of a polygon, the depth value of a vertex can be complemented to generate a different depth value for each pixel. Further, the polygon may be such that the inside is filled with a fixed color or a texture may be attached. In the case of a texture, a pixel is generated by calculating the position of the corresponding pixel on the texture and reading out the texture data.

The object from the object generating means (3) is input to the object limiting means (7).
The object limiting means (7) determines from the scanning position information generated by the scanning position generating means (2) whether the object overlaps a pixel buffer means (16) corresponding partial image, which will be described later, and overlaps. Acts to output only objects.

The object limited as described above is
It is input to the character designation format conversion means (8). The conversion means (8) is for inputting information indicating a format indicating a character and information indicating a character represented by the format, converting the information into a unified format, and outputting the unified format. A character is designated by a pointer (address) so that a character or a character having a different size can be designated.

Here, the designation format handled by the character designation format conversion means (8) is an address itself, an address aligned with the base size of the character pattern, and a character format (the number of bits per pixel and the size of the character). ) Calculates the size of the character pattern and there is a character number or the like which is aligned with this size. Further, a method of offsetting an address, such as a base register, a segment method, or a paging method, may be employed. Further, an indirect addressing method may be employed.

The character thus converted is input to the header reading means (9). The header reading means (9) makes the character usable by only specifying the character data by attaching attribute information to the character.

The header reading means (9) places attribute information as a header before the character pattern, but the same can be achieved by placing the attribute information as a footer. The storage position of the character pattern may be indirectly known from the storage position of the attribute information. The attribute information described in the header may be information on the size of a character, a color value in a system that does not pass through the palette, and the like, in addition to the bit number of one pixel, the palette number, and flip information.

The object generated by the object generating means (3) as described above is input to the pixel generating means (10), and is decomposed into pixels by the means, and the code value and the depth value relating to the color of the pixel are obtained. , Pixel information such as position information is output.

On the other hand, a control means (11), a transparent storage means (12) and a transparent control means (13) are provided. As the control means (11), a dedicated CPU may be used. Alternatively, the personal computer may be used as the control means and the circuit means according to the present invention may be mounted on an expansion board. The transparent storage unit (12) is provided with the control unit (1).
If the value written in the pallet means (21) described later is transparent by 1), the pallet address is stored. The transparency control means (13) judges whether or not the code value is transparent by accessing the transparency storage means (12) based on the pixel information generated by the pixel generation means (10). Is transmitted to the pixel drawing means (15) via the pixel limiting means (14).

The pixel limiting means (14) limits only pixels overlapping the partial image corresponding to the pixel buffer means (16), and the pixel drawing means (15)
Is output to On the other hand, the pixel drawing means (15) accesses the pixel buffer means (16) based on the scanning position information from the scanning position generating means (2) and the position information from the pixel generating means (10),
The depth value from the depth buffer (17) is compared with the depth value from the pixel generation means (10), and the code value and pixel value of the pixel buffer means (16) are generated based on the result of the comparison. The code value and the depth value from the means (10) are updated.

The pixel buffer means (16) comprises:
As shown in FIG. 2, the image is constituted by a pixel buffer unit smaller than the number of pixels constituting one horizontal row of the image. However, the number is not particularly limited.
Each pixel buffer unit is composed of a depth buffer (17) for storing a depth value relating to the depth of a pixel and a code buffer (18) for storing a code value which is information relating to the color of the pixel. . Then, the pixel information is sequentially stored in pixel units such that the scanning position is at the end and the buffer capacity ahead of the scanning position is at the beginning, and when the scanning position is moved, the pixel information storage position at the end is stored at the beginning. Switching is performed by circulating through the pixel buffer unit in pixel units so as to come to the position.

As the depth buffer (17) and the code buffer (18), a dual port memory dedicated to an image having a serial access port and a parallel access port in addition to a general-purpose RAM / IC is used. be able to. In this case, drawing is performed by the parallel port, display is performed by the serial port, and arbitration means is performed by the dual port.
It will be inside the memory.

The scanning position information from the scanning position generating means (2) is input to a buffer output means (19), and the buffer output means (19) changes the color of the pixel at the scanning position based on the scanning position information. After reading out a code value which is related information, the pixel buffer means (1
Delete the contents of 6).

The drawing request from the pixel drawing means (15) to the pixel buffer means (16) and the display request from the buffer output means (19) to the pixel buffer means (16) are arbitrated. For this purpose, a buffer access arbitration means (20) is provided. The arbitration means (20) may be configured so that drawing and display are separated at a fixed time.

Palette means (21) for converting and outputting color information of display pixels based on the display pixel code value from the buffer output means (19) is provided. Further, a synchronizing signal generating means (23) for generating a synchronizing signal based on the information from the scanning position generating means (2), and a color information from the pallet means (21) and a synchronizing signal from the synchronizing signal generating means (23). A video signal generating means (22) for synthesizing the signal and converting it into a composite video signal is provided.
The pallet means (21) and the video signal generation means (2)
For 2), a commercially available video encoder IC with a pallet can be used.

The pixel access means is realized by three cycles of precharge, read, compare and write by utilizing read and write to the same address as a pair. Equipped with speed-up means.

[0069]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment according to the present invention shown in FIG. 3 will be described below. The illustrated embodiment is a part of a monolithic one-chip unit.

The reset circuit (60) detects a drop in the power supply voltage, and when the power is turned on or off, a reset signal LPW for protecting and initializing the system and a system signal when the power is turned on or the system is restarted. And a reset signal RES for initializing the reset signal RES. When the LPW signal becomes active, the RES signal becomes active at the same time, and the RES signal is not released for a while even if the LPW signal is released.

The clock generator (61) (clock generating means (1)) generates the fundamental frequency oscillated by the crystal oscillator by multiplying it by the PLL. The frequency of the crystal oscillator is inevitably determined based on the frequency to generate a standard signal of NTSC / PAL. Moreover, the frequency of each standard color subcarrier itself was selected as the frequency at which the price of the oscillator was lowest. That is, NTSC is 3.579545 MHz and PAL is 4.4.
33361875 MHz.

Since the frequencies of the crystal oscillators are different between the two standards, the multiplication rate is changed by the NTSC / PAL input so that the output frequencies are substantially the same. This is because it is preferable that both standards have almost the same horizontal period, the pixel frequency will be almost the same if the screen configuration is the same, and that the processing performance of the system will be determined by this frequency and there will be a difference in performance between the two standards. Because there is no. Specifically, NTSC
In the case of CK80, 96/4 times the input, in the case of PAL, CK80 of 96/5 times the frequency, and CK4 obtained by further dividing the frequency by 2
CK20 that is divided by 0 and 4 is output.

The timing generator (62) (scanning position generating means (2)) includes a clock generator (6).
The horizontal scanning position signal H is based on the clock CK20 from 1).
[11], vertical scanning position signal V [9], composite synchronization signal S
YNCH and a timing signal such as a composite blanking signal BLANK, a burst flag signal BURST, and a line alternation signal LA are generated.

This is composed of a frequency divider, and is composed of NTSC / PA
L changes the frequency division ratio. In NTSC, 1 horizontal is 1
The frequency is divided by 365, and 263 horizontal is set to 1 vertical. Also PAL
In this example, 1 horizontal is divided by 1362 and 314 horizontal is set to 1 vertical. In both cases, interlacing is not performed, unlike the standard system, in order to eliminate the vertical movement of the screen. This division ratio is NTSC / PA
This is to provide a horizontal / vertical frequency close to the standard signal of L and an interleave method conforming to the standard. NTSC has 180 degree interleaving for both line and frame, PA
L sets the line interleave to 270 degrees. However, the frame interleave of PAL is set to 180 degrees unlike the standard. This is to reduce the dot interference that the subcarrier gives to the luminance in the non-interlace system.

The reset of the timing generator (62) is performed only once at power-on using the LPW signal. This is to prevent the synchronization signal from disappearing and the screen from being disturbed when the system is restarted.

The scanning position (H, V) is scanned such that the upper left of the display screen is (0, 16) and the lower right is (1023, 239). The pixel position is represented by the upper 9 bits of H and all bits of V, and the display screen is 256 (horizontal) × 224.
(Vertical) pixels. Therefore, one line contains 256 pixels. The relationship between the screen indicated by the scanning position and the synchronization signals is slightly shifted in consideration of the processing delay.

As the CPU (63) (control means (11)), an 8-bit microprocessor is mounted so that the contents and registers of the memory can be accessed via the bus. A bus including an address line, a data line, a control line, and the like is connected from the CPU (63).

The main memory (64) includes programs,
There is a memory for storing data, characters, etc., which is connected to the bus.

Sprite generator (65) (sprite generating means (5)) (object limiting means (7))

The sprite generator (65) has C
There are a register and a sprite memory which can be accessed from the PU (63), and these store various information of the sprite. The register stores the format T of the address information of all sprites and the location W of the header. In the memory, the number of bits B per pixel of each sprite, the size S of the character, the flip information F, the horizontal position X, the vertical position Y, the depth value Z, the palette value P, and the storage position of the character on the main memory (64) Is stored.

The sprite generator (65) searches this memory based on the information on the scanning positions H [11] and V [9] to limit the sprites that are overlapping (appearing) with the pixel buffer (78). And T [3], W, B
[3], S [2], F [2], X [9], Y [5], Z
A signal consisting of [4], P [4], and A [24] is output.

Here, there are VALID and WISH handshake signals for transmitting data from the former stage to the latter stage. VALID is a control signal transmitted from the sender to the receiver, and becomes active together with the data when the data to be sent is ready. WISH is a control signal transmitted from the receiver to the sender, and becomes active when data is accepted. One data is transmitted while both signals are active (one clock). The circuit is initialized by the RES input and operates in synchronization with the clock of CK40.

Text generator (66) (text generating means (4)) (object limiting means (7))

The text generator (66) has a CP
U (63) is provided with registers that can be accessed by pointers L, H,... Pointing to an array on the main memory (64) that stores information of each text.
A and the number of bits per pixel B applied to all text,
Character size S, flip information F, horizontal movement amount X, vertical movement amount Y, depth information Z, pallet information P, address information format T, and attribute location W are stored. The array on the main memory (64) pointed to by the pointer includes address information A, pallet information P, and depth information Z indicating the position of the character used for each text on the main memory (64). Attribute information is stored. The address information has a size (1 to 3 bytes) according to the format of the address information, and the attribute information becomes valid when the attribute is designated to be stored in an array at the location of the attribute.

The text generator (66) outputs H [1
1] and V [9] based on the information of the pixel buffer (7
8) The text information (array element) overlapping (overlapping) with (8) is read from the main memory (64) through the bus and output.

Here, only when the address information is 0, it is determined that the text itself is transparent and is not transmitted. V to the next stage
ALID, T [3], W, B [3], S [2], F
[2], X [9], Y [5], Z [4], P [4], A
[24] E (emergency signal) is output and WISH is input. Here, the emergency signal E is a signal that activates this signal to prompt the subsequent stage to receive data when the output data is not easily transmitted to the subsequent stage. This signal is activated when it detects that the difference between the output position information and the position information of H and V has widened. The circuit is RE
Initialized in S, it operates with the clock of CK40.

Selector / Mixer (67) (Object Selector (6)) (Object Generator (3))

The object information is selected / integrated from the text and sprite and sent to the subsequent stage. Normally, sprites are selected with priority, but when emergency output of text is active, text is selected with priority.

Sprite generator (65) at the preceding stage
Are VALID, T [3], W, B [3], S
[2], F [2], X [9], Y [5], Z [4], P
[4], input of A [24], output of WISH, and text generator are VALID, T [3],
W, B [3], S [2], F [2], X [9], Y
[5], Z [4], P [4], A [24], E input and WISH output. The latter stage is WISH input and VAL
ID, T [3], W, B [3], S [2], F [2],
X [9], Y [5], Z [4], P [4], A [24]
It is. The circuit is initialized by RES and operates with the clock of CK40.

The second text generator (68)

Two text generators (66, 68) were prepared so as to have two text screens and form a deep background image on the screen. The configuration and input / output are the same as those of the first device (66). The address for accessing the register from the CPU (63) is different from that of the first address (66).

The second selector / mixer (69)
The output of the first text generator (68) and the output of the first selector / mixer (67) are selected / integrated by the second selector / mixer (69). The configuration is the same as that of the first selector / mixer (67), and the priority is given to the first selector / mixer (67).

The address generator (70) (character designation format conversion means (8)) is a circuit for converting address information into a real address in accordance with the format of the address information from the preceding stage. The address generator (70) has a 16 × 16-bit segment memory accessible from the CPU (63), and stores a base address and a segment address necessary for converting the address. There are five types of address formats, one for character selection is an 8-bit number, and one is 16-bit.
Bit numbers are used, one for a 16-bit aligned pointer, one for a 16-bit pointer, and one for a 24-bit pointer.

The format of the 8-bit and 16-bit numbers is indicated by the bit number B of one pixel from the preceding stage and the size information S based on the base address (256-byte alignment) stored at address 0 of the segment memory. Capacity of one character ((B + 1) × f (78), f (0) =
64, f (1) = f (2) = 128, f (3) = 25
6) Every other address is calculated. For the 16-bit aligned pointer, the upper 3 bits of 16 bits
An address is calculated by adding the segment address (256-byte alignment) stored in the segment memory indicated by the bit and the lower 13 bits (8-byte alignment).

For the 16-bit pointer, the segment stored in the segment memory indicated by the upper 4 bits
The sum of the address (156-byte alignment) and the lower 12 bits is the real address. In the last 24-bit pointer, this value becomes the real address as it is.

These calculated addresses are transmitted to the subsequent stage together with other parameters. Here, since only the format T of the address information is not used anymore in the subsequent stage, it is not transmitted. The circuit is initialized by RES and operates with the clock of CK40.

Header fetcher (71) (header reading means (9))

The character data has a format with a header and a format without a header. Character data with a header includes a header and a pattern. And the header has at least one byte. Each byte of the header includes pallet information, and one byte immediately before the pattern includes a bit number of one pixel of the character and a flag indicating that the byte is a byte immediately before the pattern. The bytes before that also contain flip information instead of the number of bits, and a flag indicating that the byte is not the byte immediately before the pattern and distinguishing between two or more than three bytes away from the pattern.

When character data with a header is designated, one of a plurality of header bytes is designated. If the designated byte is the byte immediately before the pattern, the bit number of one pixel and pallet information stored therein are adopted as attributes, and the flip is a default value (no flip). If the specified byte is not immediately before the pattern, the palette information and flip information of the byte and the number of bits of one pixel of the byte immediately before the pattern are adopted as the attribute of the character.

The attribute location information W from the previous stage indicates whether the character data has a header or no header. If the character has a header, the header information is read from the main memory (64) designated by the character address A, and the attribute information is transmitted to the subsequent stage. Also, the address is advanced to indicate the beginning of the pattern. The circuit is initialized by RES and operates with the clock of CK40.

Strip generator (72) (pixel generating means (10))

In this example, a horizontal row of 1s to be drawn and displayed from character data that is a two-dimensional array is displayed.
Extract a dimensional array. Which one-dimensional array is specified by the vertical position Y [5] and the vertical flip information F [2] from the preceding stage, and the scanning positions H [11] and V [9]. Since the maximum vertical size of the character is 16 pixels, the vertical position information Y,
It is enough for V to have the lower 5 bits. Since the character data is arranged in a two-dimensional array as a horizontal one-dimensional array, the start address (character
Based on the pattern address), the head address of the corresponding one-dimensional array is calculated and transmitted to the subsequent stage. At this time, the number of bits B [3] of one pixel from the previous stage and the horizontal size S [2] of the character are used. Thereafter, the size and the vertical information of the flip and the vertical position are not used, so that the information is not transmitted to the subsequent stage. The previous stage is VALID, B [3], S [2], F
[2], X [9], Y [8], Z [4], P [4], A
The input [24] and the WISH output, and the subsequent stage are the WISH input and VALID, B [3], S [1], F [1], X
[9], Z [4], P [4], A [24] (strip address) connected at output. The circuit is initialized by RES and operates with the clock of CK40.

Character fetcher (73) (pixel generation means (10))

The character information transmitted so far in the form of an address is converted into the form of data (code information) actually used by accessing the main memory (64). From the position on the main memory (64) designated by the strip address from the preceding stage, data corresponding to the number of bits of one pixel and the capacity represented by the horizontal size are read and sequentially transmitted to the succeeding stage. The preceding stage is VALID, B [3], S [1], F
[1], X [9], Z [4], P [4], A [24] input and WISH output.
ID, B [3], S [1], F [1], X [9], Z
[4], P [4], and D [8] (data) output. The circuit is initialized by RES and operates with the clock of CK40.

Pixel generator (74) (pixel generating means (10))

The data from the preceding stage is in units of 8 bits, and is different from the number of bits of one pixel in many cases. Here, the data in byte units is redistributed in pixel units. The distribution method is such that byte data that comes in order is arranged in little endian, and the number of bits of one pixel is taken from the lower end. Data in pixel units is combined with pallet information to generate 8-bit code information. In this synthesizing method, first, upper 4 bits of 8 bits are filled with palette information, and then lower bits corresponding to the number of bits of pixels are filled with redistributed pixel data. The remaining bits are filled with 0. When one pixel is 5 bits or more, the palette information is eroded from the lower order by the pixel data.

Since the horizontal position of a pixel increases based on the position of the character, the horizontal position of each pixel is calculated and transmitted to the subsequent stage. At this time, if the horizontal flip is inverted, the calculation is performed so that the horizontal position once decreases by the horizontal size and then decreases.

The number of bits per pixel, size information,
Since the flip information and the pallet information are not used thereafter, they are not transmitted to the subsequent stage.

The preceding stage is VALID, B [3], S
[1], F [1], X [9], Z [4], P [4], D
[8] Input and WISH output, the latter stage is WISH input and VALID, X [9] (horizontal position in pixel unit), Z
[4], connected with C [8] (code) output. The circuit is initialized by RES and operates with the clock of CK40.

The transparent control circuit (75) (transparent storage means (1)
2)) (Transparency control means (13))

The transparent control circuit (75) includes a 16-row × 5-bit transparent control memory which can be indirectly accessed from the CPU (63). The palette memory has a configuration of 16 rows × 16 columns, and a maximum of one transparency can be set in each row. CPU
If (63) writes a color in the palette memory and the color is transparent, the transparency control memory stores which row and column of the palette memory. The row corresponds to the row of the transparent control memory as it is, and the column represents the position information by 4 bits. The transparency written last in each palette is valid. If you write a non-transparent color on top of the transparency you last wrote, the line will not be transparent. This is represented by the remaining one bit in each row of the transparency control memory.

The transparent control memory is accessed with the upper 4 bits of the code information input from the previous stage, and the contents are valid and lower 4 bits.
If it matches a bit, it is considered transparent. The non-transparent pixel information is transmitted as it is to the subsequent stage, and the transparent pixel is discarded here without being transmitted to the subsequent stage. The first stage is VALID, X [9], Z [4], C [8] input and WISH output, and the second stage is WISH input and VALID,
Connected at X [9], Z [4], C [8] outputs. The circuit is initialized by RES and operates with the clock of CK40.

Draw driver (76) (pixel limiting means (14)) (pixel drawing means (15))

From the horizontal position X and the horizontal scanning position H [11] of the inputted pixel information, it is checked whether the pixel overlaps the pixel buffer (78), and the overlapping pixel is drawn in the pixel buffer (78). Make a request.
The horizontal scan position is 1 after requesting and before it is accepted.
Because of the possibility of stepping, the pixel buffer (78) determines overlap in an area one pixel less.

The preceding stage is VALID, X [9], Z
[4], C [8] input and WISH output.
An IT (standby signal) input is connected to R (request signal), X [7] (buffer address), Z [4], and C [8] outputs. The circuit is initialized by RES and operates with the clock of CK40.

Pixel buffer control circuit (77) (buffer access arbitration means (20)) (access speed-up means (24))

A request from the draw driver (76) and a request from the view driver (81) are arbitrated. The request from the view driver (81) has priority. The arbitrated request generates a three-cycle timing signal (precharge signal, read signal, write signal) at 80 MHz to drive the pixel buffer (78) memory. In response to a request from the draw driver (76), the read depth value is compared with the input depth value, and as a result, it is determined whether the data to be written is the read data or the input data. In response to a request from the view driver (81), the inner code information of the read data is output to the next stage, and then the data to be written for clearing is fixed at 0. R, X [7], Z from the draw driver (76)
[4], C [8] input and WAIT output, and the view driver (81) is R, X [7] input and C [8] (code) output. In addition, the pixel buffer (7
8) MP (precharge) and MR for accessing
(Read), MW (write), MA [7] (address), MO [12] (read data), MI [12]
(Write data). The circuit is initialized by RES and operates with the clock of CK80.

The pixel buffer (78) (pixel
Buffer means (16) (depth buffer means (1
7)) (Code buffer means (18))

The pixel buffer (78) comprises a depth buffer (79) and a code buffer (80).
128 pixels x 4 bits, 128 pixels x
8 bits. Input / output signals are MP, MR, MW, M
A, MI and MO.

View driver (81) (buffer output means (19))

Based on the scanning position information H [11] and V [9], a data read is requested to the pixel buffer (78) control. The request is made with the request signal R and the buffer address X. Since the request is handled preferentially by the control of the pixel buffer (78), there is no signal to wait for the request. Further, the code information C [8] transmits the read data to the next stage in synchronization with the pixel separation timing (5 MHz, the second bit from the lower bit of H). The circuit is initialized by RES and operates with the clock of CK40.

The pallet circuit (82) (pallet means (2
1))

The palette (82) has a capacity of 256 colors × 13.
It has a palette memory of bits and can be accessed from the CPU (63). The code VC [8] from the preceding stage is accessed as an address, converted into 13-bit color information and output. 13-bit breakdown: Hue PH [5], Saturation PS
[3], consisting of lightness PL [5]. Hue is an integer from 0 to 23, saturation is an integer from 0 to 7, and lightness is an integer from 0 to 23. Transparency is represented when the hue accessed from the CPU (63) is from 24 to 31 (see transparency control). The circuit is initialized by RES and operates with the clock of CK40.

Window generator (83)

The screen is divided into two parts by a circuit for producing a special effect on the screen, and one of the two parts is a color effector (8
The effect can be given in 4). The configuration is CPU (6
There is a register that can be accessed from 3) to set the coordinates of the start point and end point of one horizontal line, and the logic of the left end of the screen. The output WIN starts with the set logic first, becomes active when the horizontal scanning signal H [11] matches the start point, and becomes inactive when it matches the end point. Furthermore, each time the output logic changes by setting the register, an interrupt can be generated for the CPU (63) so that the start point and the end point can be sequentially changed. By combining these, the active part and the non-active part can be roughly formed on the screen. The circuit is initialized by RES and operates with the clock of CK40.

Noise generator (85)

This is a portion for generating noise for producing one of the visual color effects realized by the color effector (84). This is a digital pseudo-random number sequence generator using an M sequence (polynomial counter).
The bit N [3] is output as a noise component. The M-sequence counter is reset by the power supply voltage drop detection signal LPW so as not to go around in an abnormal loop. The circuit is RES
And operates with the clock of CK20.

Color effector (84)

This is a circuit for giving various visual effects to the input color. Further window generator (83)
This function can be activated / deactivated by the signal WIN from the CPU. There is a register that can be accessed from the CPU (63), and the effect can be set with this register. One of the effects is hue H [5], saturation S [3], lightness L
By fixing each element of [5], there are a flag for setting each element separately and a value for fixing each element in the register. One is to reduce the luminance by half, and there is a control flag. When this flag is active, the brightness L
The values of [5] and the saturation S [3] are each halved.

One is to invert the negative / positive, add the value 12 to the hue H [5], and if the result exceeds 23, subtract the value 24 so as to go to 0, and the lightness L [5] This is realized by reversing the brightness by subtracting from 23. One is to add an appropriate noise to the luminance, and the lower three of the lightness L [5] are added.
Bit and noise from noise generator (85)
An exclusive OR operation with the data N [3] is performed. These three bits have a flag that can be set for each bit to determine whether or not to perform the operation, and the amount of noise added can be adjusted. The circuit is R
It is initialized by ES and operates with the clock of CK40.

Video encoder (86) (video signal generating means (22))

The input color information and timing information such as a synchronization signal are converted into a standard video signal corresponding to NTSC / PAL input.

[0133] It circulates so that the value following the value 23 becomes the value 0 5
There is a 24-bit counter in bits, this counter is 20
For each clock CK20 of MHz, NTSC sets PAL by 4
Goes forward by 5. Therefore, NTSC makes one lap six times and PA
L makes one round in 4.8 times. Since this counter circulates exactly at the cycle of the subcarrier, it can be regarded as a subcarrier oscillator, and the value of this counter indicates the phase. Here, in the case of NTSC, since the lower 2 bits of the counter do not change, this is asymptotically set to 0 so as to focus on the same pattern.

The hue H [5] of the input color data and the phase of this subcarrier are added to create a wave in which the subcarrier is phase-modulated with the input hue data. The phase data of the phase modulated wave is converted into amplitude data by the waveform ROM. Further, the input chroma S [3] is multiplied by the amplitude data to perform amplitude modulation with the chroma to obtain a modulated color signal. This is converted into an analog signal by an AD converter and output to the outside of the chip. Also, the input brightness L [5]
Is converted into an analog signal by an AD converter and output to the outside of the chip by adding a value 8 offset. Further, a luminance signal and a chrominance signal are added to form a composite video signal, which is converted into an analog signal by an AD converter and output to the outside.

Here, the luminance signal is black level = value 8 when the composite blanking signal BLANK input is active.
When the composite sync signal SYNCH input is active, the sync level is set to 0.

The hue input and the saturation input are controlled so that the value becomes 0 when the blanking signal is active, and the value becomes constant when the burst signal is active. Instead, a color burst signal is output at a predetermined timing.

Video function generator (87)

The blanking period of the screen is separately set by the CPU (6
There is a circuit to notify 3). This corresponds to the scanning position information H [1
1] and V [9] to recognize the blanking period and interrupt the CPU (63) at the start timing. There is also a mechanism for generating an interrupt at an arbitrary position on the screen. There is a register for storing the horizontal and vertical positions accessible from the CPU (63), and the timing is known by constantly comparing the contents with the position information, and an interrupt is issued. These interrupts are sent to the CPU (6
Activation / deactivation can be controlled in 3).

[Brief description of the drawings]

FIG. 1 is a block diagram showing a basic configuration of the present invention.

FIG. 2 is a conceptual diagram of a pixel buffer means of the present invention.

FIG. 3 is a circuit diagram showing an embodiment of the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 clock generating means 2 scanning position generating means 3 object generating means 4 text generating means 5 sprite generating means 6 object selecting means 7 object limiting means 10 pixel generating means 11 control means 12 transparent storage means 13 transparency controlling means 14 pixel limiting means 15 pixels Drawing means 16 Pixel buffer means 17 Depth buffer 18 Code buffer 19 Buffer output means 20 Buffer access arbitration means 21 Palette means 22 Video signal generation means 23 Synchronization signal generation means 24 Buffer access speed-up means

Claims (11)

[Claims] 1. A scanning-type image generating circuit means for generating an image comprising a two-dimensional pixel array, comprising a plurality of pixel buffers each storing pixel information on a pixel-by-pixel basis. Pixel information is sequentially stored in each pixel buffer unit in pixel units so that the buffer capacity ahead of the scanning position is the leading pixel, and the last pixel is stored when the scanning position moves to the next pixel buffer unit. A pixel buffer means for circulating and switching the pixel buffer unit in pixel units so that the information storage position becomes the first pixel information storage position. means. 2. A scanning image generating circuit means for generating an image formed of a two-dimensional pixel array, comprising: a clock generating means; and scanning one horizontal row of the image based on a clock generated by the clock generating means. Scanning position generating means for generating a scanning position for performing vertical scanning while repeating; and a plurality of pixel buffers each storing pixel information in pixel units. Is sequentially stored in the pixel buffer units in units of pixels such that the first pixel information is stored in the pixel buffer unit when the scanning position moves to the next pixel buffer unit. The pixel buffer unit is circulated and switched in pixel units so as to be the information storage position. The pixel buffer unit includes a depth buffer for storing a depth value relating to the depth of a pixel and a code buffer for storing a code value which is information relating to the color of the pixel.
Buffer means, after reading the code value at the scanning position from the code buffer based on the scanning position information from the scanning position generating means, and buffer output means for erasing the contents of the pixel buffer unit; A palette unit for converting and outputting color information of a display pixel based on the code value from the buffer output unit; an object generation unit; a code for decomposing the object from the object generation unit into pixels, and relating to the color of the pixel. A pixel generating unit that outputs pixel information such as a value, a depth value related to the depth of the pixel, and positional information of the pixel; based on scanning position information from the scanning position generating unit and pixel position information from the pixel generating unit. Accessing said pixel buffer means at said Pixel drawing for comparing the depth value of the pixel data with the depth value from the pixel generation means, and updating the code value and the depth value of the pixel buffer means with the code value and the depth value from the pixel generation means based on the result. And a buffer access arbitration unit for arbitrating an access request to the buffer unit from the buffer output unit and an access request to the buffer unit from the pixel drawing unit. Image generation circuit means. 3. The scanning-type image generating circuit according to claim 1, wherein said pixel buffer stores pixel information of a number smaller than the number of pixels constituting one horizontal row of the image. . 4. The pixel buffer corresponding to the pixel buffer means based on the scanning position information from the scanning position generating means and the position information from the pixel generating means among the pixel information from the pixel generating means. 3. The scanning image generating circuit means according to claim 2, further comprising a pixel limiting means for limiting only the pixels which are present and outputting to the pixel drawing means. 5. A method for determining whether an object generated by said object generating means overlaps a partial image corresponding to said pixel buffer means, based on scanning position information generated by said scanning position output means. 3. The scanning type image generation circuit means according to claim 2, further comprising an object limiting means for outputting. 6. The pixel buffer means performs three kinds of precharge, read, and comparison / write by utilizing the fact that read and write to the same address are paired.
3. The scanning image generating circuit means according to claim 2, further comprising a buffer access speed-up means realized in a cycle. 7. The scanning-type image generating circuit according to claim 2, wherein said object generating means comprises a text generating means, a sprite generating means, and an object selecting means for selecting one of them. 8. A synchronizing signal generating means for generating a synchronizing signal based on information from the scanning position generating means, and a composite video signal by synthesizing the color information from the pallet means and the synchronizing signal from the synchronizing signal generating means. 3. The scanning image generation circuit means according to claim 2, further comprising a video signal generation means for converting the video signal into a video signal. 9. A control means; a transparent storage means for storing a pallet address when a value written to the pallet means by the control means is transparent; and pixel information generated by the pixel generation means. A transparency control means for judging whether or not the code value is transparent by accessing the transparent storage means on the basis of, and transmitting only non-transparent pixel information to the pixel drawing means,
3. A scanning image generation circuit means according to claim 2. 10. A character that is characterized by a pattern data that is a two-dimensional array of pixels and a plurality of pieces of attribute information characterizing the pattern. It has a character data structure that can be specified, and has header reading means for inputting information designating the attribute information and outputting the designated attribute information and the information designating the pattern data portion of the character data. Scanning image generation circuit means. 11. A plurality of different character designation formats for designating a character are converted into a uniform format by inputting information indicating the character designation format and information designating a character represented by the format, and outputting the converted format. Scanning image generation circuit means comprising character designation format conversion means.