JPH10215288A - Noncontact ic card - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a stable clock signal in synchronism with an input signal by detecting a rise and a fall of a signal and delaying it through OR processing, generating an enable signal for phase detection from the OR signal and gating a signal of a VCO oscillation circuit with the enable signal, and making a phase comparison between the rise and fall signals. SOLUTION: With a PSK-modulated signal 7a received by a coil 7, a binarizing circuit 301 generates a digital signal 3a, and a leading edge detecting circuit 302 and a trailing edge detecting circuit 303 generate edge pulse signals 3b and 3c. Those edge pulse signals 3b and 3c are put together to generate an edge signal 3d, which is inputted to a delay circuit 305 and a gate signal generating circuit 306. The output 3f of the gate signal generating circuit 306 masked with a signal 3h generated by making the output signal 3g of a VCO circuit 309 into pulses by an edge detecting circuit 309 and after phase detection with the output of the delay circuit 305, the frequency of the VCO circuit 309 is controlled.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for generating a clock for a non-contact IC card, which receives power and transmits and receives information signals from a reader / writer, which is a higher-level terminal device, by electromagnetic coupling. The present invention relates to a method for generating a clock signal using a signal.

[0002]

2. Description of the Related Art In recent years, as storage media for electronic money and the like,
IC cards with built-in ICs such as processors are attracting attention. There is a contact type IC card which receives power and a clock from a reader / writer device, which is a higher-order terminal device, using a contact according to a signal transmission method and processes commands from the reader / writer device. However, contact-type IC cards have problems such as poor contact at the contacts, and have a problem in reliability. Therefore, in recent years, non-contact type IC cards have been developed.

FIG. 1 is a diagram showing an example of a non-contact type IC card and its reader / writer. The non-contact type IC card receives a radio wave (electromagnetic wave) emitted from the reader / writer device 21 through the coil 6 by the coil 7 of the IC card 10, and supplies the power supply circuit 1, the transmission / reception control circuit 2,
3, the power and the clock for the power supply by the memory 4,
A transmission / reception signal is generated, and a command transmitted from the reader / writer device 20 is processed.

[0004] Non-contact IC cards have communication distances of several mm to
There are a contact type of about 10 mm, a close type of several tens of mm, and a remote type of a communication distance of several tens to several meters.

[0005] Among these, regarding the contact type IC card, the international standard ISO10536, which defines the position, shape, and electrical characteristics of the coil, has recently been enacted and conformed to this standard.
IC cards and read / write devices are being developed.

According to ISO 10536, one or two coils are provided in a card, communication is performed on the coils at a frequency of 4.91 MHz, and the modulation for identifying 1/0 of information is performed by phase modulation (PSK). Modulation), and the card side is provided with a circuit for demodulating this.

Further, when an MPU is mounted in an IC card, a clock signal for operating the MPU is required. In the case of the contact-type IC card described above, this clock signal is also supplied from the contact-type terminal, but in the case of the non-contact-type IC card, it must be generated from the phase modulation (PSK modulation) signal. Further, since the clock signal is used to modulate and demodulate the information subjected to the phase modulation (PSK), the clock signal needs to be a signal synchronized with the input signal.

An example of a non-contact data communication method using PSK modulation will be described with reference to FIG. The transmission signal is CP
The signal is sent to the read / write control circuit 5 as an RS232 transmission signal 710 from U or the like, and becomes a transmission signal 701. The transmission signal 701 is a serial signal of a logical signal 0/1, and has a carrier (4 in ISO10536).
180 ° phase modulation (PSK modulation) is performed on the 91Mhz) signal. The PSK modulation signal 702 passes through a filter circuit or the like, becomes a transmission coil drive signal 303, and drives the transmission coil 6. On the other hand, on the IC card side, a reception signal 704 is obtained by the reception coil 7 which is electromagnetically coupled with the transmission side coil. The reception signal is converted into a digital signal by a transmission / reception control circuit 2 via a binarization circuit or the like, and then subjected to processing such as demodulation. The clock signal 320 is generated based on the binarized signal 3a, and the demodulated signal 705 is obtained by sampling the binarized signal 3a at the rise of the clock signal 320.

As described above, in order to demodulate data from a PSK modulation signal, a clock signal synchronized with an input PSK signal is required. As can be seen from FIG. 7, when the clock signal 320 deviates from the input signal by 1/4 period to 1/2 period, the demodulated 0/1 level is inverted. Even when the clock signal is not synchronized with the input signal, demodulation is not performed correctly.

A method of demodulating (detecting) a PSK modulated signal generally used in a communication device employs a method in which a local oscillator having the same frequency synchronized with a carrier wave is provided on the receiver side, and synchronous detection is performed using the local oscillator. doing. The local oscillator extracts only the carrier component from the PSK modulation signal by using a filter or the like, and generates a sine wave. However, circuits used in IC cards and the like need to be simple and inexpensive to implement LSIs. Therefore, it is necessary to generate a clock signal with a simple circuit.

As one method of generating a clock signal from a PSK signal, there is a method using a delay as shown in a timing chart of FIG. This generates a rising edge signal 3b and a falling edge signal 3c from the binary signal 3a,
In this method, a clock signal 802 is obtained by delaying the synthesized signal 3d by a Dt time (a half cycle of the clock) and calculating the logical sum of the synthesized signal 3d and the delay signal 801.

However, in the above method, the clock frequency is
In the case of ISO10536, it is 4.91Mhz, so the delay time is
It is as large as 102 nS, and it is difficult to realize a delay circuit using a CR circuit because it requires a large capacitor when it is configured by an LSI.

As another method for generating a clock signal synchronized with an input signal, there is a method using a PLL (Phase Locked Loop) based on the phase modulation signal.

Generally, a PLL circuit is composed of an input signal and an oscillation circuit (V
A phase difference from a signal from the signal from the CO is detected by a phase detection circuit, and a phase change signal is fed back as a control voltage of a VCO (voltage control type oscillation circuit) through an appropriate filter.

However, if the PLL circuit is configured based on the PSK-modulated signal, the period (phase) of the input signal changes at the time of phase modulation.
The phase between the input signal and the VCO clock deviates, which causes frequency fluctuation (referred to as jitter) in the clock.

The present invention relates to the above contact type (ISO10536 compliant) IC
Cards, especially IC cards using PSK modulation, PLL
An object of the present invention is to provide a method for stably generating a clock by a circuit method.

[0017]

In the above prior art, if a clock generation circuit is configured by a PLL circuit based on a PSK-modulated input signal, the period (phase) of the input signal changes during phase modulation (PSK). If the PLL is out of phase and cannot reproduce a clock synchronized with the input,
There is a problem that clock frequency fluctuation (jitter) increases.

When the PSK signal is transmitted by electromagnetic coupling through a coil, the transmission system has frequency characteristics, so that the frequency component changes at the phase modulation point, and the signal amplitude and pulse width change. There are also problems.

The change in the signal amplitude or the pulse width disturbs the phase of the PLL circuit and causes an increase in clock jitter.

Also, when the distance between the reader / writer and the IC card changes, the coupling coefficient (frequency characteristic) of the electromagnetic coupling changes, so that the signal amplitude and the pulse width also change.

An object of the present invention is to provide a circuit for synchronizing with an input signal and generating a stable clock using a PLL circuit in a contact type IC card.

[0022]

In order to achieve the above object, according to the present invention, as a first means, a signal (rising edge) of a signal received from an antenna coil is supplied to a clock generation circuit. Performs a logical OR operation on the circuit that detects the falling (trailing edge) and the rising and falling signals,
A delay circuit; and a circuit for generating an enable signal for phase detection from the logical sum signal, and using the enable signal to gate a signal of a VCO oscillation circuit to be input to the phase comparison circuit. A PLL type oscillation circuit is configured so that a phase of the processed signal of the VCO oscillation circuit is compared with a phase detection circuit.

As a second clock generating means, either a rising signal or a falling signal of the received signal is input to the delay circuit and the phase detection enable signal generating circuit, and Either the rising signal or the falling signal is compared with the gated signal of the VCO oscillation circuit by a phase detection circuit. That is, the phase detection circuit 307, the filter 30
8, VCO 309, edge detection circuit 310, AND circuit 3
11 constitutes a new PLL circuit.

[0024]

Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a contactless IC card reader / writer and an IC.
It is a figure showing a card. The reader / writer 20 generates a 4.91 MHz clock (which is also a carrier signal for power supply) and data (downlink data) to the PSK-modulated IC card by the read / write control circuit 5, and drives the coil 6. To the IC card side. On the other hand, data (uplink data) from the IC card to the reader / writer is received by the coil 6 and demodulated and reproduced. Here, the coil may be formed with a printed pattern of a conductive paste or the like, and a coil in which the line width of the pattern is partially changed may be used.

Further, the IC card 10 is
Upon receiving the above signal and generating a DC voltage in the power supply circuit 1, the transmission / reception control circuit 2 performs demodulation of downlink data and modulation of uplink data. The demodulated signal is
Write data to the memory 4 via the CPU 3. The upstream data read from the memory is transmitted to the CPU 3 and the transmission / reception control circuit 2
To drive the coil 7 through.

FIG. 2 is a diagram for explaining in detail the configuration of the wireless integrated circuit mounted in the IC card. Power supply circuit 1
Is composed of a rectifier circuit 11 and a constant voltage power supply circuit 12. Also,
The transmission / reception control circuit 2 includes a data reception circuit 21, a downstream data demodulation circuit 22, an upstream data modulation circuit 23, a data transmission circuit 24, a clock generation circuit 29, a timing generation circuit
It consists of 30 and so on. The upstream data drives the capacitors 27 and 28 via the driver 25 to change the impedance of the card-side coil. The reader / writer reproduces the upstream data by detecting the change in the impedance.

Here, the demodulation circuit 22 comprises a data receiving circuit 21
PSK modulation signal 3a, which is the output signal of
The received signal is demodulated using the clock signal 320 generated in step 9 as an input.

FIG. 3 is a diagram showing a clock generation circuit of the present invention. 4 and 5 are time charts for explaining the operation of the present invention.

The PSK modulated signal 7a received by the coil 7 passes through the binarization circuit 301 to become a digital signal 3a, and the rising edge detection circuit 302 and the falling edge detection circuit 303
Then, the edge pulse signals 3b and 3c are generated, synthesized by the OR gate 304, and converted into the edge signal 3d, and then input to the delay circuit 305 and the gate signal generation circuit 306.

The gate signal generation circuit 306 generates a gate signal 3f for thinning out pulses of the VCO oscillation circuit, and outputs a gate signal 3g from the VCO circuit 309 to a signal 3h which is pulsed by the edge detection circuit 310. The mask process is performed by the AND gate 311.

The delay circuit 305 is a circuit for causing an input edge signal to come near the center of the gate width of the gate signal.
e is input to the phase detection circuit 307 together with the VCO gate signal 3i which is the output of the AND gate 311. The output of the phase detection circuit 307 is fed back as a frequency control voltage of the VCO circuit 309 through the filter 308.

According to the present invention, as shown in FIG. 4, the rising edge and the falling edge of the PSK-modulated signal 3a are input, and the signal of the VCO oscillation circuit oscillating at four times the input frequency is VCO As shown by the broken line pulse of the gate signal 3i, a PLL oscillation circuit is formed by thinning out.

FIG. 5 is a diagram showing how a received waveform is distorted immediately after a phase change point due to electromagnetic coupling of a PSK modulated signal by a coil. PSK modulated received signal 7
In a, at the phase modulation point, a signal shown by a thin line causes distortion as shown by a waveform shown by a thick line as shown in (A) and (B).
In the above-described distortion waveform, the reference signal of the PLL circuit is shifted as shown by t1 and t2 in the rising and falling edge signals 3b and 3c. When the rising and falling edge signals are combined by an OR circuit, the waveforms A, 3D, and 3I
In phase A and phase B, a phase difference is generated between the PLL reference pulse 3d and the VCO pulse 3i, which causes an error in the phase difference detection result of the PLL circuit, and the frequency of the oscillation circuit is unlocked or unstable. This results in frequency fluctuation (jitter) of the clock generation circuit.

The above unstable element is a case where both rising and falling edges of the PSK signal are used.
The diagram shown in FIG. 5 for the PLL reference pulse 3d-1 and the VCO pulse 3i-1 is a time chart when only the rising edge of the PSK signal is used. This method used both edges
Compared with the PLL circuit, as shown in the waveform diagram C, the fluctuation of the phase difference from the reference pulse is 1/2 that of when both edges are used.
Therefore, a more stable PLL clock generation circuit can be provided.

FIG. 6 is a diagram showing a second embodiment of the present invention, in which only the rising edge signal of the input PSK modulation signal is used as a reference signal for phase detection.
FIG. 3 is a diagram illustrating a clock generation circuit. The PSK signal converted into a digital signal by the binarization circuit 301 generates an edge pulse signal 3b by a rising edge detection circuit 302, and is input to a delay circuit 305 and a gate signal generation circuit 306. This circuit is
This is almost the same as the circuit of FIG. 3, but is an example of a clock generation circuit that uses only the rising edge signal of the PSK modulation signal and inputs the phase detection circuit to configure a PLL circuit. Hereinafter, the operation of this circuit is the same as the description of FIG.

As described above, the clock generation circuit according to the present invention provides a PSK-modulated stable clock signal synchronized with an input signal in a clock generation method using a PLL circuit for a contactless IC card. Can be.

[0038]

According to the present invention, a stable PLL circuit of the present invention can be realized by thinning out the VCO pulse at the phase change point even for an input signal modulated with PSK, and at the same time, the electromagnetic coupling of the signal is achieved. Frequency fluctuation (jitter) even with changes in pulse width caused by input signal distortion due to
It is possible to realize a clock generation circuit using the PLL circuit of the present invention with a small number of clocks.

[Brief description of the drawings]

FIG. 1 is a diagram showing a reader / writer of a non-contact IC card and an IC card.

FIG. 2 is a diagram showing a configuration of a wireless integrated circuit mounted in an IC card.

FIG. 3 is a diagram showing a clock generation circuit of the present invention.

FIG. 4 is a first time chart illustrating the operation of the present invention.

FIG. 5 is a second time chart illustrating the operation of the present invention.

FIG. 6 is a diagram showing a second embodiment of the present invention.

FIG. 7 is a diagram showing an example of a non-contact data communication method.

FIG. 8 is a diagram showing one method of generating a clock signal from a PSK signal.

[Explanation of symbols]

1 ... power supply circuit, 2 ... transmission and reception control circuit, 3 ... CPU, 4 ... memory, 5 ... read / write control circuit, 6 ... reader / writer side transmission / reception coil, 7 ... card side transmission / reception coil, 10 ... IC card, 11 ... rectification Circuit, 12: Power supply circuit, 21: Data receiving circuit
22 demodulation circuit, 23 modulation circuit, 24 data transmission circuit, 2
5, 26 driver, 27, 28 capacitor, 301 binarization circuit, 302 rising edge detection circuit, 303 falling edge detection circuit, 304 OR gate, 305 delay circuit, 30
6 gate signal generation circuit, 307 phase detection circuit, 308 filter, 309 VCO oscillation circuit, 310 edge detection circuit, 311
... AND gate, 320 ... clock output, 3a ... PSK modulation signal, 3b ... rising edge signal, 3c ... falling edge signal, 3d ... edge signal, 3e ... delay signal, 3f ... gate signal, 3g ... VCO pulse, 3h ... VCO edge signal, 3I… VCO gate signal, 7a… PSK modulation received signal.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI H03L 7/14 H04B 1/59 H04B 1/59 5/02 5/02 G06K 19/00 H H04L 27/233 H04L 27/22 G (72) Inventor Masato Suzuki 1-88 Ushitora, Ibaraki-shi, Osaka Hitachi Maxell, Ltd.

Claims (4)

[Claims] An antenna coil means for transmitting power by electromagnetic coupling and transmitting / receiving information, a means for detecting a leading edge (rising) of a received signal from a signal received by the antenna coil means, Means for detecting a falling edge, means for performing an OR operation on the rising and falling signal, means for delaying the OR signal, means for generating a gate signal for phase detection from the OR signal, Means for performing an AND operation with the VCO signal by the gate signal;
Means for comparing the phase of the coil input signal with the phase of the gated signal; comparing the phase of the delayed signal of the rising and falling signals with the phase of the gated signal to thereby provide a PLL circuit; A non-contact IC card, comprising: a microprocessor that operates on a clock signal generated from a circuit. 2. The non-contact IC card according to claim 1, wherein the antenna coil means is formed of a printed pattern such as a conductive paste, and the line width of the pattern is partially changed. 3. A contactless non-contact IC card which transmits power by electromagnetic coupling and transmits / receives information between an antenna coil on a reader / writer side and an antenna coil on an IC card side, wherein the antenna coil means and the clock generating means are provided. A clock generation method for an IC card, comprising a communication control means having a memory and a microprocessor (MPU) means having a memory, and a phase comparison method (PLL) using a voltage controlled oscillation (VCO) means.
In the clock generation circuit, a means for generating a clock for the MPU includes a means for detecting a leading edge (rising) of the received signal from a signal received by the antenna coil means, and a means for detecting a trailing edge (falling) of the received signal. Detecting means, means for performing a logical sum processing of the rising and falling signals, means for delaying the logical sum signal, means for generating a gate signal for phase detection from the logical sum signal, Means for performing a logical product of the VCO signal and means for comparing the phase of the coil input signal with the gated VCO signal are provided, and the delay signal of the rising and falling signals and the gate of the VCO (logical product) A non-contact IC card having a clock generation method in which a PLL circuit is configured by comparing a phase with a signal. 4. A clock generation method according to claim 3, wherein one of a rising signal and a falling signal of the signal received by said antenna coil means is input to a phase comparison means, so that a clock is generated. A non-contact IC card that is generated.