JPH10214950A - Semiconductor integrated circuit device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To drop an operating voltage by a method wherein a sidewall floating gate part connecting electrically with a floating gate is provided via an insulating film on a side surface of a control gate of a semiconductor integrated circuit device having a nonvolatile memory cell. SOLUTION: A sidewall floating gate part 3Mfg3 (hereinafter, called 3M: a memory cell omitted) is provided on a side surface of cg, and is connected electrically to a floating gate fg, but is insulated from a control gate cg by a sidewall interlayer insulation film i12 therebetween. As the entire capacitance between the floating gate fg and control gate cg is constituted by the sum of capacitance between an upper surface of an upper floating gate part fg2 and a lower surface of the control gate cg; and capacitance between the upper surface of the upper floating gate part fg2 and the lower surface of the control gate cg, it becomes possible to increase the entire capacitance between the floating gate fg and control gate cg. For this reason, it is possible to improve a capacity coupling ratio in a memory cell 3M and to reduce a rewrite voltage in a word line.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a manufacturing technique thereof, and more particularly to a MIS-FET (Metal Insulator Semiconductor Device) having a two-layer gate structure.
The present invention relates to a semiconductor integrated circuit device having a batch-erasable nonvolatile memory provided with a memory cell composed of a d Effect Transistor) and a technique effective when applied to a method of manufacturing the same.

[0002]

2. Description of the Related Art An electrically writable and erasable non-volatile memory is widely used in various products which require a memory because it can rewrite information even when it is incorporated on a wiring board and is easy to use. It is used.

[0003] In particular, an electrically erased EEPROM (El
An ectrically erasable programmable ROM (hereinafter also referred to as a flash memory (EEPROM)) has a memory cell size of a DRAM (Dynamic Random Access Memory).
It can be smaller than y), and there is great expectation for alternative uses of memory cards and magnetic disks.

This flash memory (EEPROM)
Is to collectively electrically erase data of all memory cells formed on the semiconductor chip or collectively collect data of a group of memory cells among a plurality of memory cells formed on the semiconductor chip. This is a nonvolatile memory having a function of electrically erasing the data.

[0005] For such a batch erase type EEPROM, for example, IEE in 1980,
International, Solid-State, Circuits, Conference (IEEE INTERNATIO)
NAL SOLID-STATE CIRCUITS
CONFERENCE) pages 152-153, 1987.
IEE, International, Solid-State, Circuits, Conference (IE)
EE International SOLID-ST
ATE CIRCUITS CONFERENCE), pages 76-77, or IEE, Journal, Ob, Solid-State, Circuits, 23rd.
Vol. 5, No. 5 (1988), pp. 1157 to 1163 (IEEE, J. SOLID-STATE CIRC)
UITS, vol. 23 (1988) pp. 1157-
1163) or JP-A-7-176705.

[0006] Among these flash memories (EEPROMs), the demand for a 1-bit / 1-MOS-FET structure is rapidly increasing because the degree of integration can be higher than that of a 1-bit / 2-MOS-FET structure.

In the 1-bit / 1-MOS.FET structure, one memory cell is formed by, for example, one MOS transistor having a two-layer gate structure.
The MOS-FET of the two-layer gate structure is configured by providing a floating gate on a semiconductor substrate via a gate insulating film and stacking a control gate on the floating gate via an insulating film. ing. Then, by injecting electrons into the floating gate or emitting electrons from the floating gate, "1 (High)" or "0 (Low)" level data is stored.

The injection of the electrons is performed by channel hot electron injection. There are cases where the injection of electrons is referred to as writing, and cases where the injection of electrons is referred to as erasing. In either case, writing is usually performed in byte units and erasing is performed in chip units or block units.

According to the study of the present inventor, in this MOSFET having a two-layer gate structure, the capacitance between the floating gate and the control gate is formed by using the upper surface of the floating gate and the lower surface of the control gate. .

[0010]

In a MOS-FET having a two-layer gate structure, the potential of the floating gate is determined by the capacitance coupling ratio with the control gate. For example, if the capacitance between the floating gate and the substrate is C1, the capacitance between the floating gate and the control gate is C2, the potential of the control gate is VCG, and the potential of the substrate is 0V, the potential V of the floating gate
FG is represented by (C2 / (C1 + C2)) × VCG. Therefore, the larger the capacitance C2 between the floating gate and the control gate, the more the operation at the lower control gate potential VCG becomes possible.

However, in a MOS-FET having a two-layer gate structure in which a capacitance C2 between the floating gate and the control gate is formed using the upper surface of the floating gate and the lower surface of the control gate, the capacitance C2 between the floating gate and the control gate is reduced. There is a limit on the size of the capacitance C2 between the floating gates, and a new device is required to reduce the operating voltage by increasing the capacitance C2 between the floating gate and the control gate without increasing the area of the memory cell. The inventor has found that there is.

An object of the present invention is to provide a MIS having a two-layer gate structure.
An object of the present invention is to provide a technique capable of lowering an operating voltage in a semiconductor integrated circuit device having a nonvolatile memory including an FET.

Another object of the present invention is to reduce the operating voltage of a semiconductor integrated circuit device having a non-volatile memory provided with a MIS-FET having a two-layer gate structure without increasing the area of the memory cell. To provide technology.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0015]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

A semiconductor integrated circuit device according to the present invention has a plurality of nonvolatile memory cells each composed of a MIS transistor having a two-layer gate structure in which a control gate is provided on a floating gate via an insulating film. A device,
A side wall floating gate portion electrically connected to the floating gate is provided on a side surface of the control gate via an insulating film.

Further, the semiconductor integrated circuit device of the present invention comprises a control gate provided on a floating gate via an insulating film.
A semiconductor integrated circuit device having a plurality of nonvolatile memory cells each formed of a MIS transistor having a layer gate structure, wherein a sidewall control gate portion electrically connected to the control gate is insulated on a side surface of the floating gate. It is provided via a film.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the drawings. (Note that components having the same functions in all drawings for describing the embodiments are denoted by the same reference numerals.) , And the repeated explanation is omitted).

(Embodiment 1) FIG. 1 is a plan view of a main part of a semiconductor integrated circuit device according to an embodiment of the present invention, FIG. 2 is a sectional view taken along the line II-II of FIG. 1, and FIG. 4 is a cross-sectional view taken along the line IV-IV of FIG. 1, and FIGS. 5 to 29 are explanatory views for explaining a manufacturing process of the semiconductor integrated circuit device of FIG. In the plan view used in the first embodiment, predetermined hatching is added to make the drawings easy to see.

In the first embodiment, a case where the present invention is applied to, for example, an AND type flash memory (EEPROM) will be described. This AND type flash memory (EE
FIG. 1 is a plan view of a main part of a memory cell of a PROM. FIGS. 2 to 4 are cross-sectional views of each part of FIG.

The semiconductor substrate 1 is made of, for example, a single crystal of p-type silicon (Si).
Are formed. The isolation insulating film 2 includes a central thick film portion 2a and a peripheral thin film portion 2b.
It has a function of electrically isolating the memory cell 3M formed thereon. Both the thick film portion 2a and the thin film portion 2b
For example, it is made of silicon dioxide (SiO ₂ ), and is formed in, for example, two steps as described later.

The memory cell 3M is an MO having a two-layer gate structure.
Based on S-FET, a pair of semiconductor regions 3Ml,
3Ml, a gate insulating film 3Mi, a floating gate 3Mfg, an interlayer insulating film 3Mil, and a control gate 3Mcg.

The pair of semiconductor regions 3Ml, 3Ml are regions for forming a source and a drain, and are formed above the semiconductor substrate 1 so as to be separated from each other. This semiconductor region 3
Ml and 3Ml contain, for example, arsenic (As) as an n-type impurity. The gate insulating film 3Mi is made of, for example, silicon dioxide (SiO ₂ ) and is formed on the semiconductor substrate 1.

The floating gate 3Mfg is connected to the lower floating gate 3
Mfg1, an upper floating gate 3Mfg2, and a side wall floating gate 3Mfg3. These lower floating gates 3Mfg
1. Upper floating gate 3Mfg2 and sidewall floating gate 3M
fg3 is made of, for example, low-resistance polysilicon.

The lower floating gate 3Mfg1 is formed on the gate insulating film 3Mi. The upper floating gate 3Mfg2
In FIG. 2, it is formed wider than the lower floating gate 3Mfg1, and is stacked on the lower floating gate 3Mfg1 and is electrically connected to the lower floating gate 3Mfg1.

However, between the side surface of the lower floating gate 3Mfg1 and the upper floating gate 3Mfg2, the lower floating gate 3
It is physically separated by a thin insulating film 4 and a side wall 5 (see FIG. 2) formed on the side surface of Mfg1.

Therefore, the cross section of the floating gate 3Mfg is
As shown in FIG. 2, it is T-shaped. This allows
The structure is such that the surface area of the floating gate 3Mfg can be increased and the capacitance between the floating gate 3Mfg and the control gate 3Mcg can be increased. The thin insulating film 4 and the side wall 5 are made of, for example, SiO ₂ .

As shown in FIG. 3, the side wall floating gate portion 3Mfg3 is provided on the side surface of the control gate 3Mcg. However, this side wall floating gate portion 3Mfg3 is
Is electrically connected to the control gate 3Mcg, but is insulated from the control gate 3Mcg by the interposition of the side wall interlayer insulating film 3Mil2.

In the first embodiment, the total capacitance between floating gate 3Mfg and control gate 3Mcg is equal to the upper surface of upper floating gate 3Mfg2 and control gate 3Mcg.
And the capacitance between the side wall floating gate portion 3Mfg3 and the side surface of the control gate 3Mcg.

As a result, the total capacitance between the floating gate 3Mfg and the control gate 3Mcg is increased by the upper floating gate 3Mfg2.
The total capacitance between the floating gate 3Mfg and the control gate 3Mcg can be increased as compared with a structure formed only by the capacitance between the upper surface of the floating gate 3Mcg and the lower surface of the control gate 3Mcg.

Therefore, the capacity coupling ratio in the memory cell 3M can be improved, so that the rewrite voltage on the word line (control gate 3Mcg) can be reduced. Therefore, the flash memory (EEPRO) can be used without increasing the size of the memory cell 3M.
The operation voltage of M) can be reduced.

The side wall floating gate portion 3Mfg3 is formed along the longitudinal side surface of the control gate 3Mcg. However, as shown in FIG. 4, the side wall floating gate portion 3Mf is formed on the side surface of the control gate 3Mcg on the isolation insulating film 2.
g3 is not formed, whereby the floating gate 3Mfg1 of the same word line (control gate 3Mcg) is electrically separated for each memory block.

The interlayer insulating film 3Mil1 is made of, for example, SiO ₂ , silicon nitride (Si ₃ N ₄ ), SiO ₂ and Si ₃ N ₄
Are formed by being sequentially deposited from the lower layer. The side wall interlayer insulating film 3Mil2 is made of, for example, SiO ₂ , Si ₃ N ₄ , S
iO ₂ and Si ₃ N ₄ is formed from the side surface of the control gate 3Mcg coated sequentially.

The control gate 3Mcg constitutes a part of a word line. For example, a silicide film such as tungsten silicide or molybdenum silicide is deposited on low-resistance polysilicon, and further, for example, Si
It is configured by depositing a cap insulating film made of O ₂ or the like. Note that such a memory cell 3M is covered with an interlayer insulating film 6a. The interlayer insulating film 6a is made of, for example, SiO ₂ .

Next, a method of manufacturing the semiconductor integrated circuit device according to the first embodiment will be described with reference to FIGS.

First, in the steps of FIGS. 5 to 7, after the well is formed, a thick film portion 2a of the isolation insulating film 2 is formed on the semiconductor substrate 1, and then the semiconductor substrate 1 surrounded by the thick film portion 2a is formed. A sacrificial insulating film 7 is formed on the main surface.

The thick film portion 2a of the isolation insulating film 2 is formed, for example, as follows. That is, after a pad insulating film made of SiO ₂ or the like and a non-oxidizing insulating film made of silicon nitride or the like are sequentially formed in the element formation region of the semiconductor substrate 1, the semiconductor substrate 1 is subjected to an oxidation treatment such as LOCOS oxidation. By performing this, the thick film portion 2a of the isolation insulating film 2 is formed on the semiconductor substrate 1 exposed from the non-oxidizing insulating film.

Next, in the steps of FIG. 8 to FIG.
A pair of semiconductor regions 3Ml and 3Ml and a lower floating gate 3Mfg1 of a memory cell are formed in an element formation region of the semiconductor substrate 1. That is, for example, the following is performed.

First, after removing the sacrificial insulating film 7 (see FIG. 6 and the like), the semiconductor substrate 1 is subjected to a thermal oxidation treatment or the like, as shown in FIG. 9 and FIG. A gate insulating film 3Mi made of, for example, SiO ₂ is formed thereon.

Subsequently, after a conductor film made of low-resistance polysilicon or the like is deposited on the semiconductor substrate 1 by a CVD method or the like, an insulating film made of, for example, silicon nitride or the like is deposited on the conductor film by a CVD method or the like. I do.

Thereafter, the conductive film and the insulating film are patterned by photolithography, dry etching, and the like, thereby forming the lower floating gate portion 3Mfg1 of the floating gate and the insulating film 8.

After this processing step, the lower floating gate 3Mfg1
The pattern of the insulating film 8 is formed so as to form the drain and the source of the transistor of the memory cell in a self-aligned manner.

After that, after opening and etching the semiconductor region 3Ml of the transistor of the memory cell, the semiconductor substrate 1 is subjected to a light oxidation treatment or the like, so that the lower floating gate portion 3Mfg1 on the main surface of the semiconductor substrate 1 is formed. And thin insulating films 4a and 4b are formed on the side surfaces of the insulating film 8 and the side surfaces of the insulating film 8.

Next, openings are respectively formed on the semiconductor regions 3Ml and 3Ml by using a photoresist film.
After ions are implanted into the upper portion of the semiconductor substrate 1 by an ion implantation method, a heat treatment is performed on the semiconductor substrate 1 so that a pair of semiconductor regions 3Ml,
Form 3 Ml. The semiconductor regions 3Ml, 3Ml are regions common to the transistors of each memory cell arranged in the direction in which the lower floating gate portion 3Mfg1 extends in this step (the vertical direction in FIG. 8).

Subsequently, on the semiconductor substrate 1, for example, SiO
After deposition by CVD method or the like insulating film made of _2, by total etch back the insulating film, is etched back, as shown in FIG. 11, the lower the floating gate 3
A sidewall 5 is formed on the side surface of Mfg1.

After that, the semiconductor substrate 1 is subjected to a thermal oxidation treatment to thereby form the semiconductor region 3 as shown in FIG.
On Ml and 3Ml, the thin film portions 2b of the isolation insulating film 2 are selectively formed on the left and right of the thick film portion 2a of the isolation insulating film 2. At this time, the side wall 5 functions as a stopper so that the end of the lower floating gate 3Mfg1 is not oxidized.

In the steps shown in FIGS. 8 to 12, the transistors for forming the memory cells in different blocks have the lower floating gate portion 3Mfg1 of the first layer electrically isolated. Transistors remain integrally formed, as shown in FIG.

Next, in the steps of FIGS. 13 to 15, the insulating film 8 made of silicon nitride or the like is entirely removed by immersing the semiconductor substrate 1 in hot phosphoric acid or the like. As a result, the lower floating gate 3Mfg1 and the side wall 5 remain.

Next, in the steps of FIGS. 16 to 18, after a conductor film made of, for example, low-resistance polysilicon is deposited on the semiconductor substrate 1 by a CVD method or the like, the conductor film is formed by photolithography and dry etching. The upper floating gate portion 3Mfg2 is formed by patterning using the method described above.

The upper floating gate portion 3Mfg2 is etched away on the thick film portion 2a of the isolation insulating film 2, thereby electrically separating the floating gate 3Mfg between the blocks.

The floating gate 3Mfg includes the lower floating gate 3Mfg1 and an upper floating gate 3Mfg2 formed on the lower gate 3Mfg1. The upper floating gate 3Mfg2 forms a pair of semiconductor regions 3Ml and 3Ml. It is formed in a T-shape to cover.

As described above, in different memory blocks, the floating gate 3 of the transistor for forming the memory cell is used.
Mfg is electrically isolated on the isolation insulating film 2,
In the same memory block, the floating gate 3Mfg of the transistor for the memory cell configuration is, as shown in FIG.
It remains integrally formed.

Next, in the steps of FIGS. 19 to 22, for example, the following is performed.

First, on the semiconductor substrate 1, for example, SiO ₂
/ Si ₃ N ₄ / SiO ₂ / Si ₃ N ₄ are sequentially deposited from the lower layer by a CVD method or the like, and then, for example, low-resistance polysilicon, tungsten silicide (WSi ₂ ) and SiO ₂ are formed on the interlayer insulating film 3Mil1 having the laminated structure. _A polycide film is formed by sequentially depositing _{2 and the} like in order from the lower layer by a CVD method or the like. The silicide is not limited to, for example, WSi ₂ but may be variously changed, for example, molybdenum silicide or the like.

Subsequently, the polycide film is patterned by a photolithography technique and a dry etching technique to form a control gate 3Mcg made of a polycide film. The control gate 3Mcg is formed in a band-like pattern extending in the left-right direction in FIG.

On the floating gate 3Mfg, an interlayer insulating film 3Mi
A control gate 3Mcg is formed via l1. However, in this step, the interlayer insulating film 3Mil is not patterned. In FIG. 19, the interlayer insulating film 3Mil is not shown for easy viewing. No interlayer insulating film is formed on the side surface of the floating gate 3Mfg.

Next, in the steps shown in FIGS. 23 to 25, for example, the following is performed.

First, the interlayer insulating film 3Mi is formed by self-alignment using the insulating film above the control gate 3Mcg as a mask.
Pattern l1.

Subsequently, on the semiconductor substrate 1, for example, SiO 2
_After depositing ₂ / Si ₃ N ₄ / SiO ₂ / Si ₃ N ₄ in order from the lower layer by a CVD method or the like, an interlayer insulating film 3Mil2 is formed on the side surface of the control gate 3Mcg by etch back over the entire surface.

Next, in the steps shown in FIGS. 26 to 28, for example, the following is performed.

First, for example, a low-resistance polysilicon film is deposited on the semiconductor substrate 1 by a CVD method or the like, and is then subjected to an entire surface etch-back process to obtain a structure shown in FIGS.
As shown in FIG. 7, a side wall floating gate portion 3Mfg3 is formed on the side surface of the control gate 3Mcg.

At this time, the lower floating gate portion 3Mfg1 and the upper floating gate portion 3Mf located between the control gates 3Mcg are simultaneously formed using the insulating film in the upper layer of the control gate 3Mcg as a mask.
g2 (see FIG. 24, etc.) is removed. At this time, the floating gates 3Mfg of different word lines are separated, but the floating gates 3Mfg of the same word line are connected via the side wall floating gate portion 3Mfg3.

Next, in the step shown in FIG. 29, for example, the following is performed. That is, first, a photoresist pattern 9a having the same size and the same shape as the upper floating gate portion 3Mfg2 is formed on the semiconductor substrate 1 by photolithography.

Subsequently, the side wall floating gate portion 3Mfg3 exposed from the photoresist pattern 9a is removed by isotropic etching or the like. Thus, floating gates of the same word line are separated for each block.

Thereafter, as shown in FIGS. 1 to 4, an interlayer insulating film 6 made of, for example, SiO _{2 is} formed on the semiconductor substrate 1.
a is formed by a CVD method or the like to cover the control gate 3Mcg.

According to the first embodiment, the following effects can be obtained.

(1) The capacitance between the floating gate 3Mfg and the floating gate 3Mfg of the memory cell 3M is also formed on the side surface of the word line (control gate 3Mcg).
Since the total capacitance with Mcg can be increased and the capacitance coupling ratio can be improved, the rewrite word line voltage can be reduced.

(2) According to the above (1), the voltage applied to the gate insulating film 3Mi of the transistor constituting the memory cell 3M can be reduced, so that the reliability of the memory cell 3M can be improved. Become.

(3) According to the above (1), the voltage applied to the peripheral circuit can be reduced, so that the reliability of the peripheral circuit can be improved.

(Embodiment 2) FIG. 30 is a plan view of a main part of a semiconductor integrated circuit device according to another embodiment of the present invention.
1 is a sectional view taken along the line XXXI-XXXI in FIG. 30, and FIG.
FIG. 33 is a sectional view taken along the line XXXII-XXXII, and FIG.
FIGS. 34 and 35 are cross-sectional views taken along the line XXXIII, and FIGS. 34 and 35 are explanatory views illustrating the manufacturing steps of the semiconductor integrated circuit device of FIG. In the plan view used in the second embodiment, predetermined hatching is added to make the drawings easy to see.

The second embodiment shown in FIGS.
As in the first embodiment, a case where the present invention is applied to, for example, an AND flash memory (EEPROM) will be described, and the structure is basically the same. The difference is in the following structure.

That is, in the second embodiment, as shown in FIGS. 30 to 33, the side wall control gate portion 3Mcg1 of the control gate 3Mcg is formed on the side surface of the floating gate 3Mfg via the side wall interlayer insulating film 3Mil3. I have.

The side wall control gate portion 3Mcg1 is made of, for example, low-resistance polysilicon, and is formed extending from the side surface of the control gate 3Mcg along the side surface of the floating gate 3Mfg while being electrically connected to the control gate 3Mcg. I have.

As a result, the total capacitance of the control gate 3Mcg and the floating gate 3Mfg is equal to the capacitance between the upper surface of the floating gate 3Mfg and the lower surface of the control gate 3Mfg and the floating gate 3Mfg.
g and the sum of the capacitance between the side wall and the sidewall control gate 3Mcg1.

Therefore, the capacitance between the control gate 3Mcg and the floating gate 3Mfg can be increased, and the capacitance coupling ratio of the memory cell 3M can be improved, so that the rewrite word line voltage can be reduced.

Next, a method of manufacturing the semiconductor integrated circuit device according to the second embodiment will be described with reference to FIGS.

First, also in the case of Embodiment 2, FIG.
25 are the same as those described in the first embodiment. Therefore, the description is omitted.

Subsequently, in Embodiment 2, FIG.
As shown in FIG. 4, the upper floating gate portion 3Mfg2 and the lower floating gate portion 3Mfg1 (see FIG. 24) are patterned by using the sidewall interlayer insulating film 3Mil2 made of silicon nitride or the like and the insulating film above the control gate 3Mcg as a mask. As a result, the floating gates 3Mfg of different word lines (control gates 3Mcg) are electrically separated.

Thereafter, the semiconductor substrate 1 is subjected to a thermal oxidation treatment to form a sidewall interlayer insulating film 3Mil3 made of, for example, SiO ₂ on the semiconductor substrate 1 and on the side surfaces of the upper floating gate portion 3Mfg2 and the lower floating gate portion 3Mfg1. To form At this time, the side of the word line (control gate 3Mcg)
Since it is covered with the side wall interlayer insulating film 3Mil2, it is not oxidized.

Next, the side wall interlayer insulating film 3Mil2 on the side surface of the control gate 3Mcg is removed by hot phosphoric acid or the like. At this time, the upper floating gate 3Mfg2 and the lower floating gate 3
The side wall interlayer insulating film 3Mil3 on the side surface of Mfg1 is made of, for example, SiO ₂
, So it is left without being removed.

Subsequently, a conductive film made of, for example, low-resistance polysilicon is deposited on the semiconductor substrate 1 by a CVD method or the like, and the conductive film is etched back.
As shown in FIGS. 32 and 33, the side wall control gate portion 3Mcg1 is formed.

Thereafter, for example, SiO 2 is formed on the semiconductor substrate 1.
_An interlayer insulating film 6a made of, for example,
The semiconductor integrated circuit device shown in FIG.

In the second embodiment, the following effects can be obtained.

(1) By forming a capacitance with the control gate 3Mcg also on the side surface of the floating gate 3Mfg, the total capacitance of the floating gate 3Mfg and the control gate 3Mcg of the memory cell 3M can be increased. Since the capacitance coupling ratio can be improved, the rewrite word line voltage can be reduced.

(2) According to the above (1), the voltage applied to the gate insulating film 3Mi of the transistor constituting the memory cell 3M can be reduced, so that the reliability of the memory cell 3M can be improved. Become.

(3) According to the above (1), the voltage applied to the peripheral circuit can be reduced, so that the reliability of the peripheral circuit can be improved.

(Embodiment 3) FIG. 36 is a main part plan view of a semiconductor integrated circuit device according to another embodiment of the present invention.
7 is a sectional view taken along line XXXVII-XXXVII in FIG. 36, and FIG.
FIG. 39 is a sectional view taken along the line XXXVIII-XXXVIII of FIG.
FIG. 40 to FIG. 53 are cross-sectional views taken along the line XXXIX-XXXIX. FIGS. It should be noted that the plan views used in the third embodiment are also given predetermined hatchings in order to make the drawings easier to see.

In the third embodiment, a case where the present invention is applied to, for example, a NAND flash memory (EEPROM) will be described. FIG. 36 is a plan view of a main part of a memory cell of the NAND flash memory (EEPROM). FIGS. 37 to 39 are cross-sectional views of each part of FIG.

The semiconductor substrate 1 is made of, for example, a single crystal of p-type silicon (Si), and an isolation insulating film 2 made of, for example, silicon dioxide (SiO ₂ ) is formed thereon.

The memory cell 3M has an MO of a two-layer gate structure.
Based on S-FET, a pair of semiconductor regions 3Ml,
3Ml, a gate insulating film 3Mi, a floating gate 3Mfg, an interlayer insulating film 3Mil, and a control gate 3Mcg.

The pair of semiconductor regions 3Ml, 3Ml are regions for forming a source and a drain, and are formed above the semiconductor substrate 1 so as to be separated from each other. This semiconductor region 3
Ml and 3Ml contain, for example, arsenic (As) as an n-type impurity. The gate insulating film 3Mi is made of, for example, SiO ₂ and is formed on the semiconductor substrate 1.

The floating gate 3Mfg is made of, for example, low-resistance polysilicon and has a sidewall floating gate portion 3Mfg3. As shown in FIG. 38, the side wall floating gate portion 3Mfg3
It is provided on the side surface of the control gate 3Mfg.

However, this side wall floating gate portion 3Mfg3 is
Although it is electrically connected to the floating gate 3Mfg, it is insulated from the control gate 3Mcg with a side wall interlayer insulating film 3Mil2 interposed therebetween.

In the third embodiment, the total capacitance between the floating gate 3Mfg and the control gate 3Mcg is equal to the capacitance between the upper surface of the floating gate 3Mfg and the lower surface of the control gate 3Mcg, and the side wall floating. It is constituted by the sum of the capacitance between the gate portion 3Mfg3 and the side surface of the control gate 3Mcg.

Thus, compared to a structure in which the entire capacitance between the floating gate 3Mfg and the control gate 3Mcg is formed only by the capacitance between the upper surface of the floating gate portion 3Mfg and the lower surface of the control gate 3Mcg, 3Mfg and control gate 3Mc
g can be increased.

As a result, the capacitance coupling ratio in the memory cell 3M can be improved, and the rewrite voltage on the word line (control gate 3Mcg) can be reduced. Therefore, the flash memory (EEPRO) can be used without increasing the size of the memory cell 3M.
The operation voltage of M) can be reduced.

The above-mentioned side wall floating gate portion 3Mfg3 is formed along the longitudinal side surface of the control gate 3Mcg. However, as shown in FIG. 39, on the isolation insulating film 2, the side wall floating gate portion 3 is formed on the side surface of the control gate 3Mcg.
Mfg3 is not formed, whereby the floating gate 3Mfg of the same word line (control gate 3Mcg) is electrically separated for each memory block.

The interlayer insulating film 3Mil1 is made of, for example, SiO ₂ , silicon nitride (Si ₃ N ₄ ), SiO ₂ and Si ₃ N ₄
Are formed by being sequentially deposited from the lower layer. The side wall interlayer insulating film 3Mil2 is made of, for example, SiO ₂ , Si ₃ N ₄ , S
iO ₂ and Si ₃ N ₄ is formed from the side surface of the control gate 3Mcg coated sequentially.

The control gate 3Mcg constitutes a part of a word line. For example, a silicide film such as tungsten silicide or molybdenum silicide is deposited on low resistance polysilicon, and further, for example, Si
It is configured by depositing a cap insulating film made of O ₂ or the like. Note that such a memory cell 3M is covered with an interlayer insulating film 6a. The interlayer insulating film 6a is made of, for example, SiO ₂ .

Next, a method of manufacturing the semiconductor integrated circuit device according to the third embodiment will be described with reference to FIGS.

First, in the steps of FIGS. 40 to 42,
After the isolation insulating film 2 is formed on the semiconductor substrate 1, a sacrificial insulating film 7 is formed on the main surface of the semiconductor substrate 1 surrounded by the isolation insulating film 2.

The isolation insulating film 2 is formed, for example, as follows. That is, after a well is formed, a pad insulating film made of SiO ₂ or the like and a non-oxidizing insulating film made of silicon nitride or the like are sequentially formed in the element formation region of the semiconductor substrate 1,
By subjecting the semiconductor substrate 1 to an oxidation treatment such as LOCOS oxidation or the like, an isolation insulating film 2 is formed on the semiconductor substrate 1 exposed from the non-oxidizing insulating film.

Next, in the steps of FIGS. 43 to 45, for example, the following is performed. First, after removing the above-described sacrificial insulating film 7 (FIG. 42 and the like), the semiconductor substrate 1 is subjected to a thermal oxidation treatment or the like, so that the gate insulating film is formed on the semiconductor substrate 1 as shown in FIGS. The film 3Mi is formed.

Subsequently, after a conductive film made of low-resistance polysilicon or the like is deposited on the semiconductor substrate 1 by a CVD method or the like, the conductive film is patterned by a photolithography technique, a dry etching technique, or the like.
A floating gate 3Mfg is formed. The pattern of the floating gate 3Mfg is formed as a wide pattern on the isolation insulating film 2.

Here, the floating gates 3Mfg of the memory transistors of the different memory blocks are electrically isolated, but the memory transistors of the same memory block are:
It remains integrally formed.

Next, in the steps of FIGS. 46 to 48, for example, the following is performed.

First, on the semiconductor substrate 1, for example, SiO ₂
/ Si ₃ N ₄ / SiO ₂ / Si ₃ N ₄ are sequentially deposited from the lower layer by a CVD method or the like, and then, for example, low-resistance polysilicon, tungsten silicide (WSi ₂ ) and SiO ₂ are formed on the interlayer insulating film 3Mil1 having the laminated structure. _A polycide film is formed by sequentially depositing _{2 and the} like in order from the lower layer by a CVD method or the like. The silicide is not limited to, for example, WSi ₂ but may be variously changed, and may be, for example, molybdenum silicide.

Subsequently, the control gate 3Mcg made of a polycide film is formed by patterning the polycide film by a photolithography technique, a dry etching technique or the like. The control gate 3Mcg is formed in a band-like pattern extending in the left-right direction in FIG.

On the floating gate 3Mfg, an interlayer insulating film 3Mi
A control gate 3Mcg is formed via l1. However, in this step, the interlayer insulating film 3Mil is not patterned. Note that FIG. 46 does not show the interlayer insulating film 3Mil for easy viewing. No interlayer insulating film is formed on the side surface of the floating gate 3Mfg.

Next, in the steps shown in FIGS. 49 and 50, first, the interlayer insulating film 3Mil1 is formed by self-alignment using the insulating film above the control gate 3Mcg as a mask.
Is patterned.

Subsequently, on the semiconductor substrate 1, for example, SiO 2
_After depositing ₂ / Si ₃ N ₄ / SiO ₂ / Si ₃ N ₄ in order from the lower layer by the CVD method or the like, an interlayer insulating film 3Mil2 is formed on the side surface of the control gate 3Mcg by etch back over the entire surface.

Next, in the steps shown in FIGS. 51 and 52, for example, the following is performed.

First, after depositing, for example, a low-resistance polysilicon film on the semiconductor substrate 1 by a CVD method or the like, the entire surface is etched back to form a side wall floating gate portion 3Mfg3 on the side surface of the control gate 3Mcg.

At this time, at the same time, the floating gate 3Mfg located between the control gates 3Mcg is removed using the insulating film in the upper layer of the control gate 3Mcg as a mask. At this time, the floating gates 3Mfg of different word lines are separated, but the floating gates 3Mfg of the same word line are connected via the side wall floating gate portion 3Mfg3.

Subsequently, for example, A
After implanting an n-type impurity such as s by an ion implantation method or the like, the semiconductor substrate 1 is subjected to a heat treatment to form a semiconductor region 3Ml. This semiconductor region 3Ml
Are regions common to transistors in the same memory block.

Next, in the step shown in FIG. 53, for example, the following is performed. That is, first, a photoresist pattern 9a having the same size and the same shape as the upper floating gate portion 3Mfg2 is formed on the semiconductor substrate 1 by photolithography.

Subsequently, the side wall floating gate 3Mfg3 exposed from the photoresist pattern 9a is removed by isotropic etching or the like. Thus, floating gates of the same word line are separated for each block.

Then, as shown in FIGS. 37 to 39,
On a semiconductor substrate 1, an interlayer insulating film 6a made of, for example, SiO ₂ is formed by a CVD method or the like, and a control gate 3Mcg is formed.
Is coated.

According to the third embodiment, the following effects can be obtained.

(1) By forming a capacitance with the floating gate 3Mfg also on the side of the word line (control gate 3Mcg), the floating gate 3Mfg of the memory cell 3M and the control gate 3Mfg are formed.
Since the total capacitance with Mcg can be increased and the capacitance coupling ratio can be improved, the rewrite word line voltage can be reduced.

(2) According to the above (1), the voltage applied to the gate insulating film 3Mi of the transistor constituting the memory cell 3M can be reduced, so that the reliability of the memory cell 3M can be improved. Become.

(3) According to the above (1), the voltage applied to the peripheral circuit can be reduced, so that the reliability of the peripheral circuit can be improved.

(Embodiment 4) FIG. 54 is a plan view of a main part of a semiconductor integrated circuit device according to another embodiment of the present invention.
5 is a sectional view taken along the line XXXXXV-XXXXXV in FIG. 54, and FIG.
FIG. 57 is a sectional view taken along line XXXXXVI-XXXXXVI of FIG.
FIGS. 58 and 59 are cross-sectional views taken along the line XXXXXVII-XXXXXVII, and are explanatory views for explaining the manufacturing steps of the semiconductor integrated circuit device of FIG. It should be noted that the plan view used in the fourth embodiment is also given predetermined hatching to make the drawing easier to see.

The fourth embodiment shown in FIGS.
As in the third embodiment, the case where the present invention is applied to, for example, a NAND flash memory (EEPROM) will be described, and the structure is basically the same as that of the third embodiment. The difference is in the following structure.

That is, in the fourth embodiment, as shown in FIG. 56, the side wall control gate portion 3Mcg1 is formed on the side surface of the floating gate 3Mfg via the side wall interlayer insulating film 3Mil3.

The side wall control gate portion 3Mcg1 is made of, for example, low-resistance polysilicon and is formed so as to extend from the side surface of the control gate 3Mcg along the side surface of the floating gate 3Mfg while being electrically connected to the control gate 3Mcg. I have.

As a result, the total capacitance of the control gate 3Mcg and the floating gate 3Mfg is equal to the capacitance between the upper surface of the floating gate 3Mfg and the lower surface of the control gate 3Mg.
g and the sum of the capacitance between the side wall and the sidewall control gate 3Mcg1.

Therefore, the capacitance between the control gate 3Mcg and the floating gate 3Mfg can be increased, and the capacitance coupling ratio of the memory cell 3M can be improved, so that the rewrite word line voltage can be reduced.

Next, a method of manufacturing the semiconductor integrated circuit device according to the fourth embodiment will be described with reference to FIGS.

First, also in the fourth embodiment, since the manufacturing steps shown in FIGS. 40 to 50 are the same as those described in the third embodiment, description thereof will be omitted.

Subsequently, in Embodiment 4, FIG.
As shown in FIG. 8, the floating gate 3Mfg is patterned using the sidewall interlayer insulating film 3Mil2 made of silicon nitride or the like and the insulating film above the control gate 3Mcg as a mask. Thereby, the floating gates 3Mfg of different word lines are electrically separated.

Thereafter, the semiconductor substrate 1 is subjected to a thermal oxidation treatment, so that the semiconductor substrate 1 and the floating gate 3
On the side surface of Mfg, a side wall interlayer insulating film 3Mil3 made of, for example, SiO ₂ or the like is formed. At this time, the side surface of the word line is not oxidized because the side wall interlayer insulating film 3Mil2 is formed.

Next, the side wall interlayer insulating film 3Mil2 on the side surface of the control gate 3Mcg is removed by hot phosphoric acid or the like. At this time, the side wall interlayer insulating film 3Mil3 on the side surface of the floating gate 3Mfg
Is left without being removed because it is formed of, for example, SiO ₂ .

Subsequently, a conductive film made of, for example, low-resistance polysilicon or the like is deposited on the semiconductor substrate 1 by a CVD method or the like, and the conductive film is etched back.
As shown in FIGS. 56 and 57, the side wall control gate 3Mcg1 is formed.

After that, for example, SiO 2 is formed on the semiconductor substrate 1.
And an interlayer insulating film 6a consisting of _two equal, FIG. 54 FIG 5
The semiconductor integrated circuit device shown in FIG.

In the fourth embodiment, the following effects can be obtained.

(1) By forming the capacitance with the control gate 3Mcg also on the side surface of the floating gate 3Mfg, the total capacitance of the floating gate 3Mfg and the control gate 3Mcg of the memory cell 3M can be increased. Since the capacitance coupling ratio can be improved, the rewrite word line voltage can be reduced.

(2) According to the above (1), the voltage applied to the gate insulating film 3Mi of the transistor constituting the memory cell 3M can be reduced, so that the reliability of the memory cell 3M can be improved. Become.

(3) According to the above (1), the voltage applied to the peripheral circuit can be reduced, so that the reliability of the peripheral circuit can be improved.

As described above, the invention made by the inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above-described first to fourth embodiments, and does not depart from the gist of the invention. It goes without saying that various changes can be made.

For example, in the above embodiment, AND
And NAND flash memories (EEPRO
M), the present invention is not limited to this, but can be modified in various ways. For example, a so-called DINOR type flash memory in which NOR type or NOR type bit lines are hierarchized into main and sub layers (EEP
ROM).

The structure of the two-layer gate portion of the memory cell is not limited to the first to fourth embodiments but can be variously changed. For example, a structure as shown in FIG. 60 or 61 may be used. .

In FIG. 60, the structure is such that the periphery of the control gate 3Mcg is surrounded by the floating gate 3Mfg via the interlayer insulating film 3Mil.

In FIG. 61, the floating gate 3Mf
A side wall control gate portion 3Mcg1 extending from the control gate 3Mcg is provided on the side surface of g. This side wall control gate 3Mcg1
Is formed relatively thinner than in the above-described embodiment, and its outer periphery is formed of a side wall 1 made of an insulating film.
0.

The constituent materials and forming method of the floating gate, the control gate and the interlayer insulating film formed between the gates are not limited to those of the first to fourth embodiments, but can be variously changed.

[0146]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

(1) According to the semiconductor integrated circuit device of the present invention, the side wall floating gate portion electrically connected to the floating gate is provided on the side surface of the control gate via the insulating film, so that the memory cell Can increase the total capacitance of the floating gate and the control gate, and can improve the capacitance coupling ratio, without increasing the area of the memory cell.
The operating voltage can be reduced.

(2) According to the semiconductor integrated circuit device of the present invention, the side wall control gate portion electrically connected to the control gate is provided on the side surface of the floating gate via the insulating film, so that the memory cell Can increase the total capacitance of the floating gate and the control gate, and can improve the capacitance coupling ratio, without increasing the area of the memory cell.
The operating voltage can be reduced.

[Brief description of the drawings]

FIG. 1 is a plan view of a main part of a semiconductor integrated circuit device according to an embodiment of the present invention;

FIG. 2 is a sectional view taken along line II-II of FIG.

FIG. 3 is a sectional view taken along line III-III in FIG. 1;

FIG. 4 is a sectional view taken along line IV-IV of FIG.

FIG. 5 is an explanatory diagram illustrating a manufacturing process of the semiconductor integrated circuit device in FIG. 1;

FIG. 6 is an explanatory diagram illustrating a manufacturing process of the semiconductor integrated circuit device in FIG. 1;

FIG. 7 is an explanatory diagram for describing a manufacturing process of the semiconductor integrated circuit device in FIG. 1;

FIG. 8 is an explanatory diagram illustrating a manufacturing process of the semiconductor integrated circuit device in FIG. 1;

FIG. 9 is an explanatory diagram for explaining a manufacturing process of the semiconductor integrated circuit device in FIG. 1;

FIG. 10 is an explanatory diagram for illustrating a manufacturing process of the semiconductor integrated circuit device in FIG. 1;

FIG. 11 is an explanatory diagram for illustrating a manufacturing process of the semiconductor integrated circuit device in FIG. 1;

FIG. 12 is an illustrative diagram for describing a manufacturing process of the semiconductor integrated circuit device in FIG. 1;

FIG. 13 is an explanatory diagram for illustrating a manufacturing process of the semiconductor integrated circuit device in FIG. 1;

FIG. 14 is an explanatory diagram for describing a manufacturing process of the semiconductor integrated circuit device in FIG. 1;

FIG. 15 is an explanatory diagram illustrating a manufacturing process of the semiconductor integrated circuit device in FIG. 1;

FIG. 16 is an explanatory diagram illustrating a manufacturing process of the semiconductor integrated circuit device in FIG. 1;

FIG. 17 is an explanatory diagram for illustrating the manufacturing process of the semiconductor integrated circuit device in FIG. 1;

FIG. 18 is an explanatory diagram illustrating a manufacturing process of the semiconductor integrated circuit device in FIG. 1;

FIG. 19 is an explanatory diagram for illustrating a manufacturing process of the semiconductor integrated circuit device in FIG. 1;

FIG. 20 is an explanatory diagram illustrating a manufacturing process of the semiconductor integrated circuit device in FIG. 1;

FIG. 21 is an explanatory diagram for illustrating a manufacturing process of the semiconductor integrated circuit device in FIG. 1;

FIG. 22 is an explanatory diagram illustrating a manufacturing process of the semiconductor integrated circuit device in FIG. 1;

FIG. 23 is an explanatory diagram illustrating a manufacturing step of the semiconductor integrated circuit device in FIG. 1;

FIG. 24 is an explanatory diagram for illustrating a manufacturing process of the semiconductor integrated circuit device in FIG. 1;

FIG. 25 is an explanatory diagram illustrating a manufacturing step of the semiconductor integrated circuit device in FIG. 1;

FIG. 26 is an explanatory diagram for illustrating the manufacturing process of the semiconductor integrated circuit device in FIG. 1;

FIG. 27 is an explanatory diagram illustrating a manufacturing process of the semiconductor integrated circuit device in FIG. 1;

FIG. 28 is an explanatory diagram illustrating a manufacturing step of the semiconductor integrated circuit device in FIG. 1;

FIG. 29 is an explanatory diagram illustrating a manufacturing step of the semiconductor integrated circuit device in FIG. 1;

FIG. 30 is a plan view of relevant parts of a semiconductor integrated circuit device according to another embodiment of the present invention;

FIG. 31 is a sectional view taken along line XXXI-XXXI of FIG. 30;

FIG. 32 is a sectional view taken along line XXXII-XXXII of FIG. 30;

FIG. 33 is a sectional view taken along line XXXIII-XXXIII in FIG. 30;

FIG. 34 is an illustrative diagram for describing the manufacturing process of the semiconductor integrated circuit device in FIG. 30;

FIG. 35 is an explanatory diagram for illustrating the manufacturing process of the semiconductor integrated circuit device in FIG. 30;

FIG. 36 is a plan view of relevant parts of a semiconductor integrated circuit device according to another embodiment of the present invention;

FIG. 37 is a sectional view taken along line XXXVII-XXXVII in FIG. 36.

FIG. 38 is a sectional view taken along line XXXVIII-XXXVIII in FIG. 36.

39 is a sectional view taken along line XXXIX-XXXIX of FIG. 36.

FIG. 40 is an illustrative diagram for describing the manufacturing process of the semiconductor integrated circuit device in FIG. 36;

FIG. 41 is an explanatory diagram illustrating a manufacturing step of the semiconductor integrated circuit device in FIG. 36;

FIG. 42 is an illustrative diagram for describing the manufacturing process of the semiconductor integrated circuit device of FIG. 36;

FIG. 43 is an explanatory diagram for illustrating the manufacturing process of the semiconductor integrated circuit device in FIG. 36;

FIG. 44 is an illustrative diagram for describing the manufacturing process of the semiconductor integrated circuit device in FIG. 36;

FIG. 45 is an illustrative diagram for describing the manufacturing process of the semiconductor integrated circuit device in FIG. 36;

FIG. 46 is an illustrative diagram for describing the manufacturing process of the semiconductor integrated circuit device of FIG. 36;

FIG. 47 is an explanatory diagram for illustrating the manufacturing process of the semiconductor integrated circuit device in FIG. 36;

FIG. 48 is an explanatory diagram for illustrating the manufacturing process of the semiconductor integrated circuit device in FIG. 36;

FIG. 49 is an illustrative diagram for describing the manufacturing process of the semiconductor integrated circuit device of FIG. 36;

FIG. 50 is an illustrative diagram for describing the manufacturing process of the semiconductor integrated circuit device in FIG. 36;

FIG. 51 is an explanatory diagram for illustrating the manufacturing process of the semiconductor integrated circuit device in FIG. 36;

FIG. 52 is an illustrative diagram for describing the manufacturing process of the semiconductor integrated circuit device in FIG. 36;

FIG. 53 is an explanatory diagram for illustrating the manufacturing process of the semiconductor integrated circuit device in FIG. 36;

FIG. 54 is a plan view of relevant parts of a semiconductor integrated circuit device of the present invention.

FIG. 55 is a sectional view taken along the line XXXXXV-XXXXXV in FIG. 54;

FIG. 56 is a sectional view taken along the line XXXXXVI-XXXXXVI in FIG. 54;

FIG. 57 is a sectional view taken along line XXXXXVII-XXXXXVII in FIG. 54;

FIG. 58 is an illustrative diagram for describing the manufacturing process of the semiconductor integrated circuit device of FIG. 54;

FIG. 59 is an illustrative diagram for describing the manufacturing process of the semiconductor integrated circuit device of FIG. 54;

FIG. 60 is a cross-sectional view of a principal part of a semiconductor integrated circuit device according to another embodiment of the present invention;

FIG. 61 is a cross-sectional view of a principal part of a semiconductor integrated circuit device according to another embodiment of the present invention;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Separation insulating film 2a Thick film part 2b Thin film part 3M memory cell 3Ml semiconductor region 3Mi Gate insulating film 3Mfg Floating gate 3Mil Interlayer insulating film 3Mcg Control gate 4, 4a, 4b Thin insulating film 5 Sidewall 6a Interlayer insulating film 7 Sacrificial insulating film 8 insulating film 9a photoresist pattern 10 sidewall

Claims (8)

[Claims] 1. A semiconductor integrated circuit device having a plurality of nonvolatile memory cells each composed of a MIS transistor having a two-layer gate structure in which a control gate is provided on a floating gate via an insulating film, A semiconductor integrated circuit device, wherein a side wall floating gate portion electrically connected to the floating gate is provided on a side surface of the gate via an insulating film. 2. The semiconductor integrated circuit device according to claim 1, wherein an arrangement of said plurality of nonvolatile memory cells is AND.
Semiconductor integrated circuit device of any one of the following types: NOR type, NOR type, DINOR type or NAND type. 3. The semiconductor integrated circuit device according to claim 1, wherein said floating gate is formed on a lower floating gate portion formed on a gate insulating film so as to be wider than said lower floating gate portion. A semiconductor integrated circuit device comprising a stack of gate portions. 4. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein (a) after forming a control gate on a conductor film for forming the floating gate via an insulating film, a side surface of the control gate. And (b) patterning the conductive film for forming the floating gate using the insulating film on the control gate and the insulating film on the side surface thereof as a mask to form the floating gate. (C) depositing a conductive film on the semiconductor substrate after the formation of the floating gate, and etching back the conductive film,
Forming, on the side surface of the floating gate and the side surface of the control gate, the side wall floating gate portion electrically connected to the floating gate and insulated from the control gate via an insulating film. A method for manufacturing a semiconductor integrated circuit device, comprising: 5. A semiconductor integrated circuit device having a plurality of nonvolatile memory cells each including a MIS transistor having a two-layer gate structure in which a control gate is provided on a floating gate via an insulating film, A semiconductor integrated circuit device, wherein a side wall control gate portion electrically connected to the control gate is provided on a side surface of the gate via an insulating film. 6. The semiconductor integrated circuit device according to claim 5, wherein said plurality of nonvolatile memory cells are arranged in an AND manner.
Semiconductor integrated circuit device of any one of the following types: NOR type, NOR type, DINOR type or NAND type. 7. The semiconductor integrated circuit device according to claim 5, wherein said floating gate is formed on a lower floating gate formed on a gate insulating film and wider than said lower floating gate. A semiconductor integrated circuit device comprising a stack of gate portions. 8. The method for manufacturing a semiconductor integrated circuit device according to claim 5, wherein (a) after forming a control gate on a conductor film for forming the floating gate via an insulating film, a side surface of the control gate. (B) patterning the conductive film for forming the floating gate using the insulating film on the control gate and the insulating film on the side surface thereof as a mask, and forming the floating gate. (C) subjecting the semiconductor substrate after the formation of the floating gate to a thermal oxidation treatment to form an insulating film on the upper surface side of the semiconductor substrate and the side surface of the floating gate; Removing the insulating film on the side surface; and (d) depositing a conductive film on the semiconductor substrate after removing the insulating film on the side surface of the control gate, and then etching back the conductive film to form the floating film. The control gate is electrically connected to a side surface of the gate and a side surface of the control gate, and
Forming a side wall control gate portion insulated from the floating gate via an insulating film.