JPH10214174A - Asynchronous fifo circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the erroneous recognition of a full state/an empty state by receiving the input of the inverted signals of write signals and the inverted signals of read signals and generating and outputting full signals for indicating the full state or empty signals for indicating an empty state. SOLUTION: Corresponding to the write of data, the write signals WR from the outside are inverted and inputted to a write pointer 1-12. Similarly, corresponding to data read, the read signals RD from the outside are inverted and inputted to a read pointer 1-13. Then, a full/empty detection circuit for performing a decoding processing to the respective address signals of the write pointer 1-12 and the read pointer 1-13 so as to generate the full state and the empty state is removed and a spike generated by the decoding processing is eliminated. Thus, the erroneous recognition mutually between the full state and the empty state is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an asynchronous FIFO circuit.

[0002]

2. Description of the Related Art An example of a conventional asynchronous FIFO circuit is shown in FIG.
Is shown in The conventional example is (4 words) x (8 bits)
(Hereinafter, abbreviated as FIFO circuit), and includes a selector 4-2 and D flip-flops 4-3-4-7 (4 words) × (8 bits)
Register file 4-1 and write circuit 4-8
, A read circuit 4-9, inverters 4-10 and 4-11, a write pointer 4-12, a read pointer 4-13, and a full / empty detection circuit 4-14.
And synchronization circuits 4-15 and 4-16.

In FIG. 4, in response to data writing, a write signal WR from outside is inverted by a write circuit 4-8 and an inverter 4-10 to be inverted by a write pointer 4-12 and a synchronization circuit 4-15. Is input to Similarly, in response to the data read, the external read signal RD is inverted by the D flip-flop 47 and the inverter 411 to read the read pointer 4-1.
And input to the synchronization circuit 4-16. The write pointer 4-12 is a write pointer for outputting a write address signal at the time of data writing, is composed of a 3-bit counter, and outputs a 3-bit write address signal including W ₂ , W ₁ and W _0. You. These 3-bit write address signals W ₂ , W ₁ and W ₀
Are output to the full / empty detection circuit 4-14 and the lower two bits W ₁ and W
₀ is the write circuit 4-8 as a write address signal.
Is output to Note that the counter constituting the write pointer 4-12 is counted up at the rise of the inverted signal of the write signal WR by the inverter 4-10.

A read pointer 4-13 is a read pointer for outputting a read address signal at the time of reading data, and is similarly constituted by a 3-bit counter, and comprises a 3-bit counter including R ₂ , R ₁ and R _0. Is output. These 3-bit read address signals are supplied to the full / empty detection circuit 4
-14, and the lower two bits R ₁ and R ₀ are output to the read circuit 4-9 as a read address signal. This read pointer 4
Also at -13, the counter constituting the read pointer 4-13 is counted up at the rise of the inverted signal of the read signal RD by the inverter 4-11. As described above, the write pointer 4-12 and the read pointer 4-13 are both configured as counters having the same configuration, and are initialized by an external reset signal RST.

In the case of data writing, the write pointer 4-12 is provided in the write circuit 4-8.
The input write address signals W ₁ and W ₀ are decoded, and a 4-bit write control signal WR ₃ , WR ₂ , WR ₁ synchronized with the write signal WR is obtained by a logical operation with a write signal WR input from the outside. And W
R ₀ is generated and output, and input to the clock input terminals of the corresponding D flip-flops 4-3-4-6. External input data D _{7 to} D ₀ are input to the data input terminals of the D flip-flops 4-6, 4-5, 4-4 and 4-3. Is one of the write control signals W
Selected by R ₃ , WR ₂ , WR ₁ and WR ₀ ;
The data is written to the corresponding one of the D flip-flops 4-6, 4-5, 4-4, and 4-3.

On the other hand, in the case of reading data, in the read circuit 4-9, the read address signals R ₁ and R ₀ inputted from the read pointer 4-13 are decoded, and the read control signal of 4 bits is read. R
D ₃ , RD ₂ , RD ₁ and RD ₀ are generated and output to the selector 4-2, where the read control signals RD ₃ , RD ₂ , RD ₁ and RD ₀ are output.
Through the D flip-flops 4-6, 4-5, 4-4
And data input from 4-3 are selected as appropriate and D
Is input to the flip-flop 4-7, is written in the D flip-flop 4-7 via the read signal RD from the outside, is output as the output data Q ₇ to Q _0.

A full / empty detection circuit 4-14
Is a circuit for detecting whether the FIFO circuit is in a full (full) state or an empty (empty) state, and a specific circuit thereof is shown in FIG. As shown in FIG. 5, the full / empty detection circuit 4-1 includes EXOR gates 5-1 to 5-3, OR gates 5-4 and 5-7,
It is composed of AND gates 5-6. In FIG.
When the 3-bit outputs W ₂ , W ₁ and W ₀ input from the write pointer 4-12 match the 3-bit outputs R ₂ , R ₁ and R ₀ input from the read pointer 4-13, the OR gate 5 -7, the empty signal EMP indicating that the FIFO circuit is in the empty state.
TY is output, and the lower 2 bits W ₁ and W ₀ (write address signal) of the 3-bit output of the write pointer 4-12 and the lower 2 bits R ₁ and R ₀ (read address signal) of the 3-bit output of the read pointer 4-12 ) And the upper bit W ₂ of these write address signals and the upper bit R ₂ of the read address signal do not match, the AND gate 5-6 outputs the FIFO
A full signal FULL indicating that the O circuit is in the full state is output. These full signal FULL and empty signal EMPTY are input to corresponding synchronization circuits 4-15 and 4-16, respectively.

In the synchronization circuit 4-15, the full signal FU output from the full / empty detection circuit 4-14 is output.
LL, and the WR synchronized with the write signal WR using the inverted signal of the write signal WR as a synchronization clock.
An ITE-ACK signal is generated and output to the outside as a signal indicating whether or not to accept the next write. Similarly, in the synchronization circuit 4-16, the empty signal EMPT output from the full / empty detection circuit 4-1 is output.
Y, and a WRI synchronized with the read signal RD using the inverted signal of the read signal RD as a synchronization clock.
A TE-ACK signal is generated and output to the outside as a signal indicating whether or not to accept the next read.

[0009]

In the above-mentioned conventional asynchronous FIFO circuit, a write address signal output from a write pointer and an output signal from a read pointer are used to detect a full state or an empty state of the FIFO circuit. The read address signal is input to the full / empty detection circuit in an asynchronous state, and in the full / empty detection circuit,
A spike occurs in the process of generating a full signal or an empty signal from the asynchronous write address signal and the read address signal, and the interference by the spike causes the FIFO circuit to be in a full state or an empty state. There is a problem that erroneous recognition occurs in the determination of the above, and as a countermeasure, the full state and the empty state are determined by synchronizing the write signal and the read signal. For this reason, extra redundant time is required for synchronizing the write signal and the read signal, and data writing / reading is performed.
There is a disadvantage that the reading speed is deteriorated.

[0010]

SUMMARY OF THE INVENTION Asynchronous FIFO of the present invention
The circuit receives input of multiple bits of data from the outside, stores the multiple bits of data via a predetermined multiple bits of a write control signal, and stores the stored multiple bits of data through a predetermined multiple bits of a read control signal. Register file that is selected and output as read data of a plurality of bits through an external read signal, and the write signal that is reset through an external reset signal and is inverted through an inverted signal of the external write signal. A write pointer for generating and outputting a multi-bit write address signal synchronized with the above, and the write signal from the outside and a write address signal output from the write pointer are input to generate the write control signal of a plurality of bits. And a reset circuit via an external reset signal. A read pointer for generating and outputting a plurality of bits of a read address signal synchronized with the read signal via an inverted signal of the read signal from the outside, and a read address signal output from the read pointer. A read circuit that generates and outputs a plurality of bits of the read control signal; Full (FULL: full)
Full signal or empty (EMPTY:
And a full / empty identification circuit that generates and outputs an empty signal indicating an (empty) state.

In response to the n-stage asynchronous FIFO circuit, the full / empty discriminating circuit includes a first two-input NAND gate to which an inverted signal of the write signal is input at a first input terminal, and an external A first inverter for outputting an inverted signal of the reset signal from the first inverter, an output terminal of the first two-input NAND gate connected to a first input terminal, and an output terminal of the first inverter connected to a second input terminal. Ends are connected,
A first three-input NAND gate to which a first token erase signal is input to a third input terminal; an inverted signal of the write signal input to a first input terminal; To the output terminal of the two-input AND gate of
An input AND gate and a shift register block reset by a reset inversion signal output from the first inverter;
A token signal output from a gate and a second token erase signal output from a second unit connected in cascade are input to the first token erase signal and the first token erase signal.
A first unit that outputs a talk signal of
A second inverter that inverts the talk signal of the second and outputs the full signal, and a shift register block that is reset by the reset inversion signal.
The (i = 1, 2, 3,..., N-2) th token signal output from the (i = 1, 2, 3,..., N-1) unit and the (i + 2) th unit The (i + 2) th token erasure signal output from the
The (i + 1) -th unit that outputs the token signal of (1) and the (i + 1) -th token erasing signal, and a shift register block that is reset by the reset inversion signal. The (n-1) th token signal output and the token erasure signal generated via the inverted signal of the read signal are input, and the nth token signal and the nth token erasure signal are output. An n-th unit, a third inverter that inverts the n-th token erasure signal and outputs the same as the empty signal, a first input terminal to which the n-th token erasure signal is input, and a second input A second three-input NAND gate to which the reset inversion signal is input at one end; and an output terminal of the second three-input NAND gate to the first input terminal; A second two-input NAND gate an inverted signal of the read signal to the second input terminal is input,
An output terminal of the second two-input NAND gate is connected to a first input terminal, an inverted signal of the read signal is input to a second input terminal, and the output terminal is connected to the n-th unit. A third two-input N for outputting the token erase signal
And an AND gate.

The first unit may include a fourth two-input NAN to which the token signal is input at a first input terminal.
A D gate, and a fourth input NAND gate at a first input terminal.
A fifth two-input NAND gate to which an output terminal of the gate is connected and the first token output signal is output from the output terminal, and an output terminal of the fifth two-input NAND gate connected to the first input terminal A third three-input NAND gate having the second input terminal receiving the reset inversion signal, the third input terminal receiving the second token erase signal, and the third input terminal having the third input terminal. A fourth inverter to which the output terminal of the three-input NAND gate is connected, a fifth inverter to which the output terminal of the fourth inverter is connected to the input terminal, and the second token erasure to the first input terminal The signal is input and the second
Is connected to the output terminal of the fifth inverter, the third input terminal receives the token signal, and the output terminal is connected to the second input terminal of the fourth two-input NAND gate. A fourth three-input AND gate, an input terminal connected to the output terminal of the fourth three-input AND gate, and a sixth input terminal to which the token signal is input. A two-input NAND gate, and an output terminal of the sixth two-input NAND gate connected to the first input terminal;
An output terminal of the sixth inverter is connected to a second input terminal and a second input terminal of the sixth two-input NAND gate is connected to an output terminal.
A seven-input NAND gate to which the input terminal of
An output terminal of the seventh two-input NAND gate is connected to a first input terminal, and an output terminal of the sixth inverter is connected to a second input terminal. And an eighth two-input NAND gate for outputting the second unit to the n-th NAND gate.
(N-1) units including the above-mentioned unit are formed by the same circuit configuration as the first unit.

[0013]

Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the present invention. As shown in FIG.
This is an embodiment of a (4 words) × (8 bits) four-stage FIFO circuit, and includes a (4 words) × (8 bits) register file including a selector 1-2 and D flip-flops 1-3 to 1-7. 1-1, a writing circuit 1-8,
A read circuit 1-9, inverters 1-10 and 1-11, a write pointer 1-12, a read pointer 1-13, NAND gates 1-14, 1-16, 1
-23 to 1-25, inverters 1-17, 1-18,
1-26, AND gate 1-25, 4-stage FIFO
In correspondence with the circuit, each unit is formed as a shift register and includes four units 1-19 to 1-22 each holding a 1-bit token. The number of units is set to be equal to the number of stages of the asynchronous FIFO circuit. FIG. 2 is a circuit diagram showing an internal configuration of the unit 1-19 forming the above-described shift register block.
NAND gates 2-1 to 2-3 and 2-8 to 2-10
, Inverters 2-4, 2-5 and 2-7, and NAD
And a gate 2-6. The internal configuration of the other units 1-20 to 1-22 is also the same as the circuit diagram. 3 (a), (b), (c), (d),
(E), (f), (g), (h), (i), (j),
(K), (l), (m), (n) and (o) are operation timing diagrams in the present embodiment. Hereinafter, the operation of this embodiment will be described with reference to FIGS. 1, 2, and 3.

In FIG. 1, in response to data writing, an external write signal WR is inverted by a write circuit 1-8 and an inverter 1-10, and is inverted by a write pointer 1-12, a NAND gate 1-14, AND
Input to gate 1-15. Similarly, in response to data reading, an external read signal RD is inverted by a D flip-flop 1-7 and an inverter 1-11, and is read by a read pointer 1-13 and a NAND gate 1-2.
4 and the NAND gate 25.

The write pointer 1-12 is a write pointer for outputting a write address signal at the time of data writing, is constituted by a 3-bit counter, and is initialized by an external reset signal RST. At the time of writing data, an inverted write signal of the externally input write signal WR by the inverter 1-10 is input to the clock input terminal, and is counted up at the rising edge of the inverted write signal. The lower two bits W ₁ and W ₀ are output as write address signals and input to the write circuit 1-8. In the writing circuit 1-8,
Write pointer 1-12 in synchronization with write signal WR
Receiving the input of the write address signal output from
Write control signals WR ₀ , WR ₁ , WR ₂ and WR ₃ corresponding to the write address signal are output, and are applied to clock input terminals of corresponding D flip-flops 1-3, 1-4, 1-5 and 1-6. Is entered. The data D _{7 to} D ₀ input to the data input terminals of these D flip-flops 1-3, 1-4, 1-5 and 1-6 correspond to the above-mentioned write control signals WR ₀ , WR ₁ , WR ₂ and WR
₃ are written to these D flip-flops.

The read pointer 1-13 is a read pointer for outputting a read address signal at the time of data reading. Like the write pointer 1-12, the read pointer 1-13 is constituted by a 3-bit counter. Initialized by the signal RST. At the time of data reading, an inverted read signal of the read signal RD input from the outside by the inverter 1-11 is input to the clock input terminal, and is counted up at the rising edge of the inverted read signal. The lower two bits R ₁ and R ₀ are output as read address signals and input to the read circuit 1-9. In the read circuit 1-9, the read signal R
In response to the input of the read address signal output from the read pointer 1-13 in synchronization with D, the read data selection signal RD ₃ corresponding to the read address signal,
RD ₂ , RD ₁ and RD ₀ are output and the selector 1-
2 is input.

In the D flip-flop 1-7, via the read data selection signals RD ₃ , RD ₂ , RD ₁ and RD ₀ output from the read circuit 1-9,
The data output of the D flip-flops 1-3 to 1-6 selected by the selector 1-2 is written at the rising edge of the read signal RD externally input to the clock input terminal, and the data of the D flip-flop 1-7 is written. From the output terminal, the read signals Q _{7 to} Q _{0 of the} FIFO circuit are output.
Is output as

Next, referring to FIGS. 1, 2 and 3,
A token generation operation, a token bubble-through operation, and a token erasure operation in the present embodiment will be described. In FIG. 1, a write signal WR to the FIFO circuit of the present embodiment causes a register file 1-.
The writing of the write input data D _{7 to} D _{0 to} 1 is completed. At this time, the write signal WR is inverted by the inverter 1-9 to generate the inverted write signal 101 (see FIG. 3A), so that the AND gate 1-1
5, the token signal 103 of "H" level (FIG. 3
(See (c)) is output. The token signal 103 is input to the first-stage shift register forming the unit 1-19. In FIG. 2, the shift register includes:
In order to hold the token signal at the first stage of the shift register, a flip-flop circuit is formed by the NAND gates 2-2 and 2-3, and the data write operation to the flip-flop circuit is performed by the output of the NAND gate 2-1. 105 (see FIG. 3E), the AN
It is prohibited until the operation conditions of the D gate 2-6 are met.
Therefore, the write operation to the flip-flop circuit formed by the NAND gates 2-2 and 2-3 involves the propagation of the token signal from the preceding stage and the presence of the token signal in the flip-flop circuits of the NAND gates 2-2 and 2-3. That the token signal has not been propagated to the next stage, and that the token signal held in the flip-flop circuits of the NAND gates 2-2 and 2-3 is not being erased (unit 1- The token erasing signal 115 input from the terminal 20 is at "H" level: see FIG.

When the token signal does not exist in the flip-flop circuits of the NAND gates 2-2 and 2-3, the output 106 of the NAND gate 2-2 (see FIG. 3 (f)) becomes "L" level. , NAND gate 2-3 (see FIG. 3 (g)) is at "H" level, and token erase signal 115 input from unit 1-20 is output.
(See FIG. 3 (o)) is input at the “H” level.
Token signal 10 output from AND gate 1-15
3 (see FIG. 3 (c)) are AND gates 2-6 and N
The signal is transmitted to the flip-flop circuits 2-2 and 2-3 via the AND gate 2-1. The propagation of the token signal causes the output 106 of the NAND gate 2-2 (FIG. 3 (f)).
) From “L” level to “H” level, and NA
The output 107 of the ND gate 2-3 (see FIG. 3 (g)) changes from "H" level to "L" level. As a result, the output 109 at "L" level (see FIG. 3 (i)) is supplied to the AND gate 2--2 via inverters 2-4 and 2-5.
6 and the output 110 of the AND gate 2-6.
(See FIG. 3 (j)) changes from the "H" level to the "L" level, and the propagation of the next token signal is inhibited. According to this operation process, the token signal (see FIG. 3C) generated in the NAND gate 1-15 is propagated to the first stage of the shift register forming the unit 1-19. It is necessary to erase the token signal in the preceding stage. With this erase operation,
NAND gates 2-2 and 2 are provided by AND gate 2-6.
-3 can be propagated to the flip-flop circuit, and the output 110 of the AND gate 2-6 (FIG. 3 (j))
) Is inverted to transition from “L” level to “H” level, and returns to “L” level again, and when the propagation of the token signal is completed, the output 110 of the AND gate 2-6 is completed.
At the falling edge of (see FIG. 3 (j)), the token erase signal 114 for the preceding stage (see FIG. 3 (n)) is changed from “H” level to “L” level, and the NAND
From the gate 2-10, the token erase signal 114 (FIG. 3)
(See (n)). In this state,
The token signal held in the flip-flop circuits of the NAND gates 2-2 and 2-3 is erased, and the output 103 (see FIG. 3C) of the AND gate 1-15 becomes "L" level. The flip-flop circuit formed by the gates 2-7 and 2-9 is in a reset state. As a result, the token erasure signal 114 (see FIG. 3 (n)) output from the NAND gate 2-10 returns from the "L" level to the "H" level, and the token erasure request for the preceding stage is cancelled. The erasing operation is completed.

Thus, the units 1-19, 1-
In each shift register block forming 20, 20, 21 and 22, the token transmission operation to the next stage and the token erase operation at the subsequent stage are repeatedly performed in conjunction with each other, so that the token signal to the output stage of these shift registers is obtained. Is propagated. Unit 1-21
In the output stage, the read operation is completed at the trailing edge of the read signal RD to the FIFO circuit, but the inverted read signal of the read signal RD by the inverter 1-11 is supplied to the NAND gates 1-24 and 1-2.
5, the token signal of the unit 1-22 can be erased, and the level of the token signal 117 output from the unit 1-22 becomes "H" level by the erasure of the token. To the "L" level, the output level of the NAND gate 1-25 returns to the "H" level again, and the above-described token signal erasing request is canceled.

Next, referring to FIG. 1, the token signal 10 output from the NAND gate 2-2 of the unit 1-19 will be described.
6, an empty signal FULL inverted by the inverter 1-17 and the token signal 117 output from the NAND gate 2-2 of the unit 1-22 are inverted by the inverter 1-26 and output. Signal E
MPTY will be described in detail. Where FIFO
The full state of the circuit means a state in which a token exists in the unit 1-19 forming the shift register block, and the empty state of the FIFO circuit means the state of the unit 1-2 forming the shift register block.
2 means that no token exists.

The trigger signal for bringing the FIFO circuit to the full state is always a write signal W to the FIFO circuit.
R itself, and the FIFO circuit is brought into a full state only by the write signal WR. Actually, the read signal RD to the FIFO circuit is always the full signal FULL
Operates only in the direction of clearing the full signal FULL, so that high-speed writing can be performed by reading the full signal FULL without going through a synchronization circuit.
Since the propagation of the token signal is processed through the delay action of each gate circuit, the delay of the gate circuit is
Although this will affect the cycle time when performing continuous writing, after the writing operation is completed, the unit 1
After the transmission of the token signal to the first stage of −19 is completed,
Since the number of stages of the gate circuit that passes through to the next stage is about 20 in the case of the FIFO circuit of the present embodiment, the operation time is completed in about 10 ns,
Therefore, a continuous write operation at 50 MHz (20 ns) becomes possible.

The trigger signal for bringing the FIFO circuit into the empty state is always the read signal RD for the FIFO circuit, and the read signal RD
The FIFO circuit is in an empty state. Actually, since the read signal RD to the FIFO circuit always acts only in the direction to clear the empty signal EMPTY, high-speed reading can be performed by reading the empty signal EMPTY without passing through the synchronization circuit. It is possible to do. Also, since the propagation of the token signal is controlled through the delay action of each gate circuit, the time from once reading to the propagation of the next token signal is the time of continuous reading operation. However, the number of stages of the gate circuit that the token passes when the token is propagated after the read operation is completed is approximately 20 in the case of the FIFO circuit of the present embodiment. After the elapsed time of about 10 ns, the next read operation can be performed. Therefore, a continuous read operation at 50 MHz (20 ns) becomes possible.

[0024]

As described above, the present invention is applied to an asynchronous FIFO circuit, and generates a full state and an empty state of the asynchronous FIFO circuit. By eliminating the full / empty detection circuit for performing the decoding process and eliminating spikes generated by the decoding process, there is an effect that erroneous recognition between the full state and the empty state can be prevented.

Further, since the introduction of the synchronization circuit as the circuit means for generating the full state and the empty state is eliminated, it is possible to eliminate the time delay caused by the synchronization operation by the synchronization circuit. This makes it possible to improve the processing speed of the asynchronous FIFO circuit.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a circuit diagram showing an internal configuration of a unit according to the embodiment.

FIG. 3 is an operation timing chart in the present embodiment.

FIG. 4 is a block diagram showing a conventional example.

FIG. 5 is a circuit diagram showing an internal configuration of a full / empty detection circuit in a conventional example.

[Explanation of symbols]

1-1, 4-1 Register file 1-2, 4-2 Selector 1-3-1-7, 4-3-4-7 D flip-flop 1-8, 4-8 Write circuit 1-9, 4- 9 Readout circuit 1-10, 1-11, 1-17, 1-18, 1-26,
2-4, 2-5, 2-7, 4-10, 4-11, 5-5
Inverter 1-12, 4-12 Write pointer 1-13, 4-13 Read pointer 1-14, 1-16, 1-23-1-25, 2-1-2
-3, 2-8 to 2-10 NAND gate 1-15, 2-6, 5-6 AND gate 1-19 to 1-22 unit 4-14 Full / empty detection circuit 4-15, 4-16 Synchronization Circuit 5-1 to 5-3 EXOR gate 5-4, 5-7 OR gate

Claims (3)

[Claims] 1. A multi-bit read control signal receiving a plurality of bits of data from an external device and storing the multi-bit data via a predetermined multi-bit write control signal. And a register file that is selected via the external read signal and output as a plurality of bits of read data via an external read signal. The register file is reset via an external reset signal. A write pointer for generating and outputting a multi-bit write address signal synchronized with a write signal; and an externally applied write signal and a write address signal output from the write pointer, and a multi-bit write control signal. And a write circuit that generates and outputs A read pointer that generates and outputs a plurality of bits of a read address signal synchronized with the read signal via an inverted signal of the read signal from outside, and a read address signal output from the read pointer. A read circuit for generating and outputting a plurality of bits of the read control signal; and a shift register block included therein upon receiving an input of an inverted signal of the write signal and an inverted signal of the read signal from outside. A full / empty identification circuit that generates and outputs a full signal indicating a full (FULL: full) state or an empty signal indicating an empty (EMPTY: empty) state of the asynchronous FIFO. circuit. 2. In response to an n-stage asynchronous FIFO circuit,
A first two-input NA having a first input terminal to which an inverted signal of the write signal is input;
An ND gate, a first inverter that outputs an inverted signal of an external reset signal, an output terminal of the first two-input NAND gate connected to a first input terminal, and a second input terminal connected to the second input terminal. A first three-input NAND gate to which an output terminal of the first inverter is connected and a third input terminal to which a first token erase signal is input; and an input signal to which an inverted signal of the write signal is input. A first two-input AND gate having an output terminal of the first two-input AND gate connected to a second input terminal; and a shift register reset by a reset inversion signal output from the first inverter. A token signal output from the first two-input AND gate and a second token erasure signal output from a cascade-connected second unit, which are formed by a block; A first unit that outputs a first token erase signal and a first talk signal; a second inverter that inverts the first talk signal and outputs the full signal; and a reset by the reset inverted signal And the i-th (i = 1, 2, 3, 3)
.., N−1) output from the unit (i =
, N-2) and the (i + 2) th token erasure signal output from the (i + 2) th unit are input, and the (i + 1) th token signal and the (i + 1) th token signal are input. And (n-1) th unit formed by a (i + 1) th unit that outputs a token erase signal of (i) and a shift register block reset by the reset inversion signal and output from the (n−1) th unit. An n-th unit that receives as input a token signal generated through an inverted signal of the read signal and an n-th token signal and an n-th token erase signal; A third inverter for inverting the token erasure signal of the above and outputting the same as the empty signal, and the n-th token erasure signal is input to a first input terminal, A second three-input NAND gate to which the reset inversion signal is input at the input terminal; an output terminal of the second three-input NAND gate connected to the first input terminal; and a read signal at the second input terminal A second two-input NAND gate to which the inverted signal of the above is input, an output terminal of the second two-input NAND gate is connected to a first input terminal, and an inverted signal of the read signal is connected to a second input terminal. A third two-input N which is input and outputs the token erasure signal from the output terminal to the n-th unit.
2. The asynchronous FIFO circuit according to claim 1, further comprising: an AND gate. 3. The first unit, wherein the fourth input NAND gate receives the token signal at a first input terminal, and the output of the fourth two input NAND gate at a first input terminal. A second input NAND gate having an output terminal connected to the first token signal and an output terminal of the fifth two-input NAND gate connected to the first input terminal. A third input NAND gate having the input terminal receiving the reset inversion signal and a third input terminal receiving the second token erase signal; and a third input NAND gate having an input terminal. A fourth inverter to which an output terminal of the fourth inverter is connected, a fifth inverter to which an output terminal of the fourth inverter is connected to an input terminal, and the second token erasing signal to be inputted to a first input terminal. And the fifth input terminal to a second input terminal. A fourth three-input AND gate having an output terminal connected to the third input terminal, the token signal being input to the third input terminal, and an output terminal connected to the second input terminal of the fourth two-input NAND gate; A sixth inverter having an input terminal connected to the output terminal of the fourth three-input AND gate, and a sixth input terminal having the first input terminal receiving the token signal.
An input NAND gate, a first input terminal connected to the output terminal of the sixth two-input NAND gate, a second input terminal connected to an output terminal of the sixth inverter, and an output terminal connected to the output terminal of the sixth inverter. 6 2-input NAN
Seventh two-input NA to which the second input terminal of the D gate is connected
An ND gate; a first input terminal connected to an output terminal of the seventh two-input NAND gate; a second input terminal connected to an output terminal of the sixth inverter; And an (n-1) -th unit including the second to n-th units, wherein each of the (n-1) units includes the second unit to the n-th unit. 3. The asynchronous FIFO according to claim 2, wherein the asynchronous FIFO is formed by the same circuit configuration as the first unit.
circuit.