JPH10210088A - Circuit for receiving signal - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the deterioration of an output duty rate by detecting the change of the voltage level of a burst input signal, and operating feedback for attenuating the input signal according to the change of this detected voltage level. SOLUTION: The bottom value of the output of an automatic threshold control(ATC) circuit 3 is detected by a bottom detector 6, a clump circuit 5 is operated by using a result amplified by an amplifier 7, and the output amplitude of a pre-amplifier 2 is controlled. Then, identification adjustment is operated by the ATC circuit 3, and the result is outputted through a limited amplifier 4. The bottom detector 6 detects the bottom values of the positive phase output and anti-phase output of the ATC circuit 3. The bottom values of the positive phase output and anti-phase output of the pre-amplifier 2 are calculated, clamped by a diode 63, and outputted to the amplifier 7. Thus, the output of the amplifier 7 is changed. Then, transistors 51 and 52 are operated according to this change, and currents running through the diodes 53 and 54 are controlled. Therefore, the output of the preamplifier 2 can be attenuated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a signal receiving circuit, and more particularly to a circuit for receiving an optical signal and outputting a signal having a pulse width corresponding to the voltage level of the signal.

[0002]

2. Description of the Related Art Generally, a passive double star (PD) is used.
An S: Passive Double Star (S) system is a system for transmitting data between one station and a plurality of subscribers. In this system, transmission from a subscriber to a station is performed by time division multiple access via transmission lines having different distances.
The burst signal has a signal level difference of 0 [dB].

A circuit for receiving the burst signal will be described with reference to the drawings. FIG. 3 is a block diagram showing a configuration of a conventional signal receiving circuit.

In FIG. 1, a conventional signal receiving circuit includes a photoelectric converter 1 for converting a received optical signal into an electric signal, and amplifies the converted electric signal to convert it into positive-phase and negative-phase differential outputs. Preamplifier 2 and an automatic threshold value adjusting circuit (Automat) for adjusting an identification value for the output of the preamplifier.
ic Threshold Control: A
3) and a limiter amplifier 4 for amplifying the output of the ATC circuit 3 and outputting the amplified signal as a signal having a predetermined pulse width. As shown in the figure, the ATC circuit 3 includes a peak detector (PD) 31 that detects a peak value of each of the positive-phase signal and the negative-phase signal.
And 32, a resistor 33 inserted in the positive-phase signal line, a resistor 34 inserted in the negative-phase signal line, a resistor 35 for applying the output of the peak detector 31 to the negative-phase signal line, and a peak detector And a resistor 36 for applying the output of the counter 32 to the positive-phase signal line.

A conventional signal receiving circuit uses the ATC
Bottom detector 60 for detecting the bottom value of the output of circuit 3
And a bottom level detector 70 for comparing the detected bottom value with a predetermined voltage level, a variable attenuator 50 for attenuating the output of the preamplifier, and selecting an amount of attenuation of the variable attenuator 50 according to the detected bottom level. Attenuation amount selection circuit 8
It is comprised including. As shown in the figure, the bottom detector 60 includes bottom detectors (BD) 61 and 62 for detecting a bottom value for each of the positive-phase signal and the negative-phase signal. Note that reference numeral 9 in the figure denotes a reset pulse.

[0006] In such a configuration, the photoelectric converter 1 comprises:
The input optical signal is converted into an electric signal. The electric signal from the photoelectric converter 1 is amplified by the preamplifier 2 and converted into a differential output voltage. After the output of the preamplifier 2 is identified and adjusted by the ATC circuit 3, the output of the limiter amplifier 4
Is input to The limiter amplifier 4 amplifies the input signal,
The output is performed with a limit at a certain amplitude level.

Here, the bottom value of the output of the ATC circuit 3 is detected by a bottom detector 60 and is input to a bottom level detector 70 composed of an EX-OR 74 and comparators 71 and 72. In the bottom level detector 70, the result of identifying the bottom value with respect to the voltage value of the reference voltage source 73 is represented by RSF
/ F81, a comparator 82 and a peak detector 84. The attenuation amount selection circuit 8 receives the information and controls the output amplitude of the variable attenuator 50.
Thereby, the identification adjustment is performed again in the ATC circuit 3, and
The duty ratio of the output of the limiter amplifier 4 is corrected.

Further, referring to the time chart of FIG.
The above operation will be described.

First, the signal light is converted into an electric signal by the photoelectric converter 1. This is shown in FIG. The electric signal is amplified by the preamplifier 2 and converted into positive and negative phase differential output voltages. This is shown in FIG. The output of the preamplifier 2 is input to the ATC circuit 3 through the variable attenuator 50.

In the ATC circuit 3, the peak detector (P
D) At 31 and 32, the peak value of the voltage level of the positive-phase output and the negative-phase output of the preamplifier is detected. This peak value is output from the ATC circuit 3 and input to the limiter amplifier 4. Note that the peak detectors 31 and 32 are reset at the input timing of the reset pulse 9 (FIG. 3C).

The output of the ATC circuit 3 is amplified by a limiter amplifier 4, limited at a predetermined voltage level, and output as a data signal.

Here, a case where a large input signal (FIG. 4A) is input will be described. In a state before the feedback control by the detectors 60 and 70 and the selection circuit 8 is applied, the output of the ATC circuit 3 has a hold error, as shown in FIG. From this state, the bottom detector 60 detects the bottom values of the positive-phase output and the negative-phase output of the ATC circuit 3 respectively. This detection result is shown in FIG.
It is shown in (f).

The bottom detector 6 in the bottom detector 60
Outputs from the first and the second 62 are input to comparators 71 and 72 of the bottom level detector 70, and are compared with a reference voltage from a reference voltage source 73. The outputs of the comparators 71 and 72 are shown in FIG.
These are shown in (g) and are input to the EX-OR 74. The EX-OR 74 identifies the logic of the outputs of the comparators 71 and 72, and outputs information only when the logic is inverted (the logic does not match). The output of the EX-OR 74 is input to the set side of the RSF / F 81 in the attenuation amount selection circuit 8.

Next, the peak detector 84 detects the peak value of the amplitude of the positive-phase output signal of the preamplifier 2. here,
FIG. 4D shows each of the peak detectors 31, 32 and 8
4 are shown. It is assumed that the RSF / F81 has been initialized by the reset pulse 9 during the guard time.

The comparator 82 compares the peak value detected by the peak detector 84 with the reference voltage from the reference voltage source 83. As a result of the comparison, in the case of a small signal input that does not cause a hold error, the RSF / F 81 in the attenuation amount selection circuit 8
Is input to the reset side.

As a result, the variable attenuator 50 operates only when a signal having an amplitude large enough to cause a hold error is input.
Control is performed to attenuate the output amplitude of the preamplifier 2. Therefore, the output of the attenuation amount selection circuit 8 is as shown in FIG. 4H, and the output of the variable attenuator 50 is as shown in FIG.

The output of the variable attenuator 50 thus attenuated is again supplied to the peak detectors 31 and 32 of the ATC circuit 3.
At the peak. Peak detector 3
As shown in FIG. 4 (j), the ATC circuit 3 uses the signal identification value (dotted line in FIG. 4 (j)).
Outputs the waveform at the center of the signal. ATC circuit 3
4 (k), the duty ratio of the output of the limiter amplifier 4 becomes as shown in FIG. 4 (k), and an output having the same pulse width as the pulse width T1 of the input signal is obtained.

The above operation can be summarized as shown in FIG. As shown in the figure, when the output of the photoelectric converter 1 includes three pulses having the pulse width T1, if the peak value of the pulse changes, the preamplifier 2 Output also changes.

Here, in the conventional circuit described above, the RSF
While / F81 is in the set state, the output of the attenuation selecting circuit 8 is always at the high level, and the attenuation of the variable attenuator 50 is constant. Further, while the RSF / F81 is in the reset state, the output of the attenuation amount selection circuit 8 is always at the low level,
The attenuation of the variable attenuator 50 is constant. That is, in the attenuation amount selecting circuit 8, the duty ratio is corrected by digital processing.

Since the amount of attenuation of the variable attenuator 50 is one of two values, the amount of attenuation is constant even when the output of the photoelectric converter 1 includes a pulse having a lower peak value than the others. . For this reason, the output of the limiter amplifier 4 includes a pulse width T2 narrower than the pulse width T1. Thus, when the peak value changes within one frame, the pulse width of the output of the limiter amplifier 4 changes, and the pulse duty ratio changes.

[0021]

In the prior art described above, the duty ratio is corrected by digital processing for each frame of the input burst signal. Therefore, with respect to a minute signal level fluctuation within one frame,
A slight duty deterioration occurs. In general, since retiming is performed after receiving light, there is a disadvantage that if the duty is deteriorated, the contents of data cannot be correctly recognized.

Further, the above-described conventional circuit has a disadvantage that the configuration of the bottom detector, the bottom level detector, and the attenuation amount selecting circuit for performing the duty correction is complicated and the circuit scale is large.

In Japanese Patent Application Laid-Open No. 57-204661, there is no circuit for discharging the peak detector. Therefore, there is a disadvantage that the signal intensity is suddenly changed in the burst transmission and the burst transmission is difficult. Further, Japanese Patent Application Laid-Open No. 58-11 / 1983
The circuit described in Japanese Patent No. 4637 has a drawback that burst transmission is difficult because a coupling capacitor is provided in a signal line.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned drawbacks of the prior art, and an object of the present invention is to provide a signal receiving circuit which can keep a duty ratio of a received burst signal constant and has a small circuit scale. It is to provide.

[0025]

A signal receiving circuit according to the present invention is a signal receiving circuit for receiving a burst input signal and outputting a signal having a pulse width corresponding to the voltage level of the signal. It is characterized by including detection means for detecting a change in the voltage level, and attenuating means for attenuating the input signal in accordance with the detected change in the voltage level.

In short, the present signal receiving circuit corrects the duty ratio not by digital processing but by analog processing. This makes it possible to cope with minute signal level fluctuations within one frame, and to keep the duty ratio constant.

Further, since it can be realized by several types of active elements and the like, the circuit scale is small.

[0028]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a signal receiving circuit according to the present invention. 3, the same parts as those in FIG. 3 are denoted by the same reference numerals, and detailed description of those parts will be omitted. In the figure, the point that the signal receiving circuit according to the present embodiment differs from the conventional circuit is that the bottom detector 6,
The point is that feedback control by the amplifier 7 and the clamp circuit 5 is performed.

The bottom detector 6 includes bottom detectors 61 and 62 provided corresponding to the positive and negative phases, respectively, and a diode 6 for clamping the output of the bottom detector 61.
3 is included.

The output of the bottom detector 6 is applied to the minus side of the amplifier 7. The amplifier 7 amplifies the output of the bottom detector 6.

The clamp circuit 5 has an N-channel (hereinafter, referred to as Nch) having a negative-phase output of the amplifier 7 as a gate input.
MOS (Metal Oxide Semiconductor)
ctor) Transistors 51 and 52 and Schottky barrier diodes 53 and 54 provided corresponding to the transistors 51 and 52 and having the drain voltage of the corresponding transistor applied to the cathode and the input signal applied to the anode. It is comprised including. In addition,
The transistor 51 and the diode 53 are for controlling the positive phase of the input signal, and the transistor 52 and the diode 54 are for controlling the negative phase of the input signal.

In such a configuration, the signal light is converted by the photoelectric converter 1 into an electric signal. The electric signal is amplified by the preamplifier 2 and converted into positive and negative phase differential output voltages. The output of the preamplifier 2 is input to the ATC circuit 3. The output of the ATC circuit 3 is amplified by a limiter amplifier 4. The limiter amplifier 4 amplifies the input signal, limits the signal at a predetermined amplitude level, and outputs the signal.

Here, the bottom value of the output of the ATC circuit 3 is detected by the bottom detector 60, and the clamp circuit 5 is operated using the result amplified by the amplifier 7 to control the output amplitude of the preamplifier 2. Then, the identification and adjustment are performed again by the ATC circuit 3 and output via the limiter amplifier 4. As described above, the output of the preamplifier 2 is attenuated by the clamp circuit 5, thereby suppressing a hold error at the time of a large signal and correcting the duty ratio.

Further, referring to the time chart of FIG.
The above operation will be described. In addition, FIG.
(E) is equivalent to each of the waveforms in FIGS. 4 (a) to 4 (e), and a detailed description thereof will be omitted.

When a signal having a large amplitude as shown in FIG. 2A is input, the following operation is performed. When a signal light having a large amplitude is input, before the feedback control by the bottom detector 6, the amplifier 7, and the clamp circuit 5 is applied, the ATC circuit 3 is provided as in the conventional example.
Is as shown in FIG. 2 (e). From this state, since a hold error has occurred, the bottom detector 6 detects the bottom values of the positive-phase output and the negative-phase output of the ATC circuit 3, respectively. At this time, as shown in FIG. 2F, when the output of the bottom detector 61 is constant, the output of the bottom detector 62 changes. These bottom detectors 6
The information respectively output from 1 and 62 is clamped by the diode 63 and becomes as shown in FIG. This signal is input to the minus side of the amplifier 7.

The amplifier 7 amplifies information from the bottom detector 6 to a certain potential. The output of the opposite phase of the amplifier 7 is as shown in FIG. 2 (h), which is input to the clamp circuit 5.

The clamp circuit 5 operates as follows. First, when the output amplitude of the preamplifier 2 is small, the output voltage of the amplifier 7 is small. On the positive phase side, when the output amplitude of the amplifier 7 is small, the gate voltage (Vgs) of the NchMOS transistor 51 of the clamp circuit 5 is small. Voltage Vg
When s is small, the drain-source current (Ids) is small. When the current Ids is small, the drain voltage (Vd) increases. When the voltage Vd is high, the current flowing through the diode 53 between the transistor 51 and the positive-phase signal line decreases. The output amplitude of the preamplifier 2 is attenuated by the current flowing through the diode 53. Therefore, the diode 53
The smaller the current flowing through the circuit, the smaller the amount of attenuation.

On the other hand, when the output amplitude of the preamplifier 2 is large, the output amplitude of the preamplifier 7 becomes large,
The gate voltage Vgs of the MOS transistor 51 is large,
Many currents Ids flow. Therefore, the drain voltage Vd decreases, and the current flowing through the diode 53 increases. For this reason, the output amplitude of the preamplifier 2 is greatly attenuated.
This attenuated signal is sent to the ATC circuit 3 in the next stage.

In the case of the negative phase, the output voltage of the negative phase is different from the output voltage of the positive phase.
NchM with low operating point due to hMOS transistor 51
By using the OS transistor 52, the same operation as on the positive phase side is performed. The signal attenuated by the above operation is shown in FIG.
It is shown in (i).

The peak value of the signal thus attenuated is held by the peak detectors 31 and 32 of the ATC circuit 3. As shown in FIG. 2 (j), the ATC circuit 3 outputs a waveform in which the signal identification value (dashed line in FIG. 2 (j)) is at the center of the signal by these peak detectors 31 and 32. Since the signal identification value of the output of the ATC circuit 3 is at the center, the duty ratio of the output of the limiter amplifier 4 is as shown in FIG. 2 (k), and an output having the same pulse width T1 as the pulse width T1 of the input signal is obtained. .

The above operation is summarized as shown in FIG. As shown in the figure, when the output of the photoelectric converter 1 includes three pulses having the pulse width T1, if the peak value of the pulse changes, the preamplifier 2 Output also changes.

The bottom values of the positive and negative phases of the output of the preamplifier 2 are respectively obtained, clamped by the diode 63, and input to the amplifier 7. As a result, the output of the amplifier 7 changes as shown in FIG. The transistors 51 and 52 operate according to this change, and control the current flowing through the diodes 53 and 54. As a result, the output of the preamplifier 2 is attenuated.

On the other hand, in the conventional circuit described above, since the duty ratio is corrected by digital processing as shown in FIG. 2B, the output of the attenuation amount selecting circuit 8 is at a high level. Or one of two low level values.

As described above, in the present circuit, the duty ratio is corrected by analog processing. Therefore, even if the output of the photoelectric converter 1 includes a pulse whose peak value is lower than that of the other, the limiter amplifier 4 The output is a signal having the same pulse width T1 as the pulse width T1 of the photoelectric converter 1. As a result, in the output of the limiter amplifier 4, the pulse duty ratio can be kept constant.

As described above, in the present circuit, the change in the voltage level of the burst input signal is detected, and the feedback is performed to attenuate the input signal in accordance with the detected change in the voltage level. This prevents the output duty ratio from deteriorating. As a result, the contents of the data can be correctly recognized. In addition, since the present circuit employs a simple configuration such as an amplifier and a transistor, the circuit scale is smaller than that of a conventional circuit.

Although the above description has been given of the case where an optical signal is input, it is apparent that the present invention can be applied to a case where another burst signal is input.

The present invention can take the following aspects in connection with the description of the claims.

(4) The attenuating means clamps the input signal at a predetermined voltage, and controls a change in the clamp voltage of the clamping means according to a change in the bottom value detected by the bottom value detecting means. 4. The signal receiving circuit according to claim 1, further comprising a clamp voltage change control unit.

(5) The clamp voltage change control means controls the MO in which the drain voltage changes according to the change in the bottom value.
The signal receiving circuit according to any one of claims 1 to 4, wherein the signal receiving circuit is an S transistor, and the clamp unit is a diode to which the input signal is applied to an anode and the drain voltage is applied to a cathode.

[0051]

As described above, the present invention detects a change in the voltage level of the burst input signal and performs feedback to attenuate the input signal in accordance with the detected change in the voltage level. There is an effect that it is possible to cope with fluctuations in the voltage level within the frame and to prevent deterioration of the output duty ratio. Further, since a simple configuration is employed, there is an effect that the circuit scale is smaller than that of the conventional circuit.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a signal receiving circuit according to an embodiment of the present invention.

FIG. 2 is a time chart showing the operation of each unit in FIG.

FIG. 3 is a block diagram showing a configuration of a conventional signal receiving circuit.

FIG. 4 is a time chart illustrating the operation of each unit in FIG. 4;

5 is a time chart showing a summary of the operation of the signal receiving circuit of FIG. 1 and the signal receiving circuit of FIG. 3;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Opto-electric converter 2 Preamplifier 3 ATC circuit 4 Limiter amplifier 5 Clamp circuit 6 Bottom detector 7 Amplifier 31 and 32 Peak detector 51 and 52 NchMOS transistor 53 and 54 Schottky barrier diode 61 and 62 Bottom detector 63 Diode

Claims (3)

[Claims] 1. A signal receiving circuit for receiving a burst input signal and outputting a signal having a pulse width corresponding to the voltage level of the signal, comprising: detecting means for detecting a change in the voltage level of the input signal; A signal attenuating means for attenuating the input signal in accordance with a change in the detected voltage level. 2. The apparatus according to claim 1, wherein said detecting means comprises: identification value adjusting means for detecting a peak value of the input digital signal and adjusting an identification value of the signal; and bottom value detecting means for detecting a bottom value of the signal after the adjustment. 2. The signal receiving circuit according to claim 1, wherein the attenuation unit attenuates the input signal according to a change in the bottom value detected by the bottom value detection unit. 3. The signal receiving circuit according to claim 1, wherein the input signal is a photoelectrically converted optical signal.