JPH10209904A - Receiver - Google Patents

Receiver

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Publication number
JPH10209904A
JPH10209904A JP822097A JP822097A JPH10209904A JP H10209904 A JPH10209904 A JP H10209904A JP 822097 A JP822097 A JP 822097A JP 822097 A JP822097 A JP 822097A JP H10209904 A JPH10209904 A JP H10209904A
Authority
JP
Japan
Prior art keywords
band
signal
filter
complex
digital
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP822097A
Other languages
Japanese (ja)
Inventor
Hirotake Wakai
洋丈 若井
Makoto Onishi
誠 大西
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Denshi KK
Original Assignee
Hitachi Denshi KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Denshi KK filed Critical Hitachi Denshi KK
Priority to JP822097A priority Critical patent/JPH10209904A/en
Publication of JPH10209904A publication Critical patent/JPH10209904A/en
Pending legal-status Critical Current

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  • Noise Elimination (AREA)

Abstract

PROBLEM TO BE SOLVED: To ensure the stable calls with no increase of the cost by using a wide analog band filter which has its pass areas of all speech channels to perform the A/D conversion after the frequency conversion and to perform the narrow band filter processing via the digital complex signal processing. SOLUTION: The received signal undergoes the frequency conversion into an IF band signal which inputted to an input terminal 1 to undergo the band limitation via a wide band pass filter 9. Then the received signal is multiplied by the DC local oscillation signal produced by an oscillator 4 and a 90-degree phase shifter 5 via the multipliers 3i and 3q. The multiplied signal undergoes the DC detection at a base band, and the detection output is transmitted through the low band pass filters 6i and 6q for elimination of the higher harmonic components. Then the received signal is converted a digital signal by the A/D converters 7i and 7q. The digital signal undergoes the arithmetic processing via a complex processing circuit 10 and then undergoes the narrow band limitation via the digital low band pass filters 11i and 11q. Then the digital signal is demodulated by a demodulator 8 and outputted to an output terminal 15. Thus, no IF filter equalizer is required for correction of the characteristic.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する利用分野】本発明は、ディジタル信号処
理技術を用いて、ディジタル変調信号の復調を行う受信
機に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a receiver for demodulating a digitally modulated signal using a digital signal processing technique.

【0002】[0002]

【従来の技術】従来の受信機の一例を図2のブロック図
を用いて説明する。1は入力端子、2は帯域通過フィル
タ、3iはIF帯信号の同相成分Iの乗算器、3qはIF
帯信号の直交成分Qの乗算器、4は発振器、5は90度移
相器、6iは同相成分の低域通過フィルタ、6qは直交成
分の低域通過フィルタ、7はA/D変換器、8は復調器、
15は出力端子である。受信信号はIF帯の信号に周波数
変換してから入力端子1に入力し、帯域通過フィルタ2で
帯域制限され、発振器4と90度移相器5によって発生し
た直交局部発振信号を乗算器3iと3qによって乗算し、
直交検波を行う。直交検波出力信号の同相成分Iと直交
成分Qは低域通過フィルタ6iと6qに通して高調波成分
を除去したあと、A/D変換器7iと7qでディジタル信
号に変換する。その後復調器8により復調し、出力端子1
5に出力される。
2. Description of the Related Art An example of a conventional receiver will be described with reference to a block diagram of FIG. 1 is an input terminal, 2 is a band-pass filter, 3i is a multiplier of an in-phase component I of an IF band signal, and 3q is an IF
Multiplier for quadrature component Q of band signal, 4 for oscillator, 5 for 90 degree phase shifter, 6i for low-pass filter for in-phase component, 6q for low-pass filter for quadrature component, 7 for A / D converter, 8 is a demodulator,
15 is an output terminal. The received signal is frequency-converted into an IF band signal, input to an input terminal 1, band-limited by a band-pass filter 2, and a quadrature local oscillation signal generated by an oscillator 4 and a 90-degree phase shifter 5 is multiplied by a multiplier 3 i. Multiply by 3q,
Perform quadrature detection. The in-phase component I and the quadrature component Q of the quadrature detection output signal are passed through low-pass filters 6i and 6q to remove harmonic components, and then converted into digital signals by A / D converters 7i and 7q. After that, it is demodulated by demodulator 8 and output terminal 1
Output to 5.

【0003】[0003]

【発明が解決しようとする課題】前述の従来例では、帯
域通過フィルタは狭帯域なアナログフィルタを使用して
いる。しかし、近年では通信需要の増大に伴い通話帯域
幅を狭くする傾向にあり、帯域通過フィルタには平坦な
通過域特性と急峻な遮断特性が要求されるが、通過域が
狭帯域化するほどこれらのフィルタ特性を実現すること
が技術的に困難になる。そのためフィルタの製造コスト
が高くなり、また特性を補正するためのIFフィルタ等
化器が必要となりさらに製造コストが高くなるという問
題がある。また、広い通話チャネルをカバーするため多
数のフィルタを用意しなくてはならず、コストが増大す
るといった問題も生ずる。さらにフィルタの中心周波数
がわずかに変動しても通話困難となるため、回路の安定
度への要求も厳しくなる。
In the above-mentioned conventional example, a narrow-band analog filter is used as the band-pass filter. However, in recent years, the communication bandwidth tends to be narrowed with the increase in communication demand, and a bandpass filter is required to have a flat passband characteristic and a steep cutoff characteristic. It is technically difficult to realize the filter characteristics described above. Therefore, there is a problem that the manufacturing cost of the filter is increased, and an IF filter equalizer for correcting the characteristics is required, and the manufacturing cost is further increased. In addition, a large number of filters must be prepared to cover a wide communication channel, which causes a problem that the cost increases. Further, even if the center frequency of the filter slightly changes, it becomes difficult to talk, so that the requirement for the stability of the circuit becomes severe.

【0004】本発明の目的は、これらの欠点を除去し、
安価で高精度な受信機を提供することである。
[0004] It is an object of the present invention to obviate these disadvantages,
It is to provide an inexpensive and highly accurate receiver.

【0005】[0005]

【課題を解決するための手段】本発明は上記の目的を達
成するために、全通話チャネルを通過域とする広帯域な
アナログ帯域通過フィルタを用い、周波数変換した後A
/D変換し、ディジタル複素信号処理により狭帯域なフ
ィルタ処理を行うことにより受信機を構成したものであ
る。
In order to achieve the above object, the present invention uses a wide-band analog band-pass filter having a pass band for all communication channels, and performs A-to-A conversion after frequency conversion.
The receiver is constructed by performing / D conversion and performing narrow band filter processing by digital complex signal processing.

【0006】[0006]

【発明の実施の形態】以下、本発明の一実施例を図1を
用いて説明する。1は入力端子、9は広帯域通過フィル
タ、3iはIF帯信号の同相成分Iの乗算器、3qはIF
帯信号の直交成分Iの乗算器、4は発振器、5は90度移
相器、6iは同相成分の低域通過フィルタ、6qは直交成
分の低域通過フィルタ、7はA/D変換器、10は複素処
理回路、11iは同相成分のディジタル低域通過フィル
タ、11qは直交成分のディジタル低域通過フィルタ、12
は積分器、13は読込み専用のメモリ(ROM)、8は復
調器、15は出力端子である。受信信号はIF帯の信号に
周波数変換してから入力端子1に入力し、広帯域通過フ
ィルタ9で帯域制限され、発振器4と90度移相器5によ
って発生した直交局部発振信号を乗算器3iと3qによっ
て受信信号に乗算し、ベースバンド帯で直交検波を行
う。直交検波出力は低域通過フィルタ6iと6qに通して
高調波成分を除去したあと、A/D変換器7iと7qでデ
ィジタル信号に変換し、複素処理回路10で複素演算処理
を行い、ディジタル低域通過フィルタ11iと11qで、狭
帯域な帯域制限を行う。その後復調器8により復調し、
出力端子15に出力される。 ここで発振器4は復調器8と
同期がとれておらず、広帯域通過フィルタ9を使用して
いるため、例えば図4のような周波数のずれが生ずる。
このため、復調器8の出力を積分器12を通しROM13に
貯え、複素処理回路10にフィードバックすることによ
り、位相の回転を止め、中心周波数を合わせる準同期検
波により、複素処理出力を得ている。複素処理回路10の
内部構成の一例を図3に示す。複素処理回路10は、乗算
器16i-1,16i-2,16q-1,16q-2と加算器17i,17q
で構成され、その動作は式(1)のようになる。 I´= I cosωt - Q sinωt Q´= Q cosωt + I sinωt …式(1) ここでI´は同相成分の複素処理回路出力、 Q´は直交
成分の複素処理回路出力、Iは同相成分の複素処理回路
入力、 Qは直交成分の複素処理回路入力である。また本
発明の応用例として図1の発振器4を電圧制御発振器で構
成した場合には、復調器8の出力を発振器4にフィードバ
ックすることにより同期をとることができ、複素処理回
路10を省略することができる。以上の動作により、広帯
域なアナログフィルタとディジタル処理による狭帯域な
フィルタ処理の組合わせにより高精度な受信機出力を得
ることが可能となる。なお、前記実施例は直接検波方式
に適用したもので、AM変調波を検波するのに適してい
る。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIG. 1 is an input terminal, 9 is a broadband pass filter, 3i is a multiplier of the in-phase component I of the IF band signal, and 3q is an IF
A multiplier of the quadrature component I of the band signal, 4 is an oscillator, 5 is a 90-degree phase shifter, 6i is a low-pass filter of an in-phase component, 6q is a low-pass filter of a quadrature component, 7 is an A / D converter, 10 is a complex processing circuit, 11i is a digital low-pass filter of an in-phase component, 11q is a digital low-pass filter of a quadrature component, 12
Is an integrator, 13 is a read-only memory (ROM), 8 is a demodulator, and 15 is an output terminal. The received signal is frequency-converted into an IF band signal and then input to the input terminal 1, band-limited by the broadband pass filter 9, and a quadrature local oscillation signal generated by the oscillator 4 and the 90-degree phase shifter 5 is multiplied by the multiplier 3 i Multiply the received signal by 3q and perform quadrature detection in the baseband. The quadrature detection output is passed through low-pass filters 6i and 6q to remove harmonic components, then converted into digital signals by A / D converters 7i and 7q, and subjected to complex arithmetic processing by a complex processing circuit 10 to obtain a digital low-pass signal. Narrow band limitation is performed by the bandpass filters 11i and 11q. Then demodulated by demodulator 8,
Output to the output terminal 15. Here, since the oscillator 4 is not synchronized with the demodulator 8 and uses the wide band pass filter 9, a frequency shift occurs as shown in FIG. 4, for example.
Therefore, the output of the demodulator 8 is stored in the ROM 13 through the integrator 12 and fed back to the complex processing circuit 10 to stop the rotation of the phase and obtain a complex processing output by quasi-synchronous detection that adjusts the center frequency. . FIG. 3 shows an example of the internal configuration of the complex processing circuit 10. As shown in FIG. The complex processing circuit 10 includes multipliers 16i-1, 16i-2, 16q-1, 16q-2 and adders 17i, 17q.
The operation is as shown in equation (1). I ′ = I cosωt-Q sinωt Q ′ = Q cosωt + I sinωt Equation (1) where I ′ is the complex processing circuit output of the in-phase component, Q ′ is the complex processing circuit output of the quadrature component, and I is the Complex processing circuit input, Q is the complex processing circuit input of the orthogonal component. When the oscillator 4 of FIG. 1 is configured as a voltage-controlled oscillator as an application example of the present invention, synchronization can be achieved by feeding back the output of the demodulator 8 to the oscillator 4, and the complex processing circuit 10 is omitted. be able to. With the above operation, a high-accuracy receiver output can be obtained by a combination of a wideband analog filter and a narrowband filter processing by digital processing. The above embodiment is applied to a direct detection system, and is suitable for detecting an AM modulated wave.

【0007】次に本発明の第二の実施例を、図5を用い
て説明する。図5はヘテロダイン検波方式に本発明を適
用した一例で、1は入力端子、9は広帯域通過フィルタ、
3iはIF帯信号の同相成分Iの乗算器、3qはIF帯信
号の直交成分Iの乗算器、4は発振器、5は90度移相
器、6iは同相成分の低域通過フィルタ、6qは直交成分
の低域通過フィルタ、7iと7qはA/D変換器、14は複
素ディジタルフィルタ、8は復調器、15は出力端子であ
る。受信信号はIF帯の信号に周波数変換してから入力
端子1に入力し、広帯域通過フィルタ9で帯域制限する。
発振器4と90度移相器5によって発生した直交局部発振
信号を乗算器3iと3qによって受信信号に乗算し、ベー
スバンド帯で直交検波を行う。この直交検波出力は低域
通過フィルタ6iと6qを通して高調波成分を除去したあ
と、A/D変換器7iと7qでディジタル信号に変換し、
複素ディジタルフィルタ14によりフィルタ処理を行う。
複素ディジタルフィルタ14の構成の一例を図6に示す。1
7i〜26iと17q〜26qは乗算器で、27i〜29iと27q
〜29qは加算器で、30i〜33iと30q〜33qは遅延レジ
スタである。フィルタ処理を式で表すと、次の式(2)の
ようになる。 YI=HRI-HIQ YQ=HRQ+HII …式(2) ここで、 YI、YQ:ディジタル複素フィルタ出力、 HI、HR:フィルタ係数、 I 、Q :フィルタ入力信号 である。図6の複素ディジタルフィルタ14の動作を図7、
図8、図9、図10のスペクトル図を用いて説明する。図7
は、複素フィルタ処理前の信号、つまりA/D変換器7
iと7qの出力IとQである。ここで周波数fcと周波数
-fcに信号が現れているが、求める信号は一方だけ(こ
こでは +fcの成分とする)で -fcの成分はイメージ妨害
信号となる。このイメージ妨害を除去するには、図9に
示すような正の周波数域にのみ通過域を持つ複素係数フ
ィルタが必要である。この複素係数フィルタは、図8の
ような実係数フィルタの周波数特性を+fcだけ周波数シ
フトすることにより得られる。図8のフィルタを、式で
表すと次の式(3)のようになる。 H0(Z)=a0+a1Z-1+a2Z-2+・・・+anZ-n ( a0〜 an):フィルタ係数 …式(3) ここで Z= ej2πf/fs (fs:サンプリング周波数)で
ある。フィルタの中心周波数をfc´とすると、fc´をfc
にシフトするためfc´を基準とする周波数fは(f-fc)に
シフトされる。よって Z = ej2π(f-fc)/fs = ej2πf/fs ・ e-j2πfc/fs = Z・e-j2πfc/fs = Z・α (fs:サンプリング周波数) …式(4) ここで、α= e-j2πfc/fsは絶対値が1の複素数であ
る。式(4)を式(3)に代入して整理すると H0(Z)=a0+a1α-1Z-1+a2α-2Z-2+・・・+anα-nZ-n =HR0+jHI0+(HR1+jHI1)Z-1+(HR2+jHI2)Z-2+・・・+(HRn+jHIn)Z-n …式(5) となり、複素係数フィルタが得られる。この複素係数フ
ィルタの構成を示す図が図6である。また、周波数シフ
トされた複素ディジタルフィルタの周波数特性が図9で
ある。複素フィルタであるため通過域は正負周波数のど
ちらか一方(図9では正の周波数側)だけとなる。図10
は、複素ディジタルフィルタの出力でイメージ妨害成分
は複素フィルタで除去されている。アナログフィルタを
広帯域にしているため、IF信号にはイメージ妨害成分
が重なるが、複素ディジタルフィルタ処理により、この
イメージ妨害成分を除去し、かつ狭帯域なフィルタリン
グが可能となる。なお、この実施例は、FM変調波を検
波するのに適している。
Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 5 is an example in which the present invention is applied to a heterodyne detection system, where 1 is an input terminal, 9 is a broadband pass filter,
3i is a multiplier of the in-phase component I of the IF band signal, 3q is a multiplier of the quadrature component I of the IF band signal, 4 is an oscillator, 5 is a 90-degree phase shifter, 6i is a low-pass filter of the in-phase component, 6q is A quadrature component low-pass filter, 7i and 7q are A / D converters, 14 is a complex digital filter, 8 is a demodulator, and 15 is an output terminal. The received signal is frequency-converted into an IF band signal, input to the input terminal 1, and band-limited by the wide band pass filter 9.
The received signals are multiplied by the quadrature local oscillation signals generated by the oscillator 4 and the 90-degree phase shifter 5 by the multipliers 3i and 3q, and quadrature detection is performed in the baseband. The quadrature detection output is subjected to low-pass filters 6i and 6q to remove harmonic components, and then converted to digital signals by A / D converters 7i and 7q.
Filter processing is performed by the complex digital filter 14.
An example of the configuration of the complex digital filter 14 is shown in FIG. 1
7i-26i and 17q-26q are multipliers, 27i-29i and 27q
29q to 30q are adders, and 30i to 33i and 30q to 33q are delay registers. When the filter processing is expressed by an equation, the following equation (2) is obtained. Y I = H R IH I QY Q = H R Q + H I I ... Equation (2) where Y I , Y Q : digital complex filter output, H I , H R : filter coefficients, I, Q: filter This is the input signal. The operation of the complex digital filter 14 of FIG.
This will be described with reference to the spectrum diagrams of FIGS. 8, 9, and 10. Fig. 7
Is the signal before complex filtering, that is, the A / D converter 7
Outputs I and Q of i and 7q. Where frequency fc and frequency
Although a signal appears at -fc, only one signal is required (here, the component of + fc) and the component of -fc is an image interference signal. In order to remove this image disturbance, a complex coefficient filter having a pass band only in a positive frequency band as shown in FIG. 9 is required. This complex coefficient filter is obtained by frequency-shifting the frequency characteristic of a real coefficient filter as shown in FIG. 8 by + fc. The filter of FIG. 8 is expressed by the following expression (3). H 0 (Z) = a 0 + a 1 Z -1 + a 2 Z -2 + ... + anZ -n (a 0 to an): Filter coefficient ... Equation (3) where Z = e j2πf / fs (Fs: sampling frequency). Assuming that the center frequency of the filter is fc ′, fc ′ is fc
, The frequency f based on fc ′ is shifted to (f−fc). Therefore, Z = e j2π (f-fc) / fs = e j2πf / fs・ e -j2πfc / fs = Z ・ e -j2πfc / fs = Z ・ α (fs: sampling frequency)… Equation (4) where α = e -j2πfc / fs is a complex number whose absolute value is 1. Substituting equation (4) into equation (3) and rearranging, H 0 (Z) = a 0 + a 1 α -1 Z -1 + a 2 α -2 Z -2 + ... + anα -n Z -n = H R0 + jH I0 + (H R1 + jH I1 ) Z -1 + (H R2 + jH I2 ) Z -2 + ... + (H R n + jH I n) Z -n ... 5) and a complex coefficient filter is obtained. FIG. 6 shows a configuration of the complex coefficient filter. FIG. 9 shows the frequency characteristics of the frequency-shifted complex digital filter. Since this is a complex filter, the pass band is only one of the positive and negative frequencies (the positive frequency side in FIG. 9). FIG.
Is an output of the complex digital filter, and the image interference component is removed by the complex filter. Since the analog filter has a wide band, an image interference component overlaps with the IF signal, but the complex digital filter processing removes the image interference component and enables narrow-band filtering. This embodiment is suitable for detecting an FM modulated wave.

【0008】以上のように、ディジタルフィルタで狭帯
域フィルタを実現することは、周波数変換後のサンプリ
ング周波数がそれほど高くなければ、容易である。また
1度設計した後はアナログ回路のような調整作業は不要
で、コストがほとんどかからない。
As described above, it is easy to realize a narrow band filter using a digital filter if the sampling frequency after frequency conversion is not so high. Further, after designing once, adjustment work such as an analog circuit is unnecessary, and the cost is hardly required.

【0009】[0009]

【発明の効果】本発明によれば、広帯域なアナログフィ
ルタを用い、A/D変換後、狭帯域なディジタルフィル
タ処理をすることにより、コストが大幅に削減できる受
信機が実現できる。
According to the present invention, a receiver capable of greatly reducing costs can be realized by performing narrow-band digital filter processing after A / D conversion using a wide-band analog filter.

【図面の簡単な説明】[Brief description of the drawings]

【図1】 本発明の一実施例を示すブロック図FIG. 1 is a block diagram showing an embodiment of the present invention.

【図2】 従来の技術を示すブロック図FIG. 2 is a block diagram showing a conventional technique.

【図3】 複素処理回路の一実施例を示す内部構造図FIG. 3 is an internal structural diagram showing one embodiment of a complex processing circuit;

【図4】 中心周波数のずれによるベースバンド信号の
一実施例を示すスペクトル図
FIG. 4 is a spectrum diagram showing an embodiment of a baseband signal due to a shift of a center frequency.

【図5】 本発明の一実施例を示すブロック図FIG. 5 is a block diagram showing one embodiment of the present invention.

【図6】 複素ディジタルフィルタの内部構造の一実施
例を示すブロック図
FIG. 6 is a block diagram showing an embodiment of the internal structure of a complex digital filter.

【図7】 A/D変換器からの出力信号の一例を示すス
ペクトル図
FIG. 7 is a spectrum diagram showing an example of an output signal from an A / D converter.

【図8】 複素ディジタルフィルタの周波数特性(ベー
スバンド帯)の一例を示すスペクトル図
FIG. 8 is a spectrum diagram showing an example of a frequency characteristic (baseband) of a complex digital filter.

【図9】 周波数シフト後の複素ディジタルフィルタの
周波数特性の一例を示すスペクトル図
FIG. 9 is a spectrum diagram showing an example of the frequency characteristic of the complex digital filter after the frequency shift.

【図10】 複素ディジタルフィルタの出力信号の一例
を示すスペクトル図
FIG. 10 is a spectrum diagram showing an example of an output signal of a complex digital filter.

【符号の説明】[Explanation of symbols]

1:入力端子、 2:帯域通過フィルタ、 3i,3q:乗
算器、 4:発振器、5:90度移相器、 6i,6q:低
域通過フィルタ、 7i,7q:A/D変換器、 8:復
調器、 9:広帯域通過フィルタ、 10:複素処理回
路、 11i,11q:ディジタル低域通過フィルタ、 1
2:積分器、 13:ROM、 14:複素ディジタルフィ
ルタ、 15:受信機出力、 16i-1,16i-2,16q-1,
16q-2:乗算器 、 17i〜26i,17q〜26q:乗算
器、 27i〜29i,27q〜29q:加算器、 30i〜33
i、30q〜33q:遅延レジスタ。
1: input terminal, 2: band-pass filter, 3i, 3q: multiplier, 4: oscillator, 5: 90-degree phase shifter, 6i, 6q: low-pass filter, 7i, 7q: A / D converter, 8 : Demodulator, 9: wide band pass filter, 10: complex processing circuit, 11i, 11q: digital low pass filter, 1
2: integrator, 13: ROM, 14: complex digital filter, 15: receiver output, 16i-1, 16i-2, 16q-1,
16q-2: Multiplier, 17i-26i, 17q-26q: Multiplier, 27i-29i, 27q-29q: Adder, 30i-33
i, 30q to 33q: delay register.

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 全通話チャネルが通過域となるアナログ
広帯域通過フィルタに受信信号を通し、直交した局発信
号を乗算して、直交する中間周波信号に周波数変換し、
A/D変換したあと、ディジタル的に狭帯域フィルタ処
理を行い、復調出力を得ることを特徴とした受信機。
1. A reception signal is passed through an analog wide band pass filter in which all communication channels are in a pass band, multiplied by orthogonal local signals, and frequency-converted into orthogonal intermediate frequency signals.
A receiver characterized in that after performing A / D conversion, digital narrow band filtering is performed to obtain a demodulated output.
【請求項2】 請求項1記載の受信機において、A/D
変換後に複素演算処理を行い、前記直交する中間周波信
号に周波数変換する際に生ずる周波数ずれを補正するこ
とを特徴とした受信機。
2. The receiver according to claim 1, wherein the A / D
A receiver which performs complex arithmetic processing after the conversion to correct a frequency shift generated when the frequency is converted to the orthogonal intermediate frequency signal.
【請求項3】 請求項1記載の受信機において、中間周
波数に周波数変換した信号を複素ディジタルフィルタに
よりフィルタ処理を行い、イメージ妨害成分を除去し復
調出力を得ることを特徴とした受信機。
3. The receiver according to claim 1, wherein a signal subjected to frequency conversion to an intermediate frequency is filtered by a complex digital filter to remove an image interference component and obtain a demodulated output.
【請求項4】 IF帯の信号に周波数変換され受信信号
を入力する入力端子と、該入力端子に入力した受信信号
の全通話チャネルが通過域となるアナログ広帯域フィル
タと、該フィルタ通過後の信号を直交検波するための発
振器および90度移相器ならびに同相成分,直交成分2
つの乗算器と、該乗算器により検波された同相成分と直
交成分の信号の高調波成分を除去するための同相成分,
直交成分各々の低域通過フィルタと、該低域通過フィル
タを通過した信号を各々ディジタル変換するためのA/
D変換器と、該A/D変換器からの同相,直交ディジタ
ル信号を複素処理する複素処理回路と、該複素回路によ
り処理された同相成分,直交成分各々のディジタル信号
を単通話チャネル毎に選択する同相,直交各々の狭帯域
のディジタル低域通過フィルタと、該両フィルタから出
力される帯域制限された信号を復調して出力する復調器
と、該復調器の出力を積分する積分器と、該積分器の出力
に対応する位相情報データを読出し、前記複素処理回路
に出力するROMとを有し、該位相情報データにより前
記複素処理回路の位置補正を行う構成としたことを特徴
とする受信機。
4. An input terminal for inputting a reception signal which is frequency-converted into an IF band signal, an analog wideband filter having a pass band for all communication channels of the reception signal input to the input terminal, and a signal after passing through the filter. Oscillator and 90-degree phase shifter for quadrature detection of in-phase and quadrature components 2
Two multipliers, an in-phase component for removing harmonic components of the in-phase component and the quadrature component signal detected by the multiplier,
A low-pass filter for each of the orthogonal components, and an A /
A D converter, a complex processing circuit for performing complex processing on the in-phase and quadrature digital signals from the A / D converter, and selecting digital signals of the in-phase and quadrature components processed by the complex circuit for each single communication channel An in-phase and quadrature narrow-band digital low-pass filter, a demodulator for demodulating and outputting a band-limited signal output from both filters, an integrator for integrating the output of the demodulator, A ROM for reading phase information data corresponding to the output of the integrator and outputting the read data to the complex processing circuit, wherein the position of the complex processing circuit is corrected based on the phase information data. Machine.
JP822097A 1997-01-21 1997-01-21 Receiver Pending JPH10209904A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP822097A JPH10209904A (en) 1997-01-21 1997-01-21 Receiver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP822097A JPH10209904A (en) 1997-01-21 1997-01-21 Receiver

Publications (1)

Publication Number Publication Date
JPH10209904A true JPH10209904A (en) 1998-08-07

Family

ID=11687128

Family Applications (1)

Application Number Title Priority Date Filing Date
JP822097A Pending JPH10209904A (en) 1997-01-21 1997-01-21 Receiver

Country Status (1)

Country Link
JP (1) JPH10209904A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7146148B2 (en) 2002-10-01 2006-12-05 Hitachi Kokusai Electric Inc. Low intermediate frequency type receiver
US7336717B2 (en) 2000-09-08 2008-02-26 Infineon Technologies Ag Receiver circuit, in particular for a mobile radio
JP2008167000A (en) * 2006-12-27 2008-07-17 Nec Electronics Corp Receiving device
KR100950648B1 (en) 2002-04-04 2010-04-01 삼성전자주식회사 Apparatus of Suppressing Imaginary Signal
JP2012163543A (en) * 2010-09-30 2012-08-30 Daihen Corp Frequency detector

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7336717B2 (en) 2000-09-08 2008-02-26 Infineon Technologies Ag Receiver circuit, in particular for a mobile radio
KR100950648B1 (en) 2002-04-04 2010-04-01 삼성전자주식회사 Apparatus of Suppressing Imaginary Signal
US7146148B2 (en) 2002-10-01 2006-12-05 Hitachi Kokusai Electric Inc. Low intermediate frequency type receiver
JP2008167000A (en) * 2006-12-27 2008-07-17 Nec Electronics Corp Receiving device
JP4731462B2 (en) * 2006-12-27 2011-07-27 ルネサスエレクトロニクス株式会社 Receiver
JP2012163543A (en) * 2010-09-30 2012-08-30 Daihen Corp Frequency detector

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