JPH10209323A - Semiconductor device, its fixing method and semiconductor device mounting structure - Google Patents
Semiconductor device, its fixing method and semiconductor device mounting structureInfo
- Publication number
- JPH10209323A JPH10209323A JP1033997A JP1033997A JPH10209323A JP H10209323 A JPH10209323 A JP H10209323A JP 1033997 A JP1033997 A JP 1033997A JP 1033997 A JP1033997 A JP 1033997A JP H10209323 A JPH10209323 A JP H10209323A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- printed wiring
- wiring board
- contacts
- mounting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体装置に係
り、特に印刷配線板に搭載され、該印刷配線板の配線と
接続されるＱＦＰ（Ｑｕａｄ Ｆｌａｔ Ｐａｃｋａｇ
ｅ），ＢＧＡ（Ｂａｌｌ Ｇｒｉｄ Ａｒｒａｙ）等の
表面実装タイプの半導体装置、その固定方法及び半導体
装置の実装構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a QFP (Quad Flat Package) mounted on a printed wiring board and connected to wiring of the printed wiring board.
e), a surface-mounted type semiconductor device such as a BGA (Ball Grid Array), a method for fixing the same, and a mounting structure of the semiconductor device.
【０００２】[0002]
【従来の技術】半導体パッケージで多ピン化を図る際に
図１に示すようなリード（ピン）１がデバイスパッケー
ジ３の周辺に複数個、配置されたペリフェラル構造のＱ
ＦＰ等の半導体装置１０で実現するのにピンピッチ２を
狭くするか、デバイスパッケージ３のサイズを大型化す
ることにより行われている。2. Description of the Related Art In order to increase the number of pins in a semiconductor package, a plurality of leads (pins) 1 as shown in FIG.
In order to realize the semiconductor device 10 such as an FP, the pin pitch 2 is reduced or the size of the device package 3 is increased.
【０００３】また図２に示すＢＧＡのように印刷配線板
２１の上面に固定された半導体チップ２２が樹脂モール
ドされ、印刷配線板２１の下面に前記半導体チップ２２
上面に形成された回路と導通する複数の接点としての半
田ボール２３が配設されてなる半導体装置２２で多ピン
化を図るには半田ボール２３が配設されるピッチ間隔を
短くすることにより行われている。A semiconductor chip 22 fixed on the upper surface of a printed wiring board 21 is resin-molded like a BGA shown in FIG.
To increase the number of pins in a semiconductor device 22 having a plurality of solder balls 23 as a plurality of contacts electrically connected to a circuit formed on the upper surface, the pitch between the solder balls 23 is reduced by reducing the pitch interval. Have been done.
【０００４】上述した半導体装置では、半導体装置側の
電極と半導体装置が搭載される半導体装置搭載用印刷配
線板側の電極部とがリードと称する金属リードあるは、
半田ボールを介して直接、接続されることにより使用さ
れる。その際にペースト状の半田を接着剤として利用
し、加熱溶解接続する点で共通する。In the above-described semiconductor device, the electrodes on the semiconductor device side and the electrode portions on the printed wiring board side for mounting the semiconductor device on which the semiconductor device is mounted are metal leads or leads.
It is used by being directly connected via a solder ball. At this time, the method is common in that a paste-like solder is used as an adhesive and is connected by heating and melting.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、リード
がペリフェラル構造のＱＦＰ等の半導体装置でピンピッ
チを狭くすることにより多ピン化を図る場合には、半導
体装置のリード接続部の小型化、要求される搭載精度の
高精度化により半導体装置の半導体装置搭載用印刷配線
板への接続搭載品質が低下するという問題があった。However, in the case where the number of pins is reduced by narrowing the pin pitch in a semiconductor device such as a QFP having a peripheral structure, the lead is required to be reduced in the size of the lead connection portion of the semiconductor device. There has been a problem that the quality of connection and mounting of a semiconductor device to a printed wiring board for mounting a semiconductor device is degraded due to higher mounting accuracy.
【０００６】またパッケージサイズを大型化することに
より多ピン化を図る場合には半導体装置が搭載される半
導体装置搭載用印刷配線板上の占有面積が大きくなり、
半導体装置を含む部品の高密度集約実装が困難になると
いう問題があった。In order to increase the number of pins by enlarging the package size, the area occupied by the printed wiring board for mounting the semiconductor device becomes large.
There has been a problem that high-density intensive mounting of components including a semiconductor device becomes difficult.
【０００７】一方、ＢＧＡのような半導体装置において
半田ボールが配設されるピッチ間隔を短くすることによ
り多ピン化を図る場合にはパッケージ下面、すなわち半
導体チップが固定される印刷配線板の下面に電極が集中
するために電極からの配線の引出し効率が悪化する。す
なわち、印刷配線板の平面方向の配線のみでは配線容量
が不足し、印刷配線板を多層化し、その上下方向の配線
をバイアホール等で繋ぐ多層印刷配線板の利用が必要と
なる。On the other hand, in a semiconductor device such as a BGA, in order to increase the number of pins by shortening a pitch interval at which solder balls are provided, a lower surface of a package, that is, a lower surface of a printed wiring board to which a semiconductor chip is fixed is mounted. Since the electrodes are concentrated, the wiring extraction efficiency from the electrodes is reduced. That is, the wiring capacity is insufficient only with the wiring in the planar direction of the printed wiring board, and it is necessary to use a multilayer printed wiring board in which the printed wiring boards are multilayered and the wirings in the vertical direction are connected by via holes or the like.
【０００８】しかしながら、多層印刷配線板を採用する
と、印刷配線板実装体のコスト上昇を招くという問題が
ある。However, when a multilayer printed wiring board is used, there is a problem that the cost of the printed wiring board mounting body is increased.
【０００９】更にＢＧＡのような半導体装置を使用する
際に放熱フィン、ヒートシンク等の放熱部材をＢＧＡの
ような半導体装置に装着し、あるいはＢＧＡのような半
導体装置に複数部品を搭載してモジュール化することに
より半導体装置に対する荷重が増加した場合に、これら
を半導体装置搭載用印刷配線板に搭載すると、接続支持
体となっている半田ボールが、リフロー熱等による溶解
接続時に潰れてしまい、半導体装置搭載用印刷配線板上
に形成された電極間を短絡する等の接続不良を発生させ
てしまう虞れがあるという問題がある。Further, when a semiconductor device such as a BGA is used, a heat radiating member such as a heat radiation fin or a heat sink is mounted on the semiconductor device such as the BGA, or a plurality of components are mounted on the semiconductor device such as the BGA to form a module. When the load on the semiconductor device increases due to this, when these are mounted on the printed wiring board for mounting the semiconductor device, the solder balls serving as the connection support are crushed at the time of melting connection by reflow heat or the like, and the semiconductor device is There is a problem that a connection failure such as a short circuit between electrodes formed on the mounting printed wiring board may occur.
【００１０】本発明はこのような事情に鑑みてなされた
ものであり、高密度多ピン化を図った半導体装置を提供
することを第１の目的とする。[0010] The present invention has been made in view of such circumstances, and a first object of the present invention is to provide a semiconductor device with high density and high pin count.
【００１１】また本発明は、半導体装置搭載用印刷配線
板に搭載される際の半田ボール等の接点溶解接続時に接
点の潰れによる接続不良の発生の防止を図った半導体装
置を提供することを第２の目的とする。Another object of the present invention is to provide a semiconductor device which prevents connection failure due to crushing of contacts at the time of melting and connecting contacts such as solder balls when mounted on a printed wiring board for mounting semiconductor devices. This is the purpose of 2.
【００１２】本発明は、部品から発生する放射ノイズの
抑制を図った半導体装置を提供することを第３の目的と
する。A third object of the present invention is to provide a semiconductor device which suppresses radiation noise generated from components.
【００１３】また本発明は、部品の搭載効率の向上及び
接点の潰れの防止を図った半導体装置の実装構造を提供
することを第４の目的とする。It is a fourth object of the present invention to provide a semiconductor device mounting structure which improves the mounting efficiency of components and prevents the contact from being crushed.
【００１４】更に本発明は、加工工数の低減及び実装領
域の増大を図った半導体装置の固定方法を提供すること
を第５の目的とする。It is a fifth object of the present invention to provide a method of fixing a semiconductor device which reduces the number of processing steps and increases the mounting area.
【００１５】[0015]
【課題を解決するための手段】第１の目的を達成するた
めに請求項１に記載の発明は、印刷配線板の上面に固定
された半導体チップを樹脂モールドし、前記半導体チッ
プ上面に形成された回路と導通する複数のリードが前記
印刷配線板の周囲に配設すると共に、前記半導体チップ
上面に形成された回路と導通する複数の接点を前記印刷
配線板の下面に配設したことを特徴とする。According to a first aspect of the present invention, a semiconductor chip fixed to an upper surface of a printed wiring board is resin-molded and formed on the upper surface of the semiconductor chip. A plurality of leads electrically connected to the printed circuit board are provided around the printed wiring board, and a plurality of contacts electrically connected to a circuit formed on the upper surface of the semiconductor chip are provided on the lower surface of the printed wiring board. And
【００１６】請求項１に記載の発明によれば、高密度多
ピン化を図った半導体装置を実現できる。According to the first aspect of the present invention, it is possible to realize a semiconductor device with high density and high pin count.
【００１７】第２の目的を達成するために請求項２に記
載の発明は、請求項１に記載の半導体装置において、前
記印刷配線板の下面から前記リードの下端の延長線上ま
での垂直距離が前記接点の高さより僅かに短かくなるよ
うにしたことを特徴とする。According to a second aspect of the present invention, there is provided a semiconductor device according to the first aspect, wherein a vertical distance from a lower surface of the printed wiring board to an extension line of a lower end of the lead is provided. The height of the contact is slightly shorter than the height of the contact.
【００１８】請求項２に記載の発明によれば、ペリフェ
ラル構造の印刷配線板の下面から前記リードの下端の延
長線上までの垂直距離が前記接点の高さより僅かに短か
くなるようにした複数のリードを設けることにより、半
導体装置搭載用印刷配線板に半導体装置を搭載する際に
リフロー熱による接点の加熱溶解時に接点に過度に荷重
がかからないように前記リードにより半導体装置本体が
支持されるために接点の潰れによる電極間ショート等の
接続不良を防止することができる。According to the second aspect of the present invention, the plurality of vertical distances from the lower surface of the printed wiring board having the peripheral structure to the extension of the lower end of the lead are slightly shorter than the height of the contact. By providing the lead, when mounting the semiconductor device on the printed wiring board for mounting the semiconductor device, the semiconductor device body is supported by the lead so that the contact is not excessively loaded when the contact is heated and melted by reflow heat. It is possible to prevent connection failure such as short-circuit between electrodes due to crushing of the contact.
【００１９】第３の目的を達成するために請求項３に記
載の発明は、請求項１に記載の半導体装置において、前
記印刷配線板の周囲に配設された前記複数のリードのう
ちの特定のリードに電源ライン及びグランドラインを接
続し、前記複数の接点に信号ラインを接続することを特
徴とする。According to a third aspect of the present invention, there is provided a semiconductor device as set forth in the first aspect, wherein the plurality of leads are arranged around the printed wiring board. A power line and a ground line are connected to the lead, and a signal line is connected to the plurality of contacts.
【００２０】請求項３に記載の発明によれば、部品から
発生する放射ノイズを外側のリードでシールドすること
により抑制することができる。According to the third aspect of the present invention, radiation noise generated from the component can be suppressed by shielding the noise with the outer leads.
【００２１】第４の目的を達成するために請求項４に記
載の発明は、印刷配線板の上面に固定された半導体チッ
プを樹脂モールドし、印刷配線板の下面に前記半導体チ
ップ上面に形成された回路と導通する複数の接点が配設
された半導体装置を、前記複数の接点に対向して形成さ
れた複数の電極を有する半導体装置搭載用印刷配線板の
所定の電極位置に前記複数の接点を載置し、接続するこ
とにより搭載する際に、前記複数の接点のうちの特定の
接点の代わりに前記接点の高さより僅かに短い高さを有
する受動素子を介在させたことを特徴とする。According to a fourth aspect of the present invention, a semiconductor chip fixed to an upper surface of a printed wiring board is resin-molded and formed on the upper surface of the semiconductor chip on a lower surface of the printed wiring board. A semiconductor device provided with a plurality of contacts electrically connected to a plurality of contacts, the plurality of contacts being provided at predetermined electrode positions of a semiconductor device mounting printed wiring board having a plurality of electrodes formed to face the plurality of contacts. When mounting by mounting and connecting, a passive element having a height slightly shorter than the height of the contact is interposed instead of a specific contact of the plurality of contacts. .
【００２２】請求項４に記載の発明によれば、部品の搭
載効率の向上及びボール状接点の潰れの防止を図った半
導体装置の実装構造を実現できる。According to the fourth aspect of the present invention, it is possible to realize a mounting structure of a semiconductor device in which the mounting efficiency of components is improved and the ball-shaped contact is prevented from being crushed.
【００２３】第５の目的を達成するために請求項５に記
載の発明は、印刷配線板の上面に固定された半導体チッ
プを樹脂モールドし、印刷配線板の下面に前記半導体チ
ップ上面に形成された回路と導通する複数の接点が配設
された半導体装置を半導体装置搭載用印刷配線板に固定
する際に、前記半導体装置の周縁部と前記半導体装置搭
載用印刷配線板とを受動素子を介して固定することを特
徴とする。According to a fifth aspect of the present invention, a semiconductor chip fixed to an upper surface of a printed wiring board is resin-molded and formed on the upper surface of the semiconductor chip on a lower surface of the printed wiring board. When fixing a semiconductor device provided with a plurality of contacts conducting to a circuit to a printed wiring board for mounting a semiconductor device, a peripheral portion of the semiconductor device and the printed wiring board for mounting a semiconductor device are connected via a passive element. Fixed.
【００２４】請求項５に記載の発明によれば、本来、半
導体装置内あるいは半導体装置搭載用印刷配線板の別の
領域に実装すべき受動素子を、半導体装置を半導体装置
搭載用印刷配線板に搭載するために固定する際に、半導
体装置の周縁部と半導体装置搭載用印刷配線板との間に
介在させて行うようにしたので、加工工数の低減及び実
装領域の増大が図れる。According to the fifth aspect of the present invention, the passive element to be originally mounted in the semiconductor device or in another region of the printed wiring board for mounting the semiconductor device is replaced with the passive device to be mounted on the printed wiring board for mounting the semiconductor device. When the semiconductor device is fixed for mounting, the semiconductor device is interposed between the peripheral portion of the semiconductor device and the printed wiring board for mounting the semiconductor device, so that the number of processing steps can be reduced and the mounting area can be increased.
【００２５】[0025]
【発明の実施の形態】以下、本発明の実施の形態を図面
を参照して説明する。本発明の第１の実施の形態に係る
半導体装置の構成を図３に示す。半導体装置の印刷配線
板２１の上面は、複数のリード３１と導通する複数の印
刷配線２６が形成されており、印刷配線板２１の下面に
は、複数の印刷配線２６と導通する正方形で銅製の複数
の電極２７が等間隔で配設されている。半導体装置は、
印刷配線板２１上面の複数の印刷配線２６間に半導体チ
ップ２２をマウントし、半導体チップ２２上面に形成さ
れた回路に接続されているパッド２４と印刷配線２６と
をボンディングワイア２５でボンディングし、印刷配線
板２１上に固定された半導体チップ２２を樹脂２８によ
りモールドすることにより構成されている。これにより
半導体チップ２２上面に形成された回路とパッド２４、
ボンディングワイア２５、印刷配線２６、電極２７を介
して導通する複数のリード３１が印刷配線板２１の周囲
に配設される。Embodiments of the present invention will be described below with reference to the drawings. FIG. 3 shows the configuration of the semiconductor device according to the first embodiment of the present invention. On the upper surface of the printed wiring board 21 of the semiconductor device, a plurality of printed wirings 26 which are electrically connected to the plurality of leads 31 are formed, and on the lower surface of the printed wiring board 21, a square copper-made electrically conductive with the plurality of printed wirings 26 is formed. A plurality of electrodes 27 are arranged at equal intervals. Semiconductor devices
The semiconductor chip 22 is mounted between the plurality of printed wirings 26 on the upper surface of the printed wiring board 21, and the pads 24 connected to the circuits formed on the upper surface of the semiconductor chip 22 and the printed wirings 26 are bonded by bonding wires 25, and printed. The semiconductor chip 22 fixed on the wiring board 21 is molded by a resin 28. As a result, the circuit formed on the upper surface of the semiconductor chip 22 and the pad 24,
A plurality of leads 31 that conduct through the bonding wire 25, the printed wiring 26, and the electrodes 27 are provided around the printed wiring board 21.
【００２６】また半導体チップ２２上面に形成された回
路とパッド２４、ボンディングワイア２５、印刷配線２
６、電極２７を介して導通する複数の接点としての半田
ボール２３が印刷配線板２１の下面に配設されている。
この半田ボール等の接点の形成は、予め準備された球状
の半田合金及び金等の単独金属を接着剤を使用して、あ
るいはリフロー溶解等により接着する方法、またはペー
スト印刷等によって接点を作り込んでいく方法のいずれ
によっても可能である。接点の形状は、ボール状に限ら
ず、円柱状、つずみ状、太鼓状のいずれでもよい。The circuit formed on the upper surface of the semiconductor chip 22, the pad 24, the bonding wire 25, the printed wiring 2
6. Solder balls 23 are provided on the lower surface of the printed wiring board 21 as a plurality of contacts that conduct through the electrodes 27.
The contact such as a solder ball is formed by a method in which a prepared spherical solder alloy and a single metal such as gold are bonded using an adhesive, by reflow melting, or the like, or by paste printing. It is possible by any of the following methods. The shape of the contact is not limited to the ball shape, but may be any of a columnar shape, a conical shape, and a drum shape.
【００２７】このように図１に外観構成を示すＱＦＰ，
ＳＯＰ（Ｓｍａｌｌ Ｏｕｔｌｉｎｅ Ｐａｃｋａｇ
ｅ），ＰＬＣＣ（Ｐｌａｓｔｉｃｓ Ｌｅａｄｌｅｓｓ
Ｃｈｉｐ Ｃａｒｒｉｅｒ）等の半導体チップが固定
される印刷配線板の周囲にリードを引き出す構造の半導
体装置に対しては上記印刷配線板の下面に複数の接点と
しての半田ボールを例えば、マトリクス状に配設するこ
とにより高密度多ピン化を図ることができる。As described above, the QFP, whose external configuration is shown in FIG.
SOP (Small Outline Package)
e), PLCC (Plastics Leadless)
For a semiconductor device having a structure in which leads are drawn around a printed wiring board on which a semiconductor chip such as a chip carrier is fixed, solder balls as a plurality of contacts are arranged on the lower surface of the printed wiring board, for example, in a matrix. By doing so, it is possible to increase the density and the number of pins.
【００２８】また図２に示すようにＢＧＡ等のような半
導体装置に、半導体チップ２２上面に形成された回路と
導通する複数のリード３１を印刷配線板２１の周囲にカ
シメ等により接続してペリフェラル構造に配設すること
により高密度多ピン化を図ることができる。ここで印刷
配線板２１の周囲に配置されるリードの形状は、ＱＦ
Ｐ，ＳＯＰに代表されるＧull Ｗing 形状、またはＰＬ
ＣＣに代表されるようなＪ型形状のいずれであってもよ
い。図３に示す半導体装置の裏面から見た部品構造を図
４に示す。同図に示すように印刷配線板２１の周囲に接
続されたリード３１と印刷配線板２１の底面にマトリク
ス状に形成された複数の接点としての半田ボール２３が
混在した半導体装置となる。As shown in FIG. 2, a plurality of leads 31 electrically connected to a circuit formed on the upper surface of the semiconductor chip 22 are connected to the periphery of the printed circuit board 21 by caulking or the like to a semiconductor device such as a BGA. By arranging them in a structure, it is possible to increase the density and the number of pins. Here, the shape of the lead arranged around the printed wiring board 21 is QF
Gull Wing shape represented by P, SOP, or PL
Any of the J-shaped shapes represented by CC may be used. FIG. 4 shows a component structure as viewed from the back surface of the semiconductor device shown in FIG. As shown in the figure, a semiconductor device in which leads 31 connected around the printed wiring board 21 and solder balls 23 as a plurality of contacts formed in a matrix on the bottom surface of the printed wiring board 21 are mixed.
【００２９】図３に示す半導体装置３０において、複数
のリード３１のうちの特定のリードに電源ライン及びグ
ランドラインを接続し、複数の接点としての半田ボール
に信号ラインを接続するようにしている。このように構
成することにより、信号ライン発生するから発生する放
射ノイズを上記半田ボールの外側に位置するリード部で
シールドすることにより部品から発生する放射ノイズを
抑制することができる。In the semiconductor device 30 shown in FIG. 3, a power supply line and a ground line are connected to specific ones of a plurality of leads 31, and a signal line is connected to solder balls as a plurality of contacts. With this configuration, the radiation noise generated from the component can be suppressed by shielding the radiation noise generated from the generation of the signal line by the lead portion located outside the solder ball.
【００３０】次に図３に示す半導体装置を半導体装置搭
載用印刷配線板としてのマザー印刷配線板に搭載した状
態を図６に示す。同図において、マザー印刷配線板５０
上面には電極５１が形成されており、半導体装置３０は
印刷配線板２１の下面に形成された半田ボール２３、及
び印刷配線板２１の周囲に接続されたリード３１の下端
がマザー印刷配線板５０上の所定位置の電極上に載置さ
れ、接着される。ここで半導体装置３０は、図３に示す
ように印刷配線板の下面から前記リードの下端の延長線
上までの垂直距離ｈが前記半田ボールの直径Ｄより僅か
に短かくなるように形成されている。Next, FIG. 6 shows a state in which the semiconductor device shown in FIG. 3 is mounted on a mother printed wiring board as a printed wiring board for mounting a semiconductor device. In the figure, a mother printed wiring board 50
An electrode 51 is formed on the upper surface. The semiconductor device 30 has a solder ball 23 formed on the lower surface of the printed wiring board 21 and a lower end of a lead 31 connected around the printed wiring board 21 to the mother printed wiring board 50. It is placed on the electrode at a predetermined upper position and bonded. Here, the semiconductor device 30 is formed such that the vertical distance h from the lower surface of the printed wiring board to the extension of the lower end of the lead is slightly shorter than the diameter D of the solder ball, as shown in FIG. .
【００３１】この半導体装置３０をマザー印刷配線板５
０上に載置し、半田ボール２３、リード３１と電極５１
とを接着する際に半導体装置３０にヒートシンク、ヒー
トスプレッダー等の放熱部材５２が予め装着され、ある
いはモジュール等の複数部品が半導体装置３０に実装さ
れて重量が増加している場合であってもペリフェラル状
のリードが設けられることにより、リフロー熱による半
田ボール２３の加熱溶解時に接点としての半田ボールに
過度に荷重がかからないように前記リードにより半導体
装置本体が支持されるので、半田ボールが潰れることが
なく、それ故電極間短絡等の接続不良の発生を防止する
ことができる。接点の材料として半田のような低融点合
金を用いる場合はＢＧＡのみならず、ＣＳＰ（Ｃｈｉｐ
Ｓｉｚｅ Ｐａｃｋａｇｅ），μ−ＢＧＡ（ｍｉｃｒ
ｏ−ＢＧＡ），ＬＧＡ（ＬａｎｄＧｒｉｄ Ａｒｒａ
ｙ）等にも利用できる。The semiconductor device 30 is connected to the mother printed wiring board 5
0, the solder ball 23, the lead 31 and the electrode 51
When the semiconductor device 30 is attached with a heat radiating member 52 such as a heat sink or a heat spreader in advance, or when a plurality of components such as modules are mounted on the semiconductor device 30 and the weight increases, the Since the semiconductor device body is supported by the leads so that the load is not excessively applied to the solder balls as the contacts when the solder balls 23 are heated and melted by the reflow heat, the solder balls may be crushed. Therefore, it is possible to prevent the occurrence of a connection failure such as a short circuit between the electrodes. When a low melting point alloy such as solder is used as a contact material, not only BGA but also CSP (Chip)
Size Package), μ-BGA (micro
o-BGA), LGA (LandGrid Arra)
y) etc. can be used.
【００３２】本発明の第２の実施の形態を図５及び図７
に示す。本発明の第２の実施の形態では図２に示した半
導体装置において印刷配線板２１の下面に配設された複
数の接点としての半田ボール２３の内の一部を半田ボー
ル２３の直径より僅かに短い高さを有するコンデンサ、
抵抗等の受動素子４１に置換するように構成している。
この半導体装置４０の裏面の状態を図５に示す。この受
動素子４１はチップ部品として用意したものを上記複数
の半田ボール２３の代わりに電極２７に接続することに
より接点２３と受動素子４１とを置換している。この半
導体装置４０をマザー印刷配線板５０上に搭載した状態
を図７に示す。半導体装置４０をマザー印刷配線板５０
上に載置し、半田ボール２３、受動素子４１と電極５１
とを接着する際に半導体装置４０にヒートシンク、ヒー
トスプレッダー等の放熱部材５２が予め装着され、ある
いはモジュール等の複数部品が半導体装置４０に実装さ
れて重量が増加している場合であっても受動素子４１に
よって半導体装置４０が支持されるのでリフロー熱によ
る半田ボール２３の加熱溶解時にも半田ボールが潰れる
ことがなく、それ故電極間短絡等の接続不良の発生を防
止することができると共に、半導体装置搭載用印刷配線
板としてのマザー印刷配線板上の部品の搭載効率の向上
を図った半導体装置の実装構造を実現できる。FIGS. 5 and 7 show a second embodiment of the present invention.
Shown in In the second embodiment of the present invention, in the semiconductor device shown in FIG. 2, a part of the solder balls 23 as a plurality of contacts arranged on the lower surface of the printed wiring board 21 is slightly smaller than the diameter of the solder balls 23. A capacitor with a short height to
It is configured to be replaced with a passive element 41 such as a resistor.
FIG. 5 shows a state of the back surface of the semiconductor device 40. The passive element 41 replaces the contact 23 with the passive element 41 by connecting a prepared chip component to the electrode 27 instead of the plurality of solder balls 23. FIG. 7 shows a state in which the semiconductor device 40 is mounted on a mother printed wiring board 50. The semiconductor device 40 is connected to a mother printed wiring board 50.
Placed on the solder ball 23, the passive element 41 and the electrode 51
When bonding the semiconductor device 40 to the semiconductor device 40, a heat radiating member 52 such as a heat sink or a heat spreader is attached in advance, or even if a plurality of components such as modules are mounted on the semiconductor device 40 and the weight is increased, Since the semiconductor device 40 is supported by the element 41, the solder ball 23 is not crushed even when the solder ball 23 is heated and melted by reflow heat. A semiconductor device mounting structure can be realized in which the mounting efficiency of components on a mother printed wiring board as a printed wiring board for mounting the device is improved.
【００３３】尚、本発明の第２の実施の形態では受動素
子４１を予めチップ部品として用意したが、この代わり
に半導体装置４０をマザー印刷配線板５０に搭載する際
に半導体装置４０の印刷配線板２１とマザー印刷配線板
５０上の所定の電極５１との間に形成するようにしても
よい。In the second embodiment of the present invention, the passive element 41 is prepared in advance as a chip component. However, when the semiconductor device 40 is mounted on the mother printed wiring board 50, the printed wiring of the semiconductor device 40 is used instead. It may be formed between the board 21 and a predetermined electrode 51 on the mother printed wiring board 50.
【００３４】また受動素子を半導体装置４０側に設ける
代わりに半田ボール２３の直径より僅かに短い高さを有
するコンデンサ、抵抗等の受動素子４１予めチップ部品
として用意し、これをマザー印刷配線板５０側の所定の
電極５１に予め接続しておき、その後半導体装置４０と
接続するようにしてもよい。Instead of providing a passive element on the semiconductor device 40 side, a passive element 41 such as a capacitor or a resistor having a height slightly shorter than the diameter of the solder ball 23 is prepared in advance as a chip component, and this is prepared as a mother printed wiring board 50. May be connected to the predetermined electrode 51 on the side in advance, and then connected to the semiconductor device 40.
【００３５】更に受動素子４１を予めチップ部品として
用意する代わりにマザー印刷配線板５０の電極５１を形
成する際に所定の電極位置に受動素子を形成するように
してもよい。Further, instead of preparing the passive element 41 as a chip component in advance, the passive element may be formed at a predetermined electrode position when the electrode 51 of the mother printed wiring board 50 is formed.
【００３６】次に本発明の第３の実施の形態を図８を参
照して説明する。同図において、本発明の第３の実施の
形態では図２に示す半導体装置２０を半導体搭載用印刷
配線板としてのマザー印刷配線板５０に固定する際に、
半導体装置２０の周縁部とマザー印刷配線板５０とを受
動素子６０を介して半田６１により固定する。Next, a third embodiment of the present invention will be described with reference to FIG. In the figure, in the third embodiment of the present invention, when the semiconductor device 20 shown in FIG. 2 is fixed to a mother printed wiring board 50 as a printed wiring board for mounting a semiconductor,
The peripheral portion of the semiconductor device 20 and the mother printed wiring board 50 are fixed with the solder 61 via the passive element 60.
【００３７】第３の実施の形態によれば、加工工数の低
減及び実装領域の増大が図れる。According to the third embodiment, the number of processing steps can be reduced and the mounting area can be increased.
【００３８】[0038]
【発明の効果】以上説明したように請求項１に記載の発
明によれば、高密度多ピン化を図った半導体装置を実現
できる。As described above, according to the first aspect of the present invention, it is possible to realize a semiconductor device with high density and high pin count.
【００３９】請求項２に記載の発明によれば、ペリフェ
ラル構造の複数のリードを設けることにより、半導体装
置搭載用印刷配線板に半導体装置を搭載する際にリフロ
ー熱による接点の加熱溶解時に接点の潰れによる電極間
ショート等の接続不良を防止することができる。According to the second aspect of the present invention, by providing a plurality of leads having a peripheral structure, when mounting the semiconductor device on the printed wiring board for mounting the semiconductor device, the contact is heated and melted by reflow heat. Poor connection such as short-circuit between electrodes due to crushing can be prevented.
【００４０】請求項３に記載の発明によれば、部品から
発生する放射ノイズを外側のリードでシールドすること
により抑制することができる。According to the third aspect of the present invention, the radiation noise generated from the component can be suppressed by shielding the noise with the outer leads.
【００４１】請求項４に記載の発明によれば、部品の搭
載効率の向上及び接点の潰れの防止を図った半導体装置
の実装構造を実現できる。According to the fourth aspect of the present invention, it is possible to realize a semiconductor device mounting structure that improves the mounting efficiency of components and prevents the contact from being crushed.
【００４２】請求項５に記載の発明によれば、本来、半
導体装置内あるいは半導体装置搭載用印刷配線板の別の
領域に実装すべき受動素子を、半導体装置を半導体装置
搭載用印刷配線板に搭載するために固定する際に、半導
体装置の周縁部と半導体装置搭載用印刷配線板との間に
介在させて行うようにしたので、加工工数の低減及び実
装領域の増大が図れる。According to the fifth aspect of the present invention, the passive element to be originally mounted in the semiconductor device or in another region of the printed wiring board for mounting the semiconductor device is replaced with the printed wiring board for mounting the semiconductor device. When the semiconductor device is fixed for mounting, the semiconductor device is interposed between the peripheral portion of the semiconductor device and the printed wiring board for mounting the semiconductor device, so that the number of processing steps can be reduced and the mounting area can be increased.
【図１】ペリフェラル構造のＱＦＰ等の半導体装置の外
観構成を示す斜視図。FIG. 1 is a perspective view showing an external configuration of a semiconductor device such as a QFP having a peripheral structure.
【図２】半導体チップがマウントされる印刷配線板の裏
面にマトリクス状にボール状接点が配設されてなるＢＧ
Ａ等の半導体装置の外観構成を示す図。FIG. 2 is a BG in which ball-shaped contacts are arranged in a matrix on the back surface of a printed wiring board on which a semiconductor chip is mounted;
FIG. 2 is a diagram illustrating an external configuration of a semiconductor device such as A.
【図３】本発明の第１の実施形態に係る半導体装置の構
成を示す図。FIG. 3 is a diagram showing a configuration of a semiconductor device according to the first embodiment of the present invention.
【図４】図３に示した半導体装置の裏面から見た外観構
成図。FIG. 4 is an external structural view of the semiconductor device shown in FIG.
【図５】本発明の第２の実施の形態に係る半導体装置の
裏面構成を示す図。FIG. 5 is a diagram showing a back surface configuration of a semiconductor device according to a second embodiment of the present invention.
【図６】図３に示した半導体装置をマザー印刷配線板に
搭載した状態を示す断面図。FIG. 6 is a sectional view showing a state where the semiconductor device shown in FIG. 3 is mounted on a mother printed wiring board.
【図７】図５に示す半導体装置をマザー印刷配線板に搭
載した状態を示す断面図。7 is a cross-sectional view showing a state where the semiconductor device shown in FIG. 5 is mounted on a mother printed wiring board.
【図８】図２に示す半導体装置をマザー印刷配線板に固
定した状態を示す断面図。8 is a cross-sectional view showing a state where the semiconductor device shown in FIG. 2 is fixed to a mother printed wiring board.
１ リード ３ デバイスパッケージ １０ 半導体装置 ２０ 半導体装置 ２１ 印刷配線板 ２２ 半導体チップ ２３ 半田ボール ２４ パッド ２５ ボンディングワイア ２６ 印刷配線 ２７ 電極 ２８ 樹脂 ３０ 半導体装置 ３１ リード ４０ 半導体装置 ４１ 受動素子 ５０ マザー印刷配線板 ５１ 電極 ５２ 放熱部材 ６０ 受動素子 ６１ 半田 DESCRIPTION OF SYMBOLS 1 Lead 3 Device package 10 Semiconductor device 20 Semiconductor device 21 Printed wiring board 22 Semiconductor chip 23 Solder ball 24 Pad 25 Bonding wire 26 Printed wiring 27 Electrode 28 Resin 30 Semiconductor device 31 Lead 40 Semiconductor device 41 Passive element 50 Mother printed wiring board 51 Electrode 52 Heat dissipation member 60 Passive element 61 Solder
Claims (5)
ップを樹脂モールドし、前記半導体チップ上面に形成さ
れた回路と導通する複数のリードが前記印刷配線板の周
囲に配設すると共に、前記半導体チップ上面に形成され
た回路と導通する複数の接点を前記印刷配線板の下面に
配設したことを特徴とする半導体装置。A semiconductor chip fixed to an upper surface of the printed wiring board is resin-molded, and a plurality of leads electrically connected to a circuit formed on the upper surface of the semiconductor chip are arranged around the printed wiring board; A semiconductor device, wherein a plurality of contacts for conducting with a circuit formed on an upper surface of a semiconductor chip are arranged on a lower surface of the printed wiring board.
下端の延長線上までの垂直距離が前記接点の高さより僅
かに短かくなるようにしたことを特徴とする請求項１に
記載の半導体装置。2. The semiconductor device according to claim 1, wherein a vertical distance from a lower surface of said printed wiring board to an extension of a lower end of said lead is slightly shorter than a height of said contact. .
複数のリードのうちの特定のリードに電源ライン及びグ
ランドラインを接続し、前記複数の接点に信号ラインを
接続することを特徴とする請求項１に記載の半導体装
置。3. A power supply line and a ground line are connected to specific ones of the plurality of leads arranged around the printed wiring board, and a signal line is connected to the plurality of contacts. The semiconductor device according to claim 1.
ップを樹脂モールドし、印刷配線板の下面に前記半導体
チップ上面に形成された回路と導通する複数の接点が配
設された半導体装置を、前記複数の接点に対向して形成
された複数の電極を有する半導体装置搭載用印刷配線板
の所定の電極位置に前記複数の接点を載置し、接続する
ことにより搭載する際に、前記複数の接点のうちの特定
の接点の代わりに前記接点の高さより僅かに短い高さを
有する受動素子を介在させたことを特徴とする半導体装
置の実装構造。4. A semiconductor device in which a semiconductor chip fixed to an upper surface of a printed wiring board is resin-molded, and a plurality of contacts for conducting to a circuit formed on the upper surface of the semiconductor chip are provided on a lower surface of the printed wiring board. Placing the plurality of contacts at predetermined electrode positions on a printed wiring board for mounting a semiconductor device having a plurality of electrodes formed to face the plurality of contacts, and mounting the plurality of contacts by connecting the plurality of contacts; Characterized in that a passive element having a height slightly shorter than the height of the contact is interposed in place of a specific one of the contacts.
ップを樹脂モールドし、印刷配線板の下面に前記半導体
チップ上面に形成された回路と導通する複数の接点が配
設された半導体装置を半導体装置搭載用印刷配線板に固
定する際に、前記半導体装置の周縁部と前記半導体装置
搭載用印刷配線板とを受動素子を介して固定することを
特徴とする半導体装置の固定方法。5. A semiconductor device in which a semiconductor chip fixed to an upper surface of a printed wiring board is resin-molded, and a plurality of contacts that are electrically connected to a circuit formed on the upper surface of the semiconductor chip are provided on a lower surface of the printed wiring board. A method of fixing a semiconductor device, comprising: fixing a peripheral portion of the semiconductor device to the printed wiring board for mounting the semiconductor device via a passive element when fixing the printed wiring board to the semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1033997A JP3460489B2 (en) | 1997-01-23 | 1997-01-23 | Semiconductor device mounting structure and semiconductor device fixing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1033997A JP3460489B2 (en) | 1997-01-23 | 1997-01-23 | Semiconductor device mounting structure and semiconductor device fixing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH10209323A true JPH10209323A (en) | 1998-08-07 |
| JP3460489B2 JP3460489B2 (en) | 2003-10-27 |
Family
ID=11747444
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1033997A Expired - Fee Related JP3460489B2 (en) | 1997-01-23 | 1997-01-23 | Semiconductor device mounting structure and semiconductor device fixing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3460489B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7005747B2 (en) | 2002-10-02 | 2006-02-28 | Shinko Electric Industries Co., Ltd. | Semiconductor device having additional functional element and method of manufacturing thereof |
-
1997
- 1997-01-23 JP JP1033997A patent/JP3460489B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7005747B2 (en) | 2002-10-02 | 2006-02-28 | Shinko Electric Industries Co., Ltd. | Semiconductor device having additional functional element and method of manufacturing thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3460489B2 (en) | 2003-10-27 |
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