JPH10208994A - Alignment method and aligner - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the expanding or shrinking amount of a semiconductor substrate to zero by finding the temperature difference corresponding to the expanding or shrinking amount of the substrate by dividing the measured expanding or shrinking amount of the substrate by the coefficient of thermal expansion of the substrate and heating or cooling the substrate. SOLUTION: After a semiconductor substrate 35 is roughly aligned by measuring the temperature of the substrate 35, the positional deviations of alignment marks at several points on the substrate 35 are measured with a detector 6 and a signal processing unit 5 extracts an expanding or shrinking component and finds the target temperature of the substrate 35 from the expanding or shrinking amount of the component. Then a temperature controller 3 controls the temperature of a fluid and adjusts the temperature of a holder 9 by circulating a fluid to the holder 9. A temperature sensor 2 measures the temperature of the substrate 34 while the substrate 35 is heated or cooled and, when the temperature of the substrate 35 reaches a target value, alignment is started. Consequently, highly accurate in-chip overlay can be performed by correcting the positional deviation of the substrate 35.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an exposure method and an exposure apparatus for positioning a circuit pattern formed on a mask on a semiconductor substrate and transferring the circuit pattern.

[0002]

2. Description of the Related Art With the miniaturization of the pattern size of a semiconductor integrated circuit, the demand for the overlay accuracy between mask patterns has become very strict. Generally, it is said that the overlay accuracy is required to be about 1/4 to 1/3 of the minimum design size. Applying this to a dynamic random access memory (DRAM), which is a typical semiconductor integrated circuit, a 64 MDRAM (minimum dimension 0.35 μm)
Is 0.10 μm, 256M DRAM (minimum dimension 0.2
5 μm) is 0.07 μm, and that of 1GDRAM (minimum dimension 0.18 μm) is 0.05 μm.

FIG. 4 is a schematic plan view showing a semiconductor substrate for explaining a state of superposition between chips. There are many factors that affect the overlay accuracy, and the classification methods are various. One of the classification methods is a method of distinguishing between the overlap between chips and the overlap within the chips. As shown in FIG. 4, the chip-to-chip superimposition is intended for the measurement point A representing the chip to be accurately superimposed on the semiconductor substrate 35, and a plurality of measurement points in the chip to be superimposed accurately. Does not always matter.

FIGS. 5 (a) and 5 (b) are schematic plan views showing a chip for explaining displacement in the case of superposition within a chip. On the other hand, in the superposition in the chip,
As shown in FIG. 5, it is intended to be accurately superimposed at any point in the chip or at least a plurality of measurement points (A to I).

The former is mainly affected by the accuracy of the alignment sensor and the stage accuracy of the exposure apparatus, and the latter is mainly affected by lens distortion (including magnification) and reticle rotation. Both the intra-chip and inter-chip overlay accuracy improvement measures have been considered as important issues, but the improvement of the intra-chip overlay accuracy is particularly important in manufacturing 256-M DRAM high-density memories. Attention has come to attention. The reasons are mainly the following two points.

The first reason is that it has been found that the formation of a silicon nitride film, a silicon oxide film, a polycrystalline silicon film, etc. causes expansion and contraction of a semiconductor substrate represented by silicon, resulting in an overlay error. Yes (Reference: A. Ima
i et. al, SPIE. Vol. 2726,199
6, pp. 104-pp. 112 etc.). The second reason is
When the semiconductor substrate expands and contracts at a certain expansion and contraction rate, the amount of intra-chip overlay error increases as the chip size increases.

FIG. 6 is a plan view of one chip for explaining an intra-chip overlay error, and FIG. 7 is a table showing film types / film thicknesses and substrate expansion / contraction amounts. As an example of the in-chip overlay error due to the expansion and contraction of the substrate, as shown in FIG. 6, overlay error measurement marks are arranged above and below a semiconductor chip having a length of 22 mm in the long side direction of the chip. We examined how much stretching would occur. As a result, as shown in the table of FIG. 7, a maximum overlay error of about 0.1 to 0.2 μm is generated in the chip, and it is impossible to cope with a 256 MDRAM class device without any correction. found.

As a method for correcting such an intra-chip overlay error due to the expansion and contraction of the semiconductor substrate, a method of adjusting the projection magnification in a projection exposure apparatus by a small amount has been conventionally proposed. As an example of this, the contents disclosed in JP-A-4-107465 will be described below.

FIG. 8 is a flowchart for explaining a method of correcting an intra-chip overlay error in an example of the related art.
FIG. 9 is a diagram showing measurement points on a wafer. In this correction method, first, in step A of FIG. 8, a wafer coated with a photoresist is carried into an exposure apparatus and placed on a wafer holder. Next, in step B of FIG. 8, rough alignment of the wafer was performed, and in step C, the amount of misalignment at several locations on the wafer was measured by the alignment sensor of the exposure apparatus. At this time, for example, as shown in FIG. 9, if the positional deviation amount at four locations (measurement points J to M) around the wafer is measured, the substrate expansion and contraction in the X and Y directions can be performed in steps D and E. The rate can be calculated by the following equation.

X-direction expansion and contraction ratio: (ΔX ₄ + ΔX ₃ ) / Lx (ppm) (2) Y-direction expansion and contraction ratio: (ΔY ₁ + ΔY ₂ ) / Ly (ppm) (2) where ΔY ₁ is at measurement point J The amount of displacement in the Y direction,
−ΔY ₂ is the amount of displacement in the Y direction at the measurement point K, −ΔX
₃ is a displacement amount in the X direction at the measurement point L, ΔX ₄ is a displacement amount in the X direction at the measurement point M (284), Ly is a distance between the measurement points J and K, and Lx is a distance between the measurement points L and M. It is. For simplicity, the X of the measurement points J and K
The direction shift amount is 0, and the shift amounts of the measurement points L and M in the Y direction are also 0.
There is.

Next, in step F, shift, rotation,
Correction such as orthogonality and scaling is performed. In parallel with this correction, in steps G and H, a correction amount of the reduction magnification is obtained from the previously obtained substrate expansion / contraction ratio and correction is performed, and then exposure is performed in step I.

[0012]

In the above-described conventional method for correcting an in-chip overlay error, fine adjustment of the projection magnification is performed by changing the pressure between the projection lens groups, that is, by changing the refractive index. Since the range is limited by the lens design, there is a problem that the projection magnification of the reduction projection exposure apparatus can be changed only in a very limited range of about 5 to 10 ppm after being converted into an amount of expansion and contraction.

In addition, it is pointed out that it is impossible in principle to adjust the projection magnification with a 1: 1 exposure apparatus typified by a 1: 1 X-ray exposure apparatus, and the projection magnification cannot be changed by all the exposure apparatuses. It is a disadvantage.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide an exposure method and an exposure apparatus capable of realizing high-accuracy in-chip superposition for a wide range of expansion and contraction ratio of a semiconductor substrate regardless of an exposure method. .

[0015]

A feature of the present invention is that in an exposure method for aligning and transferring a mask pattern on a semiconductor substrate by exposure and transfer, the amount of expansion and contraction of the semiconductor substrate on a plane due to a previous process is measured. Dividing the measured expansion / contraction amount by the thermal expansion coefficient of the semiconductor substrate to obtain a temperature difference corresponding to the expansion / contraction amount, and heating or cooling the semiconductor substrate so that the temperature difference becomes zero. An exposure method for eliminating the amount of expansion and contraction, and thereafter exposing and transferring the mask pattern onto the semiconductor substrate. Also, measuring a difference between a distance between a coordinate of at least one pair of alignment marks arranged at a center of the semiconductor substrate in one direction of the semiconductor substrate and a direction orthogonal to the one direction from a preceding process. It is desirable to determine the amount of expansion and contraction by the following formula.

Another feature of the present invention is that an exposure optical system for projecting exposure light on a reticle on which the mask pattern is formed, and that the mask pattern is projected on the semiconductor substrate mounted on a holder of a stage. In an exposure apparatus including a projection lens, a measuring mechanism for measuring the amount of expansion and contraction of the semiconductor substrate from the coordinates of the alignment mark and measuring the expansion and contraction ratio, and measuring the temperature of the semiconductor substrate so that the expansion and contraction ratio becomes zero. The exposure apparatus includes a temperature control mechanism for controlling the exposure. Further, it is desirable to provide a temperature control unit for always maintaining the temperature of the semiconductor substrate at a constant temperature.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a schematic sectional view showing an exposure apparatus according to an embodiment of the present invention. As shown in FIG. 1, the exposure apparatus recognizes at least two positions of alignment marks on the semiconductor substrate 35 in the X and Y directions through the alignment optical system 7 and detects a position shift of the semiconductor substrate 35 from a previous process. A detector 6 for measuring the amount of expansion and contraction, a signal processing unit 5 and a control unit 4 for calculating the expansion and contraction ratio of the semiconductor substrate 35 from the amount of expansion and contraction from the detector 6 and the original alignment mark position, and a holder 9 for mounting the semiconductor substrate 35
A temperature control fluid circulating mechanism 1 built-in, a temperature sensor 2 for measuring the temperature of the semiconductor substrate 35, and a temperature controller 3 based on an expansion / contraction rate signal from the signal processing unit and a temperature signal from the temperature sensor 2.
And a control unit 4 for performing PID control.

The exposure light of this exposure apparatus has a wavelength of 2
A 48 nm excimer laser 22 is used. Then, the KrF band narrowed from the excimer laser 22 is used.
Excimer laser beam is extracted and beam expander 2
It is shaped into an appropriate shape by 1. Next, the light enters the fly-eye lens 19 via the reflection mirror 20 to form a secondary light source via the aperture stop 18 and the condenser lens 23, and then the exposure light uniformly irradiates the reticle 13. The circuit pattern formed on the reticle 13 is reduced to a predetermined projection magnification by the projection lens 12 so that the semiconductor substrate 35
The image is formed on the surface of the substrate and the pattern is transferred.

An off-axis alignment optical system 7 is provided in addition to the projection optical system. The alignment optical system 7 irradiates the laser beam of the He-Ne laser 17 to the alignment mark formed on the semiconductor substrate 35 via the reflection mirrors 16 and 15 and the alignment optical system 7, and detects the diffracted light by the detector 6. To obtain position information. The alignment light is not necessarily He-Ne laser light, and light of a broadband wavelength may be applied to detect the image of the alignment mark.

On the other hand, a temperature control fluid mechanism 1 for raising or lowering the temperature of the semiconductor substrate 35 is connected to the temperature controller 3 via a pipe on the jacket of the holder 9 and is connected to the temperature sensor 2 embedded in the holder 9. The temperature is detected and PID control of the temperature controller 3 is performed by the control unit 4 so that the temperature of the semiconductor substrate 35 reaches a predetermined temperature in a short time. The temperature sensor 2 uses a high-resolution platinum resistor, for example. Further, the control unit 4 is a device in which a microcomputer is incorporated in a commercially available PID controller.

The distance between the alignment marks in the X or Y direction is measured by the moving distance of the stage 8. The moving distance is determined by the mirror 10 of the stage 8.
Is irradiated with laser light, and the reflected light enters the laser interferometer 11 for measurement. This operation is used when measuring the amount of expansion and contraction between the alignment marks described below.

Here, as shown in FIG. 9 described above, at least two or more measurement points are preferably independently selected in the X and Y directions on the semiconductor substrate 35. The expansion and contraction ratio of the substrate can be obtained from the above equations (1) and (2). If the number of measurement points is further increased, a more accurate expansion and contraction ratio can be obtained statistically.

FIG. 2 is a flowchart for explaining an exposure method using the exposure apparatus of FIG. FIGS. 1 and 2 show a method of correcting a displacement according to the present invention.
This will be described with reference to FIG. First, in step A of FIG. 2, a wafer as the semiconductor substrate 35 is placed on the holder 9 of FIG.
In step B, the temperature of the wafer is measured. Thereafter, in step C, rough alignment of the wafer is performed. Here, the order of step B of temperature measurement and step C of coarse alignment may be reversed. Next, in step D, the amount of misalignment of several alignment marks in the wafer as the semiconductor substrate is measured by the detector 6 in FIG.
Then, the expansion / contraction component is extracted by the signal processing unit 5 of FIG. Then, in Steps F and G, the shift component is extracted and the shift component is corrected.

Next, the process of correcting the displacement will be described. Usually, the amount of expansion and contraction ΔL due to a change in temperature of a substance is represented by
Is obtained by the following equation.

L = L ₀ (1 + αT) (1) ΔL = L ₂ −L ₁ = L ₀ (1 + αT ₂ ) −L ₀ (1−αT ₁ ) (2) where L: length of object L ₀ The length of the object at 0 ° C. T; the temperature L ₁ ; the length of the object at the temperature T ₁ L ₂ ; the length of the object at the temperature T ₂ . ΔL has already been obtained from the displacement amount, and T ₁ is the temperature of the semiconductor substrate 35 already measured. L ₀ is the theoretical distance between the alignment marks and is determined if chip information is obtained. α is a value specific to the substance,
In the case of silicon, it is 2.6 × 10 ⁻⁶ . More precisely, it is desirable to obtain the coefficient of linear expansion for each step of film formation and pattern formation. However, in the case of a 6-inch silicon substrate, which is a typical semiconductor substrate, the thickness is about 700 μm, which is sufficiently large with respect to the thickness of a film to be formed later. .

Next, in step H, a target substrate temperature is determined. For example, when the temperature of the semiconductor substrate 35 is 23
° C, the distance between the alignment marks is 100 mm, and the difference in displacement between the two alignment marks is 0.50 μm.
When it is, (if shrinks substrate, if extending 21.08 ° C.) temperature T ₂ is 24.92 ° C. can be obtained with the target temperature.

When the target temperature is determined based on the calculation result performed by the control unit 4 in FIG.
Controls the temperature of the fluid such as florinate. This fluid is circulated to the holder 9 to adjust the temperature of the holder 9. Further, the temperature of the semiconductor substrate 35 is measured by the temperature sensor 2 and PID-controlled by the control unit 4. Next, after it is confirmed in step J that the temperature of the semiconductor substrate 35 is sufficiently close to the target temperature, for example, within 0.2 ° C., exposure is started in step K. At this time, the correction of each shift component has already been performed in parallel with the above processing. As described above, the displacement due to the expansion and contraction of the semiconductor substrate can be appropriately corrected.

The range of expansion and contraction that can be corrected is 1
It is corrected to 2.6 ppm for temperature change of ℃.
The pm correction corresponds to a change of approximately 8 ° C. In this temperature range, the photochemical reaction of the resist occurs without any problem, so that it can be controlled over a wide range.

FIG. 3 is a schematic sectional view showing a modification of the exposure apparatus shown in FIG. In this exposure apparatus, as shown in FIG. 3, a temperature control unit 3a is provided in the middle of a piping path between the temperature controller 3 and the temperature control fluid circulator light 1. Other configurations are the same as those of the exposure apparatus shown in FIG.

Normally, when the temperature of the semiconductor substrate 35 is controlled only by the temperature controller 3, even if the PID control is performed, it takes time to reach the target temperature and the throughput is reduced. Therefore, for the second and subsequent semiconductor substrates 35 in the case of processing a plurality of semiconductor substrates, the temperature is controlled in advance by the temperature control unit 22 to the target temperature, and then the semiconductor substrate 35 is loaded on the holder 9. With the addition of the temperature control unit 3a, there is an advantage that the temperature of the semiconductor substrate 35 rises and falls more quickly, the time required to reach the target temperature in the temperature controller 3 becomes shorter, and the throughput can be improved accordingly.

[0032]

As described above, according to the present invention, the amount of displacement of the distance between the alignment marks is measured, the amount of expansion and contraction of the semiconductor substrate from the previous process is obtained, and the temperature of the semiconductor substrate corresponding to the amount of expansion or contraction is increased. Since exposure is performed after reaching the semiconductor substrate at the target temperature to be lowered, misalignment is corrected, and high-accuracy in-chip superimposition can be performed, which has the effect of reducing superimposition defects and improving yield.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view showing an exposure apparatus according to an embodiment of the present invention.

FIG. 2 is a flowchart for explaining an exposure method by the exposure apparatus of FIG. 1;

FIG. 3 is a schematic sectional view showing a modified example of the exposure apparatus of FIG.

FIG. 4 is a schematic plan view showing a semiconductor substrate for explaining a state of superposition between chips.

FIG. 5 is a schematic plan view showing a chip for explaining displacement in the case of superposition in a chip.

FIG. 6 is a plan view of one chip for explaining an intra-chip overlay error.

FIG. 7 is a table showing film types / film thicknesses and substrate expansion / contraction amounts.

FIG. 8 is a flowchart illustrating a method of correcting an intra-chip overlay error according to an example of the related art.

FIG. 9 is a diagram showing measurement points on a wafer.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Temperature control fluid circulation mechanism 2 Temperature sensor 3 Temperature controller 3a Temperature control unit 4 Control unit 5 Signal processing unit 6 Detector 7 Alignment optical system 8 Stage 9 Holder 10 Mirror 11 Laser interferometer 12 Projection lens 13 Reticle 14, 15, 16 , 20 Reflecting mirror 17 He-Ne laser 18 Aperture stop 19 Fly-eye lens 21 Beam expander 22 Excimer laser 23 Condenser lens 35 Semiconductor substrate

Claims (4)

[Claims] 1. An exposure method for exposing and transferring a mask pattern on a semiconductor substrate by exposing and transferring the mask pattern, the amount of expansion and contraction of the semiconductor substrate on a plane due to a process in a previous step is measured, and the measured amount of expansion and contraction is measured by the semiconductor. Dividing by the thermal expansion coefficient of the substrate to determine the temperature difference corresponding to the amount of expansion and contraction, heating or cooling the semiconductor substrate so that the temperature difference of the semiconductor substrate becomes zero, eliminating the amount of expansion and contraction, and then the An exposure method, comprising exposing and transferring a mask pattern onto the semiconductor substrate. 2. The method according to claim 1, wherein a difference between a distance between a coordinate of at least one pair of alignment marks symmetrically arranged at a center of the semiconductor substrate in one direction of the semiconductor substrate and a direction perpendicular to the one direction is different from a distance between the coordinates of the alignment mark and a previous step. The exposure method according to claim 1, wherein the amount of expansion and contraction is obtained by measuring. 3. An exposure apparatus comprising: an exposure optical system that projects exposure light onto a reticle on which the mask pattern is formed; and a projection lens that projects the mask pattern onto the semiconductor substrate mounted on a stage holder. A measuring mechanism that measures the amount of expansion and contraction of the semiconductor substrate from the coordinates of the alignment mark to measure the expansion and contraction ratio, and a temperature control mechanism that controls the temperature of the semiconductor substrate so that the expansion and contraction ratio becomes zero. An exposure apparatus comprising: 4. The exposure apparatus according to claim 3, further comprising a temperature control unit for keeping the temperature of the semiconductor substrate constant at all times.