JPH10207774A - Data rewriting device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To protect the data of a rewritable memory without dropping processing speed and increasing cost by judging whether a rewriting program storing area is accessed or not for each fetch cycle period, and only when the area is accessed, executing a rewriting instruction. SOLUTION: Data are rewritably stored in the rewritable memory 6. A write permission signal generation circuit 4 generates a signal (write permission signal) for permitting writing in the memory 6 only at the time of judging that the rewriting program storing area 2a is accessed in accordance with a rewriting instruction for the memory 6 which is outputted from a CPU 1. Only when the write permission signal is generated when the data rewriting instruction signal for the memory 6 is outputted from the CPU 1, a data rewriting means 5 executes the data rewriting of the memory 6, so that the generation of error rewriting is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a data rewriting device, and more particularly to a data rewriting device for a device having a rewritable memory and a read-only memory storing a program for rewriting data in the rewritable memory. In the present invention, the important data stored in the data rewriting memory
It is used to prevent accidental rewriting due to runaway of U.

[0002]

2. Description of the Related Art An information management apparatus for collecting, storing, and managing data such as operation history or billing information of copying machines and other devices is a rewritable memory (hereinafter also referred to as RAM).
A read-only memory (hereinafter also referred to as a ROM) storing a program for executing the rewriting operation of the rewritable memory (rewritable memory data rewriting program), and a CPU for controlling the operation of devices including these memories. Have. In such an information management device, the CPU
In the event of a runaway, the rewriting operation may be performed erroneously, and the data stored in the rewritable memory may be rewritten or destroyed without permission.

In order to prevent this, conventionally, when a write request for a rewritable memory is made, a write operation cannot be executed unless a predetermined specific pre-operation is performed. An apparatus having a protection circuit for protecting stored data is disclosed in Japanese Patent Application Laid-Open No. 61-55753. The data rewriting device disclosed in the above publication is configured to execute a command for designating a predetermined specific address of a ROM storing a rewrite operation program prior to a rewrite execution command.

The data rewriting device disclosed in Japanese Patent Application Laid-Open No. 7-86909 prepares an evacuation memory separately from a rewritable memory, and when rewriting important data,
The same data as the data to be rewritten is temporarily stored in the evacuation memory, and only after the rewriting process is executed, when the fixed information of the processed data is compared with the fixed information of the contents of the evacuation memory, it is determined that the data is normal. The rewritable memory is rewritten.

[0005]

In the former prior art,
There is a problem that the time required for rewriting is delayed by performing the specific pre-operation, and high-speed data processing cannot be performed.
In the latter case, an evacuation memory for evacuation of data is required, and the configuration is complicated and the cost is increased. The present invention has been made in view of the above circumstances, and has an object of the following content (O01). (O01) An object of the present invention is to solve the above-mentioned problems of the prior art and to provide a data rewriting device capable of protecting data in a rewritable memory without lowering the processing speed and without increasing the cost.

[0006]

Next, the present invention devised to solve the above-mentioned problems will be described. Elements of the present invention are used to facilitate correspondence with elements of the embodiments described later. , The reference numerals of the elements of the embodiment are enclosed in parentheses. The reason why the present invention is described in correspondence with the reference numerals of the embodiments described below is to facilitate understanding of the present invention, and not to limit the scope of the present invention to the embodiments.

According to the present invention, there is provided a data rewriting device according to the present invention, which has the following requirements. (A01) A rewritable memory capable of rewriting stored data (A01) 6), (A02) a rewrite program storage area (2a) in which data rewrite programs for rewriting data stored in the rewritable memory (6) are collected and stored, and another program storage area for storing other operation programs (2b) a read-only memory (2), (A03) a CPU (1) for controlling a rewrite operation of the rewritable memory (6), (A04) a CPU (1)
The rewritable memory (6) only when it is determined that the rewritable program storage area (2a) has been accessed in response to a rewrite instruction of the rewritable memory (6) from
Write enable signal generating circuits (4), (A)
05) When the CPU (1) outputs a data rewrite command signal of the rewritable memory (6), the data of the rewritable memory (6) is generated only when the write enable signal is generated. Data rewriting means (5) for executing rewriting.

(Operation of the present invention) In the data rewriting device of the present invention, data is rewritably stored in the rewritable memory (6). The read-only memory (2) has a rewrite program storage area (2a) and another program storage area (2b) in which other programs are stored. The rewrite program storage area (2a) collectively stores data rewrite programs for rewriting data stored in the rewritable memory (6). The CPU (1) controls a rewriting operation of the rewritable memory (6). The write enable signal generation circuit (4) only determines that the rewrite program storage area (2a) has been accessed in response to a rewrite instruction of the rewritable memory (6) from the CPU (1). A signal (write enable signal) for permitting the writing of the rewritable memory (6) is generated. The data rewriting means (5) performs the rewriting only when the CPU (1) outputs a data rewriting command signal of the rewritable memory (6) and the write enable signal is generated. The data of the memory (6) is rewritten. Thereby, erroneous rewriting of the rewritable memory (6) due to runaway of the CPU (1) can be prevented. Further, high-speed rewriting can be executed by eliminating the need to execute a specific process prior to the execution of rewriting as in the prior art, and by not requiring the addition of a save memory or the like.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION

(Embodiment 1 of the present invention) Embodiment 1 of the data rewriting device of the present invention is characterized in that the first invention has the following requirements: (A06) The program of the CPU (1) When a fetch cycle signal, which is a read cycle signal, is output, if a rewrite notification signal that notifies that the data rewrite program in the rewritable program storage area has been read is output, during the fetch cycle period Is the write enable signal generating circuit (4) for outputting the write enable signal. (Operation of the First Embodiment) In the first embodiment of the data rewriting device according to the present invention, the write enable signal generating circuit (4) includes a fetch cycle which is a program read cycle signal of the CPU (1). When the signal is output, if a rewrite notification signal for notifying that the data rewrite program in the rewritable program storage area has been read is output, the write enable signal is output during the fetch cycle. Output. That is, in one fetch cycle, the data in the rewritable memory (6) is rewritten only when it is notified that the data rewrite program in the rewritable program storage area has been read.

(Embodiment 2) The data rewriting device according to Embodiment 2 of the present invention is characterized in that in the present invention, the following requirements are satisfied: (A07) The CP
When a chip select signal for selecting a chip storing a program to be read by U (1) is output, a rewrite notification signal for notifying that the data rewrite program in the rewritable program storage area has been read is output. If so, the write enable signal generating circuit (4) that outputs the write enable signal until the next chip select signal is output. (Operation of the Second Embodiment of the Invention) In the second embodiment of the data rewriting device according to the present invention, the write enable signal generation circuit (4) is provided with a chip storing a program to be read by the CPU (1). When the chip select signal to be selected is output and a rewrite notification signal is output to notify that the data rewrite program in the rewritable program storage area has been read, the next chip select signal is output. During this period, the write enable signal is output. That is, from the time one chip select signal is output to the time the next chip select signal is output,
Only when it is notified that the data rewrite program in the rewritable program storage area has been read, the data in the rewritable memory (6) is rewritten.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, specific examples (embodiments) of embodiments of the present invention will be described with reference to the drawings. (Embodiment 1) FIG. 1 is a block diagram for explaining a configuration of a device management apparatus provided with a data rewriting apparatus according to Embodiment 1 of the present invention, wherein 1 is a CPU, 2 is a read-only memory, and 2a is a storage of a rewriting program. Area 2b is another program storage area, 3 is a decoder, 4 is a latch circuit, 5 is a gate, 6 is a rewritable memory, 7 is an address bus, and 8 is a managed device managed by a device management device. In FIG.
U1 is a central controller that controls the operations of the read-only memory 2, the rewritable memory 6, and the device management device. A rewritable memory data rewriting program is collectively stored in a rewriting program storage area 2a of the read-only memory 2. The other program storage area 2b stores a program for controlling other operations of the device management apparatus.

The decoder 3 outputs a latch signal to the latch 4 when detecting the address of the rewrite program storage area among the addresses of the read-only memory transferred on the address bus 7, and outputs the latch signal to the latch 4 from the CPU 1. Is latched, the latch 4 is latched. Latch 4
The gate 5 supplies a write signal from the CPU 1 to the rewritable memory 6 under the condition that there is a latch output in the rewritable memory 6, and rewrites data in the rewritable memory 6 according to the rewrite program read from the rewrite program storage area 2a.
Therefore, when the CPU 1 outputs a data rewrite command signal of the rewritable memory 6 from the CPU 1, the gate 5 performs the data rewrite of the rewritable memory 6 only when the write enable signal is generated. The "data rewriting means 5" to be executed is configured. The managed device 8 is, for example, a copying machine, and transfers a copy count number, an operation state, and other management data accompanying the operation thereof to the CPU 1 of the device management apparatus via a line.

(Operation of First Embodiment) FIG. 2 is a time chart for explaining the operation of the first embodiment of the data rewriting device according to the present invention. FIG. 3 is a flowchart for explaining the operation of the first embodiment of the data rewriting device according to the present invention. Hereinafter, the operation of the configuration of FIG. 1 will be described with reference to FIGS. The CPU 1 periodically outputs a fetch cycle signal, reads a program stored in the read-only memory 2, and executes various instructions. As shown in FIG. 1, in this embodiment, programs for executing the data rewriting operation of the rewritable memory 6 are collectively stored in the rewriting program storage area 2a of the read-only memory 2. Rewriting of the rewritable memory 6 is enabled only when the rewriting program storage area 2a is accessed, and when there is no access to the rewriting program storage area 2a, rewriting is prohibited to prevent rewriting of erroneous data due to runaway of the CPU. Prevent and protect data.

When the power of the device management apparatus of this embodiment is turned on, the CPU 1 is reset in step ST1. When a write request occurs, in step ST2, an address signal for accessing the read-only memory 2 becomes O.
N. Next, in step ST3, it is determined whether or not the address signal is in the designated area. If the answer is yes (Y) in step ST3 (if the address is in the rewrite program storage area 2a), the process proceeds to step ST4. In step ST4, the output of the decoder 3 becomes "L" and is supplied to the D input terminal of the latch 4. If the answer is no (N) in step ST3, the process moves to step ST5. In step ST5, the output of the decoder becomes "H" and is supplied to the D input terminal of the latch 4. Next, in step ST6, it is determined whether or not the fetch signal FC from the CPU 1 has fallen. If no (N), step ST6 is repeatedly executed. If yes (Y), the process moves to step ST7.

In step ST7, at the falling edge of the fetch signal, the latch 4 outputs the output signal of the decoder 3 input to the D input terminal from the Q terminal. At this time,
When the output signal of the decoder 3 is “L”, the output of the Q terminal becomes “L” (that is, a write enable signal),
Is "H", the output of the Q terminal becomes "H" (that is, a write inhibit signal). The output signals of these Q terminals are given to the gate 5. Next, in step ST8, it is determined whether or not the specified address is in a writable memory area. This determination is made based on whether the output signal of the decoder 3 is "L" or "H". In the case of "L", the result is yes (Y), and in the case of "H", the result is no (N).

If the answer is no (N) in step ST8, the processing operation is executed in step ST9. In step ST10, it is determined whether or not a rewriting operation is performed. If no (N), the process moves to step ST9, and if yes (Y), the process moves to step ST11. Step S
At T11, it is determined whether or not the write permission signal is "L". No (N) (write enable signal is "L"
If not, that is, if the write enable signal is not "L", the rewrite operation is invalidated in step ST12 and the process returns to step ST2. If yes (Y) in step ST11, a rewrite operation is executed in step ST9. In the execution of this rewriting operation, the CPU
The write signal W from 1 passes through the gate 5 and is written to the rewritable memory 6.

According to the first embodiment, the write enable signal generating circuit (latch 4) determines whether or not the rewrite program storage area 2a has been accessed at each cycle of the fetch cycle, and determines whether the rewrite program storage area 2a has been accessed. Only when is accessed, the write signal from the CPU 1 during the fetch cycle is validated and the rewrite instruction is executed. As a result, erroneous rewriting of the rewritable memory due to runaway of the CPU does not require the execution of a specific process prior to the execution of the rewriting as in the above-described prior art, and high-speed rewriting can be performed.

(Embodiment 2) FIG. 4 is a block diagram for explaining the configuration of a device management apparatus provided with a data rewriting apparatus according to Embodiment 2 of the present invention, wherein 1 is a CPU, 2 is a read-only memory, and 2a is Rewriting program storage area, 2b is another program storage area, 3a is a first decoder, 3b is a second decoder,
4 is a latch circuit, 5 is a gate, 6 is a rewritable memory, 7
Is an address bus, and 8 is a managed device managed by the device management device. In FIG. 4, similar to the first embodiment,
The CPU 1 is a central control device that controls operations of the read-only memory 2, the rewritable memory 6, and the device management device. A rewritable memory data rewriting program is collectively stored in a rewriting program storage area 2a of the read-only memory 2. The other program storage area 2b stores a program for controlling other operations of the device management apparatus.

When the first decoder 3a detects the address of the rewrite program storage area among the addresses of the read-only memory transferred on the address bus 7, the input terminal D of the latch 4 stores the address of the rewrite program storage area. It outputs a signal "L" (see FIG. 5) indicating the designation.
The second decoder 3b outputs a chip select signal CS to the read only memory 2 and the CK terminal of the latch 4 when detecting the address of the read only memory 2 among the addresses of the read only memory transferred on the address bus 7. . When the chip select signal CS is output from the second decoder 3b to the latch 4, the latch 4 latches the input signal of the D terminal and outputs it from the Q terminal. Under the condition that the output of the Q terminal of the latch 4 (latch output) is at the “L” level, the gate 5 can write the write signal from the CPU 1 into the rewritable memory 6.
To rewrite the data in the rewritable memory 6 according to the rewriting program read from the rewriting program storage area 2a. As in the first embodiment, the managed device 8
Is a copying machine, for example, and transfers a copy count number, an operation state, and other management data accompanying the operation thereof to the CPU 1 of the device management apparatus via a line.

(Operation of Second Embodiment) FIG. 5 is a time chart for explaining the operation of the second embodiment of the data rewriting device according to the present invention. FIG. 6 is a flowchart illustrating the operation of the data rewriting device according to the second embodiment of the present invention. Hereinafter, FIG.
The operation of the configuration will be described with reference to FIGS. C
When accessing the read-only memory 2, the PU 1 gives the address to the read-only memory 2 via the data bus 7. As shown in FIG. 4, in this embodiment, programs for executing the data rewriting operation of the rewritable memory 6 are collectively stored in the rewriting program storage area 2a of the read-only memory 2. This rewrite program storage area 2
Rewriting of the rewritable memory 6 is enabled only when a is accessed, and when there is no access to the rewriting program storage area 2a, rewriting is prohibited to prevent erroneous data rewriting and protect data. When the power of the device management apparatus of this embodiment is turned on, the processing of the flowchart shown in FIG. 6 is started. The processing of steps ST21 to ST32 in the flowchart of FIG. 6 of the second embodiment is almost the same as that of the flowchart of FIG. 3 of the first embodiment.
The only different process is a portion for determining whether or not the ROM chip select signal CS has fallen in step ST26.

In the second embodiment, as in the first embodiment,
Each time the chip select signal CS is output, the write enable signal generation circuit (latch 4) determines whether or not the rewrite program storage area 2a has been accessed, and only when the rewrite program storage area 2a has been accessed. , The rewrite command is executed with the write signal from the CPU 1 enabled. As a result, erroneous rewriting of the rewritable memory due to runaway of the CPU does not require the execution of a specific process prior to the execution of the rewriting as in the above-described prior art, and high-speed rewriting can be performed.

[0022]

The above-described data rewriting device of the present invention has the following effects. (E01) It is possible to provide a data rewriting device which can solve the above-mentioned problems of the prior art and can protect the data in the rewritable memory without lowering the processing speed and without increasing the cost. In addition, since a command for writing to a writable memory, which conventionally existed without restriction in the entire read-only memory, is merely collected in a designated area on the read-only memory, special processing is performed during a write operation. It is not necessary to perform this operation, and it is possible to protect data from being destroyed due to erroneous writing to the writable memory without providing a special memory for saving data.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a device management apparatus including a data rewriting device according to a first embodiment of the present invention.

FIG. 2 is a time chart illustrating an operation of the data rewriting device according to the first embodiment of the present invention.

FIG. 3 is a flowchart illustrating an operation of the data rewriting device according to the first embodiment of the present invention.

FIG. 4 is a block diagram illustrating a configuration of a device management device including a data rewriting device according to a second embodiment of the present invention.

FIG. 5 is a time chart illustrating the operation of the data rewriting device according to the second embodiment of the present invention.

FIG. 6 is a flowchart illustrating an operation of the data rewriting device according to the second embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... CPU, 2 ... Read-only memory, 2a ... Rewriting program storage area, 2b ... Other program storage area, 4 ... Write permission signal generation circuit, 5 ... Data rewriting means (gate), 6
… Rewritable memory,

Claims (3)

[Claims] 1. A data rewriting device having the following requirements:
(A01) A rewritable memory capable of rewriting stored data, (A02) A rewriting program storage area in which a data rewriting program for rewriting data stored in the rewritable memory is stored, and other operation programs are stored. (A03) a CPU that controls a rewriting operation of the rewritable memory, and (A04) a CPU that controls a rewriting operation of the rewritable memory. A write enable signal generation circuit that permits writing to the rewritable memory only when it is determined that
(A05) Data rewriting means for executing data rewriting of the rewritable memory only when the write enable signal is generated when the CPU outputs a data rewriting instruction signal of the rewritable memory. 2. The data rewriting device according to claim 1, wherein the data rewriting device has the following requirements: (A06) When a fetch cycle signal, which is a program read cycle signal of the CPU, is output,
When a rewrite notification signal is output to notify that the data rewrite program in the rewritable program storage area has been read, the write enable signal is output until the next fetch cycle signal is output. The write enable signal generating circuit for outputting. 3. The data rewriting device according to claim 1, further comprising: (A07) the rewritable program when a chip select signal for selecting a chip storing a program read by the CPU is output. When a rewrite notification signal is output to notify that the data rewrite program of the storage area has been read, the write enable signal is output during the period until the next chip select signal is output. Input enable signal generation circuit.