JPH10207587A - Computer system and its worm starting method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a computer system capable of reducing the load of a CPU at the instantaneous interruption of a power supply and quickly and safely executing preceding operation and a worm starting method for the computer system. SOLUTION: The computer system is constituted of a central processing unit(CPU) 1, a random access memory(RAM) 20, a read-only memory(ROM) 10 for storing a boot program to be executed after turning on the power supply, a ROM 11 for storing a worm starting program to be executed at the instantaneous interruption of the power supply, and a bus for mutually connecting the CPU 1, the RAM 20, and the ROMs 10, 11. The system is also provided with a power supply circuit 15, a memory holding capacitor 13 for supplying power to the RAM 20 only for prescribed time when power supply from the circuit 15 is interrupted, a capacitor monitor 14 for monitoring the output voltage of the capacitor 13, and a ROM switching circuit 12 for switching connection between the ROM 10 or 11 and a data bus DB in accordance with an output from the monitor 14 when power supply from the circuit 15 is restarted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer system capable of continuing normal operation even after a power interruption, and a warm start method thereof.

[0002]

2. Description of the Related Art An ordinary computer stores programs and data directly handled by a CPU (central processing unit) in a RAM (random access memory), and generally uses a volatile memory such as a dynamic RAM as the RAM. It is a target. In such a computer, if an instantaneous power interruption occurs in which the power supply is stopped for a very short time, the data stored in the RAM will be lost. Impossible
In the worst case, the CPU runs away.

In a device such as an aircraft which requires particularly high reliability, even if a momentary power failure of the computer occurs, the interruption of the entire operation is not allowed, and the previous operation must be normally continued.

[0004] As a method of starting the computer immediately after energization, there are a cold start and a warm start. In the cold start, the power supply is stopped for a long time, and after the power supply is turned on, the computer is initialized and a ROM (read only memory) is provided.
A warm start is a method of loading a program from a RAM or a magnetic disk into a RAM. A warm start is a method in which the state immediately before power-off is stored in some storage device, for example, a magnetic disk, and the state immediately before power-on is restored. Let me
This is a method of continuing the previous operation.

[0005]

In the conventional warm start method, operations for detecting a state to be warm started, restoring the state, restarting the processing, and the like rely only on software processing. For example, the operation from the detection of a momentary power interruption to the saving of data and the operation of restoring data after resuming energization must be performed in a very short time, which imposes a heavy load on the CPU executing software. Inevitably, it takes some time from the momentary interruption of the power supply to the restart of the operation.

Further, during execution of such a save operation or a return operation, the CPU has no margin for executing other programs, which greatly affects other operations.

[0007] Further, when the data save location is a magnetic disk or a magneto-optical disk, data access time is longer than that of an electrical memory, so that many processes cannot be executed in a short time.

[0008] An object of the present invention is to provide a control system in which the CP
An object of the present invention is to provide a computer system capable of reducing the load on U and continuing the previous operation quickly and safely, and a warm start method thereof.

[0009]

According to the present invention, there is provided a central processing unit for performing arithmetic processing according to a predetermined program, a volatile RAM for storing programs and data, and a nonvolatile memory for storing a first program to be executed after power-on. Sex First
A central processing unit, a bus having a data bus and an address bus, and interconnecting the RAM and each ROM; a central processing unit; A power supply circuit that supplies power to the RAM and each ROM, a power storage element that is charged by the power supply circuit and supplies power to the RAM for a predetermined time when power supply from the power supply circuit is cut off, and an output voltage of the power storage element. A voltage monitoring means for monitoring, and a ROM switching means for switching a connection between the first ROM or the second ROM and the data bus according to an output of the voltage monitoring means when power supply from the power supply circuit is resumed. It is a computer system characterized by the following. According to the present invention, when the power supply from the power supply circuit is interrupted, the operation of the RAM can be ensured for the predetermined time by the power storage element supplying the power to the RAM for the predetermined time. Therefore, data stored in a volatile memory other than the RAM, for example, various registers in the central processing unit, a program counter, a stack pointer, or the like, or data stored in a register in a peripheral circuit or the like can be saved in the RAM. Then, when the energization is resumed, the data saved in the RAM can be quickly returned to the original memory. Further, by monitoring the output voltage of the storage element, it can be easily determined whether or not the program and the save data in the RAM are normally held. If the saved data in the RAM is retained after the power supply is resumed, the second ROM and the data bus are connected, and the operation is switched to the operation by the second program executed when the power supply is momentarily interrupted, and the warm start is executed. On the other hand, if the saved data in the RAM is destroyed after the power supply is resumed, the first ROM and the data bus are connected to switch to the operation by the first program executed when the power is turned on, and the cold start is executed.
By determining the output voltage of the storage element in this manner,
Switching between warm start and cold start can be easily realized according to the length of the instantaneous power interruption time.

The present invention also provides a central processing unit for performing arithmetic processing in accordance with a predetermined program, a volatile RAM for storing programs and data, a non-volatile first ROM for storing a first program to be executed after power-on, and , A central processing unit, a RAM, and a power supply circuit for supplying power to a first ROM, comprising: a non-volatile memory storing a second program to be executed at the moment of a power interruption, separately from the first ROM; Second ROM
When the power supply from the power supply circuit is interrupted, a power storage element that supplies power to the RAM for a predetermined time is provided, and when the power supply from the power supply circuit is restarted, the power supply voltage of the power storage element is less than the predetermined value. If present, the central processing unit is the first ROM
Executes the first program stored in the storage device. On the other hand, if the supply voltage of the storage element is equal to or higher than a predetermined value, the central processing unit
A warm start method for a computer system characterized by executing a second program stored in a ROM. According to the present invention, when the power supply from the power supply circuit is interrupted, the operation of the RAM can be ensured for the predetermined time by the power storage element supplying the power to the RAM for the predetermined time. Therefore, data stored in a volatile memory other than the RAM, for example, various registers in the central processing unit, a program counter, a stack pointer, or the like, or data stored in a register in a peripheral circuit or the like can be saved in the RAM. Then, when the energization is resumed, the data saved in the RAM can be quickly returned to the original memory. Further, by comparing the output voltage of the storage element with a predetermined value, it can be easily determined whether or not the program and the saved data in the RAM are normally held. R after energization is resumed
If the saved data of the AM is held, the connection between the second ROM and the data bus is made, and the operation is switched to the operation by the second program executed at the moment of the instantaneous power interruption, and the warm start is executed. On the other hand, if the saved data in the RAM is destroyed after the power supply is resumed, the first ROM and the data bus are connected to switch to the operation by the first program executed when the power is turned on, and the cold start is executed. By determining the output voltage of the power storage element in this manner, switching between warm start and cold start can be easily realized in accordance with the length of the instantaneous power interruption time.

[0011]

FIG. 1 is a block diagram showing an electrical configuration of an embodiment of the present invention. The computer system includes a CPU (central processing unit) 1 and a boot ROM 1.
0, a warm start ROM 11 and a RAM 20
And an input / output circuit (I / O) 21 interposed between input devices such as a keyboard, a switch and a sensor, and output devices such as a motor and an actuator, and a bus 22 for interconnecting these circuits. ing.

CPU 1 includes ROMs 10 and 11 and RA
The arithmetic processing is performed in accordance with the program stored in M20, and various registers 3 for temporarily storing data, a program counter 4 for storing the execution address of the program, and a register 3 and a program counter 4 for interrupt processing are provided in the CPU 1. A stack pointer 5 for storing an address for saving data such as data in the RAM 20, an interrupt circuit 2 for detecting a drop in the power supply voltage of the CPU 1 itself and generating an interrupt, and the like are formed.

The ROMs 10 and 11 are non-volatile memories. The ROM 10 stores a boot program to be executed after the power is turned on, and a warm start program to be executed when the power is momentarily interrupted.

The RAM 20 is composed of a volatile memory such as a dynamic RAM, and stores an OS (operation system), application programs, various data, and the like.

The bus 22 includes a data bus DB including a plurality of data lines, an address bus AB including a plurality of address lines, and a control bus CB including a plurality of control lines.

The power supply circuit 15 converts electric power supplied from commercial electric power or a generator into a DC voltage and supplies the DC voltage to the above circuit.

In this embodiment, a memory holding capacitor 13 is provided as a spare power supply for the RAM 20.
The memory holding capacitor 13 is charged by the power supply circuit 15 at the time of energization, and when the power supply from the power supply circuit 15 is cut off, the RAM 2 is stored for a predetermined time (for example, about 1 second).
Power 0.

Further, a capacitor monitor 14 for monitoring the output voltage of the memory holding capacitor 13 is provided. If the output voltage of the memory holding capacitor 13 is lower than a predetermined value, a low level is output. If it is higher than the value, a high level is output.

The ROM switching circuit 12 switches a plurality of data lines at the same time. If the output of the capacitor monitor 14 is at a low level, the ROM switch circuit 12 connects between the ROM 10 and the data bus DB.
Is high, the ROM 11 and the data bus D
B is connected.

FIG. 2 is a circuit diagram showing an example of a peripheral circuit of the memory holding capacitor 13. The power supply line VC of the power supply circuit 15 is connected to the memory holding capacitor 13 via the diode D1 for preventing backflow, and further connected to the power supply terminal of the RAM 20. A resistor R1 for determining a discharge time constant is connected to both ends of the memory holding capacitor 13, and is set so as to hold the minimum operating voltage of the RAM 20 or more for about one second after the power is stopped.

A comparator CP is used as the capacitor monitor 14, the output of the memory holding capacitor 13 is connected to the non-inverting input of the comparator CP, the reference voltage circuit VR is connected to the inverting input, and the reference voltage from the reference voltage circuit VR is applied. Er is set to the minimum operating voltage of the RAM 20. The output of the comparator CP is connected to the input of the ROM switching circuit 12.

FIG. 3 is a flowchart showing the operation. When the power is turned on after the computer system has been stopped for a long period of time, the memory holding capacitor 13 is in a discharged state. Therefore, it is determined in step s1 that the output voltage Ec of the memory holding capacitor 13 is lower than the reference voltage Er, The output of the monitor 14 becomes low level, and the ROM switching circuit 12 connects between the ROM 10 and the data bus DB.

Next, the process proceeds to step s2, after the CPU 1 is also initialized, the boot program stored in the boot ROM 10 is started, and the operating system and various application programs are transferred to the magnetic disk (non-volatile). A cold start to load the data into the RAM 20 from the illustrated position) is executed. Then, the process proceeds to step s4 and R
A predetermined program on the AM 20 starts an operation and executes a normal process.

Next, the operation at the moment of a power interruption will be described.
When the computer system is performing normal processing, another large device is started up and the capacity of the external power supply is insufficient, and the power supply circuit 1
5 may decrease for a short time. At this time,
Although the data in the RAM 20 is stored for a predetermined time by the memory holding capacitor 13, the operation of the other CPU 1 and the input / output circuit 21 becomes unstable or disabled, and the normal operation is performed even after the supply voltage of the power supply circuit 15 is restored. Is not guaranteed.

As a countermeasure, an instantaneous interruption of the power supply is detected at an early stage, and C is detected immediately before the supply voltage of the power supply circuit 15 completely decreases.
The data of the PU1 and the internal register of the input / output circuit 21 is saved in another storage device, and the saved data is returned to the original place after the supply voltage of the power supply circuit 15 is restored, so that the data before the instantaneous interruption can be quickly restored. You can recover to the state. This is called a warm start.

In the present embodiment, when the supply voltage of the power supply circuit 15 decreases, the interrupt circuit 2 generates an interrupt on the way, and the register 3, the program counter 4, the stack pointer 5, etc., according to a predetermined interrupt program. The data that is lost due to the power stop is stored in the warm start stack set in the RAM 20. Thereafter, the CPU 1 stops.

When the energization is resumed, in step s1, the output voltage Ec of the memory holding capacitor 13 and the reference voltage E
When the power supply is cut off, for example, for one second or longer, it is determined that the output voltage Ec is lower than the reference voltage Er. At this time, it is considered that the data in the RAM 20 has also been lost.
The OM 10 is selected to perform a cold start when the power is turned on.

On the other hand, if the momentary power interruption is short, after the power supply is resumed, in step s1, the memory holding capacitor 1 is turned on.
3 is compared with the reference voltage Er, and when it is determined that the output voltage Ec is equal to or higher than the reference voltage Er, the output of the capacitor monitor 14 becomes high level and the ROM
The switching circuit 12 connects between the ROM 11 and the data bus DB. At this time, the data in the RAM 20 is stored.

Next, the process proceeds to step s3, after the CPU 1 is initialized, the warm start program stored in the warm start ROM 11 is started, and
The data stored in the warm start stack of the RAM 20 is returned to the register 3, the program counter 4, the stack pointer 5, and the like. At this time, since the operating system and various application programs in the RAM 20 have not been lost, it is not necessary to reload the data from a magnetic disk or the like. Therefore, after shifting to step s4, the normal processing can be restarted from the state immediately before the momentary interruption, so that the processing interruption time can be significantly reduced as compared with the cold start.

Further, compared to the cold start, the CPU 1
Can be reduced, so that the influence on other operations can be reduced. Further, the internal data of the CPU 1 is stored in the RAM 20.
Therefore, the data access time is shorter than in the case where the data is saved to a magnetic disk or the like, and the time for the restart process can be significantly reduced.

The memory holding capacitor 13 is a RAM
It is sufficient to use a small capacity capable of maintaining 20 data retentions, or a secondary battery such as a lead storage battery or a Ni-Cd battery can be used. Further, by adjusting the capacitance of the memory holding capacitor 13, the resistance value of the resistor R1, and the reference voltage Er, the start condition of the warm start can be set arbitrarily.

[0032]

As described above in detail, according to the present invention, when power supply from the power supply circuit is cut off, various registers in the central processing unit, a program counter, a stack pointer, etc., or registers in other peripheral circuits, etc. Can be saved in the RAM.
Then, when the energization is resumed, the data saved in the RAM can be quickly returned to the original memory.

Further, by monitoring the output voltage of the storage element, switching between warm start and cold start can be easily realized according to the length of the instantaneous power interruption time.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an electrical configuration of an embodiment of the present invention.

FIG. 2 is a circuit diagram showing an example of a peripheral circuit of a memory holding capacitor 13;

FIG. 3 is a flowchart showing an operation.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 CPU 2 Interrupt circuit 3 Register 4 Program counter 5 Stack pointer 10, 11 ROM 13 Memory holding capacitor 14 Capacitor monitor 15 Power supply circuit 20 RAM 21 I / O circuit 22 Bus

Claims (2)

[Claims] A central processing unit for performing arithmetic processing according to a predetermined program; a volatile RAM for storing programs and data; a non-volatile first ROM for storing a first program to be executed after power-on; A non-volatile second ROM storing a second program to be executed at the time of disconnection; a data bus and an address bus;
A bus for interconnecting the RAM and each ROM, a power supply circuit for supplying power to the central processing unit, the RAM and each ROM, and a RAM for a predetermined time when charged by the power supply circuit and interrupted by the power supply circuit , A voltage monitoring means for monitoring an output voltage of the power storage element, and a first ROM or a second ROM according to the output of the voltage monitoring means when the power supply from the power supply circuit is restarted. And a ROM switching means for switching a connection between the computer system. 2. A central processing unit for performing arithmetic processing according to a predetermined program; a volatile RAM for storing programs and data; a non-volatile first ROM for storing a first program to be executed after power-on; A warm start method for a computer system comprising a device, a RAM, and a power supply circuit for supplying power to a first ROM, wherein a nonvolatile second ROM storing a second program to be executed at the moment of a power interruption separately from the first ROM When the power supply from the power supply circuit is interrupted, a power storage element for supplying power to the RAM for a predetermined time is provided when the power supply from the power supply circuit is restarted. If there is, the central processing unit is the first R
A computer system for executing the first program stored in the OM, and executing the second program stored in the second ROM when the supply voltage of the storage element is equal to or higher than a predetermined value. Warm start method.