JPH10198315A - Liquid crystal display device and image signal shaping circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the reduction in the quality of images while performing low-consumption electrification due to simultaneous writing, for restraining the occurrence of errors in the image position as far as possible. SOLUTION: A liquid crystal display device and an image shaping circuit are provided with a main circuit by which a set of vertical wiring signal writing transistors connected to three vertical wires of RGB out of a large number of vertical wires are simultaneously on/off operated for each set, and also in which the set being turned on is successively changed over in the order of the row, and also is provided with an image signal shaping circuit by which denoting by T the on-period of each set, three image signals are relatively delayed by (3-k)×T/3, where k=1 to 3, in the order from the top, for supplying them to a vertical wiring signal writing transistor. The image signal shaping circuit renews the image signal data being given to the vertical wiring other than the end out of at least three vertical wires nearly for each T/m (m is a natural number of 2 or more).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device using a thin film transistor, and more particularly to a liquid crystal display device having a built-in peripheral driving circuit using a polysilicon thin film transistor and the like, and an externally provided image signal shaping circuit for shaping an image signal. Further, the present invention relates to an image signal shaping circuit used for a liquid crystal display device.

[0002]

2. Description of the Related Art FIG. 6 shows a part of a circuit diagram of a liquid crystal display device incorporating a peripheral drive circuit using a polysilicon thin film transistor or the like. In FIG. 6, reference numeral 1 denotes a horizontal wiring, 2 denotes a vertical wiring, and a pixel transistor 3 and a pixel electrode 4 (not shown, but also a storage capacitor and the like) are arranged in a matrix.

The horizontal wiring 1 is connected to a scanning signal circuit 8, and the vertical wiring 2 is a signal writing transistor 5 for vertical wiring.
(In the figure, one transistor is used. However, a CMOS transistor is often used.) A signal from the image signal line 6 is written to the vertical line 2 by a signal through the shift register 10 and the buffer 7. Has become. FIG.
In this case, the same signal is input to the gate electrode of the signal writing transistor 5 for vertical wiring every three vertical wirings (usually one set of RGB). Although not shown, a liquid crystal display device is constituted by a liquid crystal and a counter electrode, peripheral members such as a backlight and a polarizing plate, and an external circuit for shaping an input signal.

FIGS. 7 (a) to 7 (f) show a conventional image signal applied to the image signal wiring 6. FIG. In FIG. 7, the R original signal 11, the G original signal 12, and the B original signal 1 separated for each of the RGB colors of (a), (b), and (c).
For 3 (vertical axis voltage, horizontal axis time), sample hold is performed at the timing indicated by the mark ●. Of the many vertical wires 2, signal writing transistors 5 for vertical wires corresponding to three adjacent vertical wires 2 corresponding to R, G, and B are set as one set.
In the case where the vertical wiring signal writing transistors 5 are simultaneously turned on / off for each group and the sets of the vertical wiring signal writing transistors 5 to be turned on are sequentially switched from left to right on the screen, one set of vertical wirings Assuming that the ON period of the application signal writing transistor is T, the timing of the mark ● is shifted by T / 3.

At the timing when the B data is held, the data is simultaneously updated for the three colors R, G, and B.
The R image signal 15, the G image signal 16, and the B image signal 17 of (d), (e), and (f) are shaped. For this conventional signal shaping, for example, a circuit configuration as shown in FIG. 10 and a timing control pulse as shown in FIG. 11 are used. SH1
SH5 is a sample and hold circuit for analog data, which holds and outputs data when the sample and hold pulses SP1 to SP3 are input. FIG.
As shown in FIG. 7, the image signal shown in FIG. 7 can be obtained by using a pulse having a cycle T with a timing shifted by T / 3 and using it as the sample hold pulses SP1 to SP3.

By using the above configuration, it becomes possible to simultaneously turn on the vertical wiring signal writing transistors 5 connected to the three vertical wirings 2 and simultaneously write data to the three vertical wirings 2 (hereinafter, referred to as the vertical wiring 2). Simultaneous writing),
The operating frequency of the shift register 10 can be reduced to 1/3 of the case where the shift register 10 is not integrated every three registers, and power consumption can be reduced. Further, by reducing the number of outputs of the shift register to 1/3, the circuit scale can be reduced.

The vertical wiring signal writing transistor 5 outputs image signals at timings (periods) 18a, 18b, 18c,... For every three vertical wirings 2 in accordance with the corresponding RGB data. Is written to the vertical wiring 2.
Normally, each of the vertical wiring signal writing transistors 5 is turned on during a period 19 corresponding to an RGB repetition period, but data writing is determined in a partial period 18a, 18b, 18c,. (The shorter the time required for 18a, 18b, and 18c, the easier to obtain a clear image).

[0008]

However, in the conventional configuration as described above, when the device is affected by variations in the element performance of the components, image blur (image position error) occurs.
Had a problem that the susceptibility was likely to occur. This will be described below with reference to the schematic diagram of FIG. In FIG.
Reference numeral 21 denotes an image signal relating to one of the image signal wirings 6 of interest, which indicates that the brightness is inverted in every RGB repetition cycle. Reference numeral 22 denotes the brightness of the corresponding pixel. In FIG. 8, (a) shows a normal case, in which light and dark are clearly displayed. On the other hand, in (b), the timing at which the vertical wiring signal writing transistors are sequentially turned on (writing is performed) (hereinafter referred to as writing timing) is relatively shifted with respect to the image signal 21, and the data is changed. In this case, the write timing overlaps with the write timing. In the case of FIG. 8B, the brightness difference between light and dark of the data is smaller than that in the case of FIG. In particular, this is a serious problem when the image is a digital source image and the data cycle is an integral multiple of the pixel cycle.

FIG. 8C shows a case where the write timing of one set of the vertical wiring signal write transistors 5 is shifted, and the write timing overlaps with the data change portion in only one place. In this case as well, dots where the brightness is not clear are generated. Such a phenomenon occurs due to, for example, uneven delay due to performance variations of elements constituting the buffer 7 (see FIG. 6).

Here, FIG. 9 shows an example in which the influence caused by the unevenness in the delay appears remarkably. This figure shows a case where a light and dark portion (for example, an oblique line slightly inclined from the vertical line) having a slight inclination with respect to the vertical direction of the screen is displayed. FIG. 8 (c)
This is related to a portion belonging to a scanning line that is vertically adjacent to the screen. 29a and 29b are systems having a write timing shift 28 which is the original signal of the image signal of the adjacent scanning line, and in the worst case, the original signal 2
9 is slightly shifted by (A), and between adjacent scanning lines, the change is two pixels apart (B).
, The brightness of the dot C, which is originally black, changes, and the image becomes uncomfortable.

Originally, an error of about one pixel (one cycle of RGB) is essential, but an error twice as large as this will occur at the worst. The problem increases as the delay variation increases with respect to the period T. In particular, the delay unevenness is T /
It is a big problem that an error of about two pixels occurs even if it is about 3 to T / 2. As described above, in a conventional liquid crystal display device having a built-in peripheral driving circuit using a polysilicon thin film transistor or the like, there is a trade-off relationship between image position error and reduction in power consumption due to simultaneous writing, and a resolution corresponding to the number of pixels is not necessarily obtained. Not occur.

An object of the present invention is to provide a liquid crystal display device capable of minimizing the occurrence of an image position error and preventing the image quality from deteriorating while reducing the power consumption and miniaturizing the circuit by simultaneous writing. An object of the present invention is to provide an image signal shaping circuit to be used.

[0013]

The liquid crystal display device according to the present invention has a vertical wiring signal writing transistor connected to each of a large number of vertical wirings, and adjacent n (n) of the many vertical wirings. Is a natural number of 2 or more) and the vertical wiring signal writing transistors corresponding to the vertical wirings are set as one set, and the vertical wiring signal writing transistors are simultaneously turned on / off for each set.
A main circuit that sequentially switches a set of vertical wiring signal writing transistors to be turned off and turned on in the order in which many vertical wirings are arranged, and an on period of one set of vertical wiring signal writing transistors is T. Then, the n image signals to be applied to the vertical wiring signal writing transistors connected to the n vertical wirings are, in order from the top, approximately (nk) × T / n; (k = 1 to n) And an image signal shaping circuit for supplying the image signal to the vertical wiring signal writing transistor with a delay. Especially,
The image signal shaping circuit updates the data of the image signal applied to at least the vertical wirings other than the last of the n vertical wirings substantially every T / m (m is a natural number of 2 or more).

Further, the image signal shaping circuit of the present invention has a signal writing transistor for vertical wiring connected to each of a large number of vertical wirings, and the adjacent n of the many vertical wirings (where n is 2 or more) (Natural number of the vertical wiring signal writing transistors corresponding to the vertical wiring) is set as a set, and the vertical wiring signal writing transistors are simultaneously turned on / off for each group and many sets of the vertical wiring signal writing transistors are turned on. It is used for a liquid crystal display device having a main circuit that sequentially switches the arrangement order of the vertical wiring,
Assuming that the ON period of a set of vertical wiring signal writing transistors is T, the n image signals to be applied to the vertical wiring signal writing transistors connected to the n vertical wirings are approximately sequentially from the top (nk). ) × T / n; (k = 1 to n), which are supplied to the vertical wiring signal writing transistor with a relatively delayed time, and which are applied to at least n vertical wirings other than the last vertical wiring. Are updated substantially every T / m (m is a natural number of 2 or more).

In this case, the image signal shaping circuit is preferably formed as an integrated circuit. According to the configuration of the present invention,
The data of the image signal given to at least the vertical wiring other than the last of the n vertical wirings is substantially T / m (m is 2
Since the image position is updated every natural number, the image position error caused by the simultaneous writing is a value obtained by adding a slight influence of delay unevenness to an essential one pixel, and it is possible to suppress the deterioration of the image quality. Further, if the image signal shaping circuit is integrated, the system can be rationalized.

In the above description, the last one of the vertical wirings may be used as it is without delaying the original image signal. Although it is described that the data is updated, there is no problem if all the data including the vertical wiring at the end is updated every T / m. The point of the present invention is that the update is performed every T / m, whereas the update is conventionally performed every T.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A liquid crystal display according to an embodiment of the present invention will be described below with reference to FIGS. Most configurations of the liquid crystal display device to which the present invention is applied in the embodiment of the present invention are the same as those of the related art, and the portions shown in FIG. Description of common parts is omitted.

In the embodiment of the present invention, the image signal applied to the image signal wiring 6 is different from that of the conventional example in the liquid crystal display device of FIG. 6, and therefore, the configuration of the image signal shaping circuit for generating this image signal is provided. Is also different. FIGS. 1A to 1F show states of image signals used in the embodiment. The difference from the conventional example shown in FIG. 7 is that the R original signal 31, the G original signal 32, and the B original signal 33 (vertical axis voltage, horizontal axis time) separated for each color of RGB are indicated by a black circle. In addition to the above timing, sample hold is performed, for example, at the timing indicated by □, and the respective timings are shifted by T / 3, where T is a time difference corresponding to the repetition period of three vertical wirings.

The difference from the conventional example is that in the embodiment of the present invention, the data is updated at the timing of T / 2 (m = 2) as a whole, and the R image signal 35, the G image signal 36, and the B image signal 37 are updated. Is to be shaped. The waveform shaping is performed by an integrated image signal shaping circuit. And
The R image signal 35, the G image signal 36, and the B image signal 37
Is simultaneously performed for each of the three vertical wirings.

The effect at this time will be described with reference to FIG.
Even if the light and dark area of the original signal 29 is shifted by A and there is a similar timing shift 28 as in FIG. 9 of the conventional example, in this case, the influence is propagated only to the area B 'at a maximum of one pixel away. No discomfort occurs in the image. Also,
FIGS. 3 and 5 are circuit diagrams each showing a configuration of an image signal shaping circuit formed into an IC for forming an image signal of the present invention (only necessary parts are shown). FIGS. 3 and 5 show the case where m = 2, respectively, in which the original signal input is performed with digital data.

In FIG. 3, input IN1 is transmitted from latch LA1 to latch LA2 and DA converter DA1 at intervals of T / 2, and input IN2 is also transmitted from latch LA3 to DA converter DA2 at intervals of T / 2. I
N3 is directly transmitted to the DA converter DA3, and the output OUT1 is a signal delayed by 2 × T / 3 with respect to the output OUT3, and the output OUT2 is delayed by T / 3 with respect to the output OUT3. The data itself is updated every T / 2.

The data delay and update as described above are as follows.
It is controlled by a control pulse supplied from the timing control unit TC. The DA converters DA1 to DA1
DA3 has both a gamma correction function and an output buffer function. Hereinafter, the operation of the circuit of FIG. 3 will be described with reference to FIG. FIG. 4 shows a circuit timing diagram of FIG. In this case, R1, R2,..., G1, G2,.
The digital data IN1, IN2, and IN3 indicated by 2,... Are designed so that six sets of data coincide with the cycle T. Latch LA1, Latch LA2, Latch LA3
Hold and output data at the timing of the timing pulses P1 and P2, respectively. DA converter DA1
The digital signal input to ＤＡDA3 is converted into analog data at the timing of the timing pulse P3, and the output is maintained until the next pulse is input. As a result, OUT1 delayed by T / 3 and updated every T / 2
To OUT3 are obtained.

FIG. 5 shows an equivalent circuit of each signal line. Latches LA1 to LA9 and DA converters DA1 to DA
A3. In this case, by letting a part of the latches LA1 to LA9 through, it is possible to perform the same operation as that of FIG. 3 or to reverse the order of the delays. The left and right inversion of the image is enabled. Specifically, the left-right inversion of the image can be achieved by reversely transferring the shift register 10 of the liquid crystal display device in FIG. 6 and inverting the RGB delay.

When a through signal is supplied, a circuit configuration in which the input digital signal is directly connected to the output of the latch without holding the digital signal is used. Making it possible. Although the above description has been made with reference to a digital input, a similar method can be considered for an analog input.

In the above description, n =
3 (simultaneous writing of RGB), but there is a possibility that n
However, the same configuration can be implemented even if the number is not 3.

[0026]

According to the liquid crystal display device and the image signal shaping circuit of the present invention, while reducing power consumption by simultaneous writing, the occurrence of image position errors is suppressed as much as possible, and the deterioration of image quality is suppressed. Effects can be obtained. At the same time, it becomes easy to eliminate the need for adjusting the writing timing for each liquid crystal display device, and the effect of simplifying production is great. That is, in the conventional system as shown in FIG. 8, it is necessary to perform timing adjustment in each liquid crystal display device. However, in the present invention, since data changes at a timing finer than the dot resolution, the timing adjustment is performed. Becomes unnecessary, and production can be simplified.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a liquid crystal display device according to an embodiment of the present invention;
6 is a time chart illustrating a relationship between a GB original signal and an RGB image signal applied to an image signal line of a panel.

FIG. 2 is a time chart for explaining the influence of image signal variation in the embodiment.

FIG. 3 is a circuit diagram illustrating a configuration of a main part of an example of an image signal shaping circuit according to an embodiment of the present invention.

FIG. 4 is a time chart for explaining the operation of FIG. 3;

FIG. 5 is a circuit diagram showing a configuration of a main part of another example of the image signal shaping circuit according to the embodiment of the present invention.

FIG. 6 is a circuit diagram showing a basic configuration of a liquid crystal display device with a built-in peripheral driving circuit to which the present invention is applied.

FIG. 7 is a time chart showing a relationship between an RGB original signal and an RGB image signal applied to an image signal line of a panel in a conventional example.

FIG. 8 is a schematic diagram for explaining an image position error.

FIG. 9 is a time chart for explaining the influence of image signal variation in the conventional example.

FIG. 10 is a circuit diagram showing a configuration of a main part of a conventional image signal shaping circuit.

FIG. 11 is a time chart for explaining the operation of the image signal shaping circuit of FIG. 10;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Horizontal wiring 2 Vertical wiring 3 Pixel transistor 4 Pixel electrode 5 Signal writing transistor for vertical wiring 6 Image signal wiring 7 Buffer 8 Scanning signal circuit 10 Shift register 11, 31 R original signal 12, 32 G original signal 13, 33 B original signal 15, 35 R image signal 16, 36 G image signal 17, 37 B image signal 18a, 18b, 18c, 18d Write timing 19 Transistor ON period 21 Image signal 22 Brightness / darkness of corresponding pixel 28 Timing shift 29 Original signal

Claims (3)

[Claims] 1. A vertical wiring signal writing transistor connected to each of a number of vertical wirings, and corresponding to adjacent n (n is a natural number of 2 or more) vertical wirings among the plurality of vertical wirings. The vertical wiring signal writing transistors are turned on / off simultaneously for each group as a set of the vertical wiring signal writing transistors, and the vertical wiring signal writing transistors are turned on. It has a main circuit that switches sequentially in the arrangement order, and when the on-period of a set of vertical wiring signal writing transistors is T, it is applied to each of the vertical wiring signal writing transistors connected to the n vertical wirings. The n image signals are sequentially delayed from the top in order by (nk) × T / n; (k = 1 to n), and the vertical wiring signal writing is performed. What is claimed is: 1. A liquid crystal display device having an image signal shaping circuit for supplying to a transistor, wherein the image signal shaping circuit generally includes at least data of the image signal given to a portion other than the last one of the n vertical wires. A liquid crystal display device which is updated every T / m (m is a natural number of 2 or more). 2. A vertical wiring signal writing transistor connected to each of a plurality of vertical wirings, and corresponding to n adjacent (n is a natural number of 2 or more) vertical wirings among the plurality of vertical wirings. The vertical wiring signal writing transistors are turned on / off simultaneously for each group as a set of the vertical wiring signal writing transistors, and the vertical wiring signal writing transistors are turned on. An image signal shaping circuit used in a liquid crystal display device having a main circuit that sequentially switches in a line-up order. When an on-period of a set of signal writing transistors for vertical wiring is T, the image signal shaping circuit is connected to the n vertical wirings. The n image signals to be applied to the vertical wiring signal writing transistors are approximately (nk) × T / n in order from the top (k = 1 to n). The data of the image signal supplied to the vertical wiring signal writing transistor after being relatively delayed by at least one of the n vertical wirings and supplied to at least the vertical wiring at the end of the n vertical wirings is approximately T / m (m Wherein the image signal is updated every two or more natural numbers. 3. The image signal shaping circuit according to claim 1, wherein the image signal shaping circuit is integrated.