JPH10197572A - Hysteresis comparator - Google Patents

Hysteresis comparator

Info

Publication number
JPH10197572A
JPH10197572A JP93997A JP93997A JPH10197572A JP H10197572 A JPH10197572 A JP H10197572A JP 93997 A JP93997 A JP 93997A JP 93997 A JP93997 A JP 93997A JP H10197572 A JPH10197572 A JP H10197572A
Authority
JP
Japan
Prior art keywords
short
hysteresis
circuit
circuit means
comparator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP93997A
Other languages
Japanese (ja)
Inventor
Hironori Saito
浩徳 斉藤
Shigeyuki Kiyota
茂之 清田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nissan Motor Co Ltd
Original Assignee
Nissan Motor Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nissan Motor Co Ltd filed Critical Nissan Motor Co Ltd
Priority to JP93997A priority Critical patent/JPH10197572A/en
Publication of JPH10197572A publication Critical patent/JPH10197572A/en
Pending legal-status Critical Current

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  • Measurement Of Current Or Voltage (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

PROBLEM TO BE SOLVED: To reduce electric power consumption by respectively connecting short-circuit means to a power source side resistance and a grounding side resistance of a reference power source generating circuit, short-circuiting the short-circuit means by a short-circuit signal from a comparator, and generating hysteresis. SOLUTION: An FET 1 and an FET 2 being short-circuit means are respectively connected to both ends of a power source side resistance R31 and a grounding side resistance R34 of a reference voltage generating circuit, and both gates of the FETs 1 and 2 are connected to the output end of a comparator 3, By constituting these in this way, the FETs 1 and 2 mutually and inversely operate according to output of the comparator 3, and generate hysteresis by short-circuiting respective both ends of resistances 31 and 34. Therefore, a constant current source to generate the hysteresis is not required, and since there is no large change in a resistance value caused by generation of the hysteresis, electric power consumption can be reduced.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、ヒステリシスコン
パレータに関し、特にヒステリシスコンパレータの低消
費電力化に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hysteresis comparator, and more particularly, to a reduction in power consumption of a hysteresis comparator.

【0002】[0002]

【従来の技術】従来より、コンパレータにヒステリシス
を発生させる技術が知られている(特開昭58−182
560号公報等参照)。図3は、かかる従来のヒステリ
シスコンパレータの回路構成を示す。このヒステリシス
コンパレータでは、スイッチS11とS12とがコンパ
レータ(以後、「COMP」と記す)1の出力に応じて
互いに逆動作する。被測定信号は入力端子INを介して
COMP1に入力される。
2. Description of the Related Art A technique for generating hysteresis in a comparator has been known (Japanese Patent Laid-Open No. 58-182).
560, etc.). FIG. 3 shows a circuit configuration of such a conventional hysteresis comparator. In this hysteresis comparator, the switches S11 and S12 operate in opposite directions to each other according to the output of the comparator (hereinafter, referred to as "COMP") 1. The signal under test is input to COMP1 via the input terminal IN.

【0003】入力端子INを介して入力された被測定信
号の信号レベルが低しきい値以下(Loレベル)である
とき、COMP1の出力はHiレベルとなり、スイッチ
S11はON、S12はOFFとなる。そして、定電流
源CS11から抵抗R12には定電流Iが供給され、C
OMP1の基準電圧(接続点Aの電圧)VA は、次式で
表される高しきい値VthHとなって安定状態となる。
When the signal level of the signal under test input via the input terminal IN is equal to or lower than the low threshold value (Lo level), the output of COMP1 becomes Hi level, the switch S11 is turned on, and the switch S12 is turned off. . Then, the constant current I is supplied from the constant current source CS11 to the resistor R12,
The reference voltage V A of the OMP 1 (the voltage at the connection point A) becomes the high threshold value VthH represented by the following equation, and enters a stable state.

【0004】VthH=R12×(Vcc+R11×I)/(R11+R12) IccH= (Vcc+R11×I)/(R11+R12) 次に被測定信号の信号レベルが高しきい値以上(Hiレ
ベル)に変化すると、COMP1の出力はLoレベルと
なり、スイッチS11はOFF、スイッチS12はON
となる。定電流源CS11から抵抗R12への定電流供
給は遮断され、定電流源CS12により抵抗R11には
定電流Iが供給される。基準電圧VA は次式で表される
低しきい値VthLとなって安定状態となる。
VthH = R12 × (Vcc + R11 × I) / (R11 + R12) IccH = (Vcc + R11 × I) / (R11 + R12) Next, the signal level of the signal under measurement is higher than the high threshold ( (Hi level), the output of COMP1 becomes Lo level, switch S11 is OFF, and switch S12 is ON.
Becomes The constant current supply from the constant current source CS11 to the resistor R12 is cut off, and the constant current I is supplied to the resistor R11 by the constant current source CS12. The reference voltage V A becomes a stable state in the low-threshold VthL represented by the following formula.

【0005】VthL=R12×(Vcc-R11×I)/(R11+R12) IccL= (Vcc+R12×I)/(R11+R12) 尚、ヒステリシスがないときの消費電流Iref、ヒステリ
シスを付加したときの消費電流増加分Ihysは、次式によ
って表される。 Iref=Vcc/(R11+R12) Vhys=2×R11 ×I/(R11+R12) Ihys=IccH-Iref=R11×I/(R11+R12) =(1/(2×R12)) ×Vhys (COMP出力Hiの時) Ihys=IccL-Iref=R12×I/(R11+R12) =(1/(2×(R11))×Vhys (COMP出力Loの時) このように、かかる従来のヒステリシスコンパレータで
は、定電流源を用いて基準電圧にヒステリシス特性を発
生させている。
VthL = R12 × (Vcc-R11 × I) / (R11 + R12) IccL = (Vcc + R12 × I) / (R11 + R12) In addition, current consumption Iref without hysteresis, and hysteresis are added. The current consumption increase Ihys at this time is expressed by the following equation. Iref = Vcc / (R11 + R12) Vhys = 2 × R11 × I / (R11 + R12) Ihys = IccH-Iref = R11 × I / (R11 + R12) = (1 / (2 × R12)) × Vhys ( (Comp output Hi) Ihys = IccL-Iref = R12 × I / (R11 + R12) = (1 / (2 × (R11)) × Vhys (Comp output Lo) Thus, this conventional hysteresis comparator In the above, a hysteresis characteristic is generated in a reference voltage using a constant current source.

【0006】ところで、ヒステリシスコンパレータは、
乾電池、バッテリー等を電源とする集積回路等にも多く
組み込まれるが、かかるヒステリシスコンパレータで
は、低消費電力化が要求される。従来のヒステリシスコ
ンパレータでは、図4に示すように、ヒステリシス特性
を有さないコンパレータに比べて消費電流Iccが増加
する。そして、この消費電流増加分Ihysは、ヒステ
リシス幅Vhysに比例して増加する。
Incidentally, the hysteresis comparator is:
Although it is often incorporated in an integrated circuit or the like using a dry cell, a battery, or the like as a power source, such a hysteresis comparator requires low power consumption. In the conventional hysteresis comparator, as shown in FIG. 4, the current consumption Icc increases as compared with a comparator having no hysteresis characteristics. Then, the increased consumption current Ihys increases in proportion to the hysteresis width Vhys.

【0007】かかる点を改善したヒステリシスコンパレ
ータとして、図5に示すようなものがある。このヒステ
リシスコンパレータは、スイッチS2を1つだけ備えて
おり、このスイッチS2は、COMP2の出力がHiレ
ベルのときはON、LoレベルのときはOFFとなる。
FIG. 5 shows an example of a hysteresis comparator in which this point is improved. This hysteresis comparator has only one switch S2, and this switch S2 is turned on when the output of COMP2 is at Hi level and turned off when the output of COMP2 is at Lo level.

【0008】被測定信号の信号レベルが低しきい値以下
であるとき、COMP2の出力はLoレベルとなり、ス
イッチS2はOFFとなり、COMP2の基準電圧(接
続点Bの電圧)VB は、次式で表される高しきい値Vt
hHとなって安定状態となる。 VthH=Vcc×(R22+R23)/(R21+R22+R23) IccH=Vcc/(R21+R22+R23) 次に被測定信号の信号レベルが、高しきい値以上に変化
したとき、COMP2の出力はHiレベルとなり、スイ
ッチS2はONとなり、基準電圧VB は、次式で表され
る低しきい値VthLとなって安定状態となる。
[0008] When the signal level of the measured signal is below the low threshold, the output of COMP2 becomes Lo level, the switch S2 is turned OFF, the V B (voltage at the connection point B) reference voltage COMP2, the following equation High threshold Vt expressed by
hH, and becomes a stable state. VthH = Vcc × (R22 + R23) / (R21 + R22 + R23) IccH = Vcc / (R21 + R22 + R23) Next, when the signal level of the signal under measurement changes above the high threshold, COMP2 the output becomes Hi level, the switch S2 is turned ON, the reference voltage V B becomes a stable state in the low-threshold VthL represented by the following formula.

【0009】VthL=Vcc×R22/(R21+R22) IccL=Vcc/(R21+R22) 尚、ヒステリシス回路がない場合の消費電流Iref、
ヒステリシス幅Vhys、及びヒステリス発生回路を設
けたことによる消費電流増加分Ihysは次式によって
表される。
VthL = Vcc × R22 / (R21 + R22) IccL = Vcc / (R21 + R22) Note that the current consumption Iref without the hysteresis circuit is
The hysteresis width Vhys and the increase in current consumption Ihys due to the provision of the hysteresis generation circuit are expressed by the following equations.

【0010】Iref=Vcc/(R21+R22+R23) Vhys=R21×R23 ×Vcc/((R21+R22+R23)×((R21+R22)) Ihys=IccH-Iref=0 (COMP出力Hi時) Ihys=IccL-Iref=(1/R21)×VhyS (COMP出力Lo時) このように、図5に示すようなヒステリシスコンパレー
タでは、ヒステリシスを発生させるための定電流源を必
要とせず、COMP出力Hiの時の消費電力増加分がカ
ットされ、低消費電力化が図られている。
Iref = Vcc / (R21 + R22 + R23) Vhys = R21 × R23 × Vcc / ((R21 + R22 + R23) × ((R21 + R22)) Ihys = IccH−Iref = 0 (when COMP output is Hi Ihys = IccL−Iref = (1 / R21) × VhyS (when COMP output is low) As described above, the hysteresis comparator as shown in FIG. 5 does not require a constant current source for generating hysteresis and outputs the COMP output. The increase in power consumption at the time of Hi is cut, and power consumption is reduced.

【0011】[0011]

【発明が解決しようとする課題】しかしながら、かかる
従来のヒステリシスコンパレータでも、基準電圧発生回
路の分圧抵抗の分圧比を変えたとき(COMP出力Lo
の時)、同時に、分圧抵抗の合成抵抗も大きく低下する
ので、図6に示すように、ヒステリシス発生時に消費電
流が増加してしまう。そして、この消費電流はヒステリ
シス幅に比例して増加する。
However, even in such a conventional hysteresis comparator, when the voltage dividing ratio of the voltage dividing resistor of the reference voltage generating circuit is changed (COMP output Lo).
At the same time, at the same time, the combined resistance of the voltage dividing resistors is greatly reduced, so that the current consumption increases when the hysteresis occurs, as shown in FIG. This current consumption increases in proportion to the hysteresis width.

【0012】従って、乾電池、バッテリー等を電源とす
る集積回路等に組み込むようなヒステリシスコンパレー
タでは、さらに低消費電力化を図る必要がある。本発明
はこのような従来の課題に鑑みてなされたもので、低消
費電力化が可能なヒステリシスコンパレータを提供する
ことを目的とする。
Accordingly, it is necessary to further reduce the power consumption of a hysteresis comparator incorporated in an integrated circuit or the like using a dry cell, a battery, or the like as a power supply. The present invention has been made in view of such conventional problems, and has as its object to provide a hysteresis comparator capable of reducing power consumption.

【0013】[0013]

【課題を解決するための手段】このため、請求項1の発
明にかかるヒステリスコンパレータは、複数の抵抗を用
いて電源電圧を分圧し、基準電圧を発生させる基準電圧
発生手段と、短絡信号が入力されたとき、電源側の抵抗
を短絡する第1の短絡手段と、短絡信号が入力されたと
き、接地側の抵抗を短絡する第2の短絡手段と、被測定
信号及び基準電圧を入力し、被測定信号の信号レベルと
基準電圧との比較結果に応じて短絡信号を第1の短絡手
段又は第2の短絡手段に出力するコンパレータと、を備
えて構成されている。
Therefore, a hysteresis comparator according to the first aspect of the present invention divides a power supply voltage using a plurality of resistors to generate a reference voltage, and a short-circuit signal. A first short-circuiting means for short-circuiting the resistance on the power supply side when input, a second short-circuiting means for short-circuiting the resistance on the ground side when a short-circuit signal is input, and inputting a signal to be measured and a reference voltage. And a comparator for outputting a short-circuit signal to the first short-circuit means or the second short-circuit means in accordance with the comparison result between the signal level of the signal under measurement and the reference voltage.

【0014】かかる構成によれば、電源電圧が基準電圧
発生手段の複数の分圧抵抗によって分圧され、これによ
り基準電圧が発生する。被測定信号は、コンパレータに
よりこの基準電圧と比較される。そして、被測定信号の
信号レベルと基準電圧との比較結果に応じて短絡信号が
コンパレータから第1の短絡手段又は第2の短絡手段に
出力される。従って、第1の短絡手段と第2の短絡手段
とは、逆動作となり、第1の短絡手段に短絡信号が出力
されたときは、第1の短絡手段により電源側の抵抗が短
絡されて電源側の抵抗値が小さくなり、第2の短絡手段
に短絡信号が出力されたときは、接地側の抵抗が短絡さ
れて接地側の抵抗値が小さくなり、これにより、基準電
圧が変化してヒステリシスが発生する。また、電源側、
接地側の抵抗の導通・短絡が切り換えられるだけなの
で、ヒステリシス発生に伴う大きな電流変化が生じなく
なり、ヒステリシス幅が変わっても消費電流はあまり変
化しない。
According to this configuration, the power supply voltage is divided by the plurality of voltage dividing resistors of the reference voltage generating means, thereby generating the reference voltage. The signal under test is compared with this reference voltage by a comparator. Then, a short-circuit signal is output from the comparator to the first short-circuit means or the second short-circuit means according to the result of comparison between the signal level of the signal under measurement and the reference voltage. Therefore, the first short-circuit means and the second short-circuit means operate in reverse, and when a short-circuit signal is output to the first short-circuit means, the resistance on the power supply side is short-circuited by the first short-circuit means and the power supply is short-circuited. When the short-circuit signal is output to the second short-circuit means, the resistance on the ground side is short-circuited and the resistance value on the ground side is reduced, whereby the reference voltage changes and the hysteresis is reduced. Occurs. Also, on the power side,
Since only conduction / short-circuiting of the ground-side resistor is switched, a large current change due to the occurrence of hysteresis does not occur, and the current consumption does not change much even if the hysteresis width changes.

【0015】請求項2の発明にかかるヒステリスコンパ
レータでは、前記第1の短絡手段により短絡される電源
側の抵抗と、第2の短絡手段により短絡される接地側の
抵抗と、は同じ抵抗値を有している。かかる構成によれ
ば、第1の短絡手段、第2の短絡手段による短絡抵抗が
切り換えられても、電源側、接地側の抵抗が同一の抵抗
値を有しているので、動作状態に関わりなく消費電流は
一定に保持される。
In the hysteresis comparator according to a second aspect of the present invention, the resistance on the power supply side short-circuited by the first short-circuit means and the resistance on the ground side short-circuited by the second short-circuit means have the same resistance value. have. According to such a configuration, even if the short-circuit resistance by the first short-circuit means and the second short-circuit means is switched, the resistances on the power supply side and the ground side have the same resistance value, regardless of the operation state. The current consumption is kept constant.

【0016】請求項3の発明にかかるヒステリスコンパ
レータでは、前記第1の短絡手段、第2の短絡手段は、
電界効果トランジスタである。かかる構成によれば、電
界効果トランジスタにより短絡、短絡解除の切り換えが
素早く行われる。
In the hysteresis comparator according to the third aspect of the present invention, the first short-circuit means and the second short-circuit means
It is a field effect transistor. According to such a configuration, switching between short-circuit and short-circuit release is quickly performed by the field-effect transistor.

【0017】[0017]

【発明の効果】請求項1の発明にかかるヒステリシスコ
ンパレータによれば、ヒステリシスを発生させるための
定電流源を必要とせず、ヒステリシス発生に伴う大きな
消費電流の増加もない。さらに、ヒステリシス幅が増加
しても消費電流の増加を殆ど無視することが出来、低消
費電力化を図ることができる。よって、乾電池、バッテ
リー等を電源とする集積回路に使用するには、極めて効
果的である。
According to the hysteresis comparator according to the first aspect of the present invention, there is no need for a constant current source for generating hysteresis, and there is no large increase in current consumption due to the occurrence of hysteresis. Furthermore, even if the hysteresis width increases, the increase in current consumption can be almost ignored, and power consumption can be reduced. Therefore, it is extremely effective for use in an integrated circuit using a dry cell, a battery, or the like as a power source.

【0018】請求項2の発明にかかるヒステリシスコン
パレータによれば、動作状態に関係なく消費電流を一定
に保つことができる。請求項3の発明にかかるヒステリ
シスコンパレータによれば、スイッチング速度が早くな
る。
According to the hysteresis comparator according to the second aspect of the present invention, the current consumption can be kept constant regardless of the operation state. According to the hysteresis comparator of the third aspect, the switching speed is increased.

【0019】[0019]

【発明の実施の形態】以下、本発明の実施の形態を図1
及び図2に基づいて説明する。図1は、本実施の形態を
示す。本実施の形態を示す図1において、被測定信号
は、入力端子INを介してCOMP(コンパレータ)3
の非反転入力端子(+)に入力され、COMP3の出力
信号は、出力端子OUTから出力される。
FIG. 1 is a block diagram showing an embodiment of the present invention.
A description will be given based on FIG. FIG. 1 shows this embodiment. In FIG. 1 showing the present embodiment, a signal to be measured is supplied to a COMP (comparator) 3 via an input terminal IN.
And the output signal of COMP3 is output from the output terminal OUT.

【0020】電源と接地間には、4つの抵抗R31、R
32、R33、R34が直列に接続されている。抵抗R
31と抵抗R34とは同一抵抗値を有する。COMP3
の反転入力端子(−)には、基準電圧として抵抗R32
と抵抗R33との接続点Cの電圧VC が入力される。こ
の4つの抵抗R31〜R34により基準電圧発生手段と
しての基準電圧発生回路が構成されている。
Between the power supply and the ground, four resistors R31 and R
32, R33, and R34 are connected in series. Resistance R
31 and the resistor R34 have the same resistance value. COMP3
Of the resistor R32 as a reference voltage.
Voltage V C of the connection point C is input and the resistor R33. The four resistors R31 to R34 constitute a reference voltage generation circuit as reference voltage generation means.

【0021】抵抗R31,R34の両端には、抵抗R3
1,R34を短絡するように、夫々、pチャンネルMO
S(Metal oxide silicon) 形電界効果トランジスタ1
(以後、「FET1」と記す)、nチャンネルMOS形
電界効果トランジスタ2(以後、「FET2」と記す)
が接続されている。FET1,2のゲートは、共にCO
MP3の出力端に接続され、COMP3の出力信号がF
ET1又はFET2のゲートに出力される。この出力信
号が短絡信号に相当し、その信号レベルに応じてFET
1、2は、互いに逆動作をする。
A resistor R3 is connected to both ends of the resistors R31 and R34.
1 and R34 are short-circuited, respectively,
Metal oxide silicon (S) field effect transistor 1
(Hereinafter referred to as "FET1"), n-channel MOS field effect transistor 2 (hereinafter referred to as "FET2")
Is connected. The gates of the FETs 1 and 2 are both CO
Connected to the output terminal of MP3, and the output signal of COMP3 is F
Output to the gate of ET1 or FET2. This output signal corresponds to the short circuit signal, and the FET
1 and 2 operate in opposite directions.

【0022】このFET1,2が、夫々、第1の短絡手
段、第2の短絡手段に相当する。次に動作を説明する。
入力端子INを介して入力された測定信号の信号レベル
が低しきい値以下であるとき、COMP3の出力信号の
信号レベルはHiとなる。この出力信号は、出力端子O
UTから出力される一方、FET1,2にも入力され
る。これにより、FET1は、ON(導通)し、抵抗R
31が短絡される。
The FETs 1 and 2 correspond to first short-circuit means and second short-circuit means, respectively. Next, the operation will be described.
When the signal level of the measurement signal input via the input terminal IN is equal to or lower than the low threshold, the signal level of the output signal of COMP3 becomes Hi. This output signal is output from an output terminal O
While being output from the UT, it is also input to the FETs 1 and 2. As a result, the FET 1 is turned on (conducting), and the resistance R
31 is short-circuited.

【0023】一方、FET2は、FET1とは逆にOF
F(非導通)となる。従って、電源と接地間の抵抗は、
R32〜R34となり、COMP3のしきい値となる基
準電圧は、次式で表される高しきい値VthHとなって
安定状態となる。 VthH=Vcc×(R33+R34)/(R32+R33+R34) IccH=Vcc/(R32+R33+R34) 但し、Vcc :電源電圧 IccH:高しきい値VthH時の消費電流 R32 〜R34 :抵抗R32 〜R34 の抵抗値 次に被測定信号の信号レベルが高しきい値以上に変化し
たとき、COMP3の出力信号はLoレベルとなり、F
ET1はOFFとなり、FET2はONとなる。これに
より、抵抗R34が短絡され、COMP3の基準電圧
は、次式で表される低しきい値VthLとなって安定状
態となる。
On the other hand, the FET 2 has an OF
F (non-conduction). Therefore, the resistance between the power supply and ground is
R32 to R34, the reference voltage serving as the threshold value of COMP3 becomes the high threshold value VthH represented by the following equation, and is in a stable state. VthH = Vcc × (R33 + R34) / (R32 + R33 + R34) IccH = Vcc / (R32 + R33 + R34) where Vcc: power supply voltage IccH: current consumption at high threshold VthH R32 to R34: resistance Next, when the signal level of the signal under measurement changes above the high threshold value, the output signal of COMP3 becomes Lo level,
ET1 is turned off and FET2 is turned on. As a result, the resistor R34 is short-circuited, and the reference voltage of COMP3 becomes the low threshold value VthL expressed by the following equation, and enters a stable state.

【0024】VthL=Vcc×R33/(R31+R32+R33) IccL=Vcc/(R31+R32+R33) 但し、IccL:低しきい値VthL時の消費電流 R31 :抵抗R31 の抵抗値 ここで、抵抗R31と抵抗R34とは同一抵抗値を有し
ているから、消費電流IccHとIccLとは等しくな
り、次式で示すようになる。
VthL = Vcc × R33 / (R31 + R32 + R33) IccL = Vcc / (R31 + R32 + R33) where IccL: current consumption at low threshold VthL R31: resistance value of resistor R31 Since the resistors R31 and R34 have the same resistance value, the consumption currents IccH and IccL are equal, and are expressed by the following equation.

【0025】IccH=IccL=Vcc/(R31+R32+R) 但し、R=R31=R34 また、ヒステリシス回路がない場合の消費電流Ire
f,ヒステリシス発生前後に於ける消費電流増加分Ih
ysは次式によって表される。 Iref=Vcc/(R32+R33+R) (ヒステリシスを持たせない場合は、R31 又はR34 は不
用となる) Ihys=IccH-Iref=0 (COMP出力Hi時) Ihys=IccH-Iref=0 (COMP出力Lo時) 従って、基準電圧発生回路に於ける消費電流Iccは、
図2に示すように一定に保持される。
IccH = IccL = Vcc / (R31 + R32 + R) where R = R31 = R34 Also, the current consumption Ire without the hysteresis circuit
f, increase in consumption current Ih before and after occurrence of hysteresis
ys is represented by the following equation. Iref = Vcc / (R32 + R33 + R) (If there is no hysteresis, R31 or R34 is unnecessary.) Ihys = IccH-Iref = 0 (when COMP output is Hi) Ihys = IccH-Iref = 0 (COMP Therefore, the consumption current Icc in the reference voltage generation circuit is
It is kept constant as shown in FIG.

【0026】次に、ヒステリシス幅Vhysは、次式に
よって表される。 Vhys=VthH-VthL=(R/(R32+R33+R))×Vcc 従って、抵抗R31と抵抗R34との抵抗値を高くすれ
ばヒステリシス幅Vhysも大きくなる。かかる構成に
よれば、COMP3の出力に応じて互いに逆動作をする
短絡用のFET1,2を、夫々、基準電圧発生回路の電
源側抵抗R31、接地側抵抗R34の両端に接続してヒ
ステリシスを発生させるようにしたので、ヒステリシス
を発生させるための電流を必要とせず、また、ヒステリ
ス発生に伴う抵抗値の大きな変化もないので、低消費電
力化を図ることができる。さらに、ヒステリシス幅が増
加しても消費電流の増加を無視することが出来る。
Next, the hysteresis width Vhys is expressed by the following equation. Vhys = VthH−VthL = (R / (R32 + R33 + R)) × Vcc Therefore, if the resistance values of the resistors R31 and R34 are increased, the hysteresis width Vhys is also increased. According to this configuration, the short-circuit FETs 1 and 2 that operate in opposite directions according to the output of the COMP 3 are connected to both ends of the power-supply-side resistor R31 and the ground-side resistor R34 of the reference voltage generating circuit to generate hysteresis. As a result, a current for generating hysteresis is not required, and there is no large change in resistance value due to the generation of hysteresis, so that power consumption can be reduced. Furthermore, even if the hysteresis width increases, the increase in current consumption can be ignored.

【0027】従って、電源に乾電池、バッテリー等を使
用するために消費電流を抑えることを必要とする集積回
路に於いて極めて効果的である。また、短絡される抵抗
R31と抵抗R34との抵抗値を同一とすることによ
り、基準電圧発生回路に於ける消費電流Iccを一定に
保持することが出来る。尚、本実施の形態では、分圧抵
抗の短絡手段として、FETを用いたが、これに限ら
ず、例えばバイポーラトランジスタ等を用いることもで
きる。
Therefore, the present invention is extremely effective for an integrated circuit that requires a reduction in current consumption in order to use a dry cell, a battery, or the like as a power supply. Further, by making the resistance values of the short-circuited resistor R31 and the resistor R34 the same, the current consumption Icc in the reference voltage generating circuit can be kept constant. In this embodiment, the FET is used as the short-circuit means of the voltage dividing resistor. However, the present invention is not limited to this. For example, a bipolar transistor or the like can be used.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施の形態を示す回路図。FIG. 1 is a circuit diagram illustrating an embodiment of the present invention.

【図2】図1の動作を示すタイミングチャート。FIG. 2 is a timing chart showing the operation of FIG.

【図3】従来のヒステリスコンパレータの回路図。FIG. 3 is a circuit diagram of a conventional hysteresis comparator.

【図4】図3の動作を示すタイミングチャート。FIG. 4 is a timing chart showing the operation of FIG. 3;

【図5】従来の別のヒステリスコンパレータの回路図。FIG. 5 is a circuit diagram of another conventional hysteresis comparator.

【図6】図4の動作を示すタイミングチャート。FIG. 6 is a timing chart showing the operation of FIG.

【符号の説明】[Explanation of symbols]

COMP3 コンパレータ FET1 pチャンネルMOS形電界効果トランジスタ FET2 nチャンネルMOS形電界効果トランジスタ COMP3 Comparator FET1 P-channel MOS field effect transistor FET2 N-channel MOS field effect transistor

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】複数の抵抗を用いて電源電圧を分圧し、基
準電圧を発生させる基準電圧発生手段と、 短絡信号が入力されたとき、電源側の抵抗を短絡する第
1の短絡手段と、 短絡信号が入力されたとき、接地側の抵抗を短絡する第
2の短絡手段と、 被測定信号及び基準電圧を入力し、被測定信号の信号レ
ベルと基準電圧との比較結果に応じて短絡信号を第1の
短絡手段又は第2の短絡手段に出力するコンパレータ
と、を備えて構成されたことを特徴とするヒステリシス
コンパレータ。
1. A reference voltage generating means for dividing a power supply voltage using a plurality of resistors to generate a reference voltage; a first short-circuit means for short-circuiting a resistor on a power supply side when a short-circuit signal is input; A second short-circuit means for short-circuiting a ground-side resistor when a short-circuit signal is input; a signal to be measured and a reference voltage being inputted; And a comparator that outputs the signal to the first short-circuit means or the second short-circuit means.
【請求項2】前記第1の短絡手段により短絡される電源
側の抵抗と、第2の短絡手段により短絡される接地側の
抵抗と、は同じ抵抗値を有していることを特徴とする請
求項1に記載のヒステリシスコンパレータ。
2. A power supply-side resistance short-circuited by said first short-circuit means and a ground-side resistance short-circuited by said second short-circuit means have the same resistance value. The hysteresis comparator according to claim 1.
【請求項3】前記第1の短絡手段及び第2の短絡手段
は、電界効果トランジスタであることを特徴とする請求
項1又は請求項2に記載のヒステリシスコンパレータ。
3. The hysteresis comparator according to claim 1, wherein said first short-circuit means and said second short-circuit means are field effect transistors.
JP93997A 1997-01-07 1997-01-07 Hysteresis comparator Pending JPH10197572A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP93997A JPH10197572A (en) 1997-01-07 1997-01-07 Hysteresis comparator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP93997A JPH10197572A (en) 1997-01-07 1997-01-07 Hysteresis comparator

Publications (1)

Publication Number Publication Date
JPH10197572A true JPH10197572A (en) 1998-07-31

Family

ID=11487653

Family Applications (1)

Application Number Title Priority Date Filing Date
JP93997A Pending JPH10197572A (en) 1997-01-07 1997-01-07 Hysteresis comparator

Country Status (1)

Country Link
JP (1) JPH10197572A (en)

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000072028A1 (en) * 1999-05-21 2000-11-30 Micrel Incorporated Voltage monitor circuit with adjustable hysteresis using a single comparator
EP1404018A1 (en) * 2002-09-26 2004-03-31 Koyo Seiko Co., Ltd. Hysteresis characteristic setting device and hysteresis characteristic setting method
JP2007088748A (en) * 2005-09-21 2007-04-05 Sony Corp Waveform shaping circuit and semiconductor integrated circuit equipped with it
JP2007295410A (en) * 2006-04-26 2007-11-08 Interchip Kk Pulse signal generator and clock signal generator
JP2008125176A (en) * 2006-11-09 2008-05-29 Fuji Electric Device Technology Co Ltd Hysteresis comparator circuit and power supply switching circuit
JP2010258950A (en) * 2009-04-28 2010-11-11 Seiko Epson Corp Comparison circuit, integrated circuit device, and electronic apparatus
JP2012503465A (en) * 2008-09-23 2012-02-02 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ Current limit control for power supplies with automatic reset, eg LED drivers
CN108649934A (en) * 2018-05-31 2018-10-12 成都锐成芯微科技股份有限公司 A kind of hysteresis comparator circuit
WO2018235373A1 (en) * 2017-06-21 2018-12-27 株式会社デンソー Comparator with hysteresis
JP2019203851A (en) * 2018-05-25 2019-11-28 エイブリック株式会社 Voltage detector
CN113484589A (en) * 2021-06-30 2021-10-08 杭州加速科技有限公司 Power-off detection circuit with hysteresis function and control system

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000072028A1 (en) * 1999-05-21 2000-11-30 Micrel Incorporated Voltage monitor circuit with adjustable hysteresis using a single comparator
US6304088B1 (en) 1999-05-21 2001-10-16 Micrel Incorporated Voltage monitor circuit with adjustable hysteresis using a single comparator
EP1404018A1 (en) * 2002-09-26 2004-03-31 Koyo Seiko Co., Ltd. Hysteresis characteristic setting device and hysteresis characteristic setting method
US7003408B2 (en) 2002-09-26 2006-02-21 Koyo Seiko Co., Ltd. Hysteresis characteristic setting device and hysteresis characteristic setting method
JP2007088748A (en) * 2005-09-21 2007-04-05 Sony Corp Waveform shaping circuit and semiconductor integrated circuit equipped with it
JP2007295410A (en) * 2006-04-26 2007-11-08 Interchip Kk Pulse signal generator and clock signal generator
JP2008125176A (en) * 2006-11-09 2008-05-29 Fuji Electric Device Technology Co Ltd Hysteresis comparator circuit and power supply switching circuit
JP4720722B2 (en) * 2006-11-09 2011-07-13 富士電機システムズ株式会社 Hysteresis comparator circuit and power supply switching circuit
JP2012503465A (en) * 2008-09-23 2012-02-02 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ Current limit control for power supplies with automatic reset, eg LED drivers
JP2010258950A (en) * 2009-04-28 2010-11-11 Seiko Epson Corp Comparison circuit, integrated circuit device, and electronic apparatus
WO2018235373A1 (en) * 2017-06-21 2018-12-27 株式会社デンソー Comparator with hysteresis
JP2019203851A (en) * 2018-05-25 2019-11-28 エイブリック株式会社 Voltage detector
CN108649934A (en) * 2018-05-31 2018-10-12 成都锐成芯微科技股份有限公司 A kind of hysteresis comparator circuit
CN113484589A (en) * 2021-06-30 2021-10-08 杭州加速科技有限公司 Power-off detection circuit with hysteresis function and control system

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