JPH10189955A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the deterioration of the covering property of metal in an electrode, even if a contact size is reduced by providing the constitution, wherein a silicon oxide film, in which nitrogen atoms are diffused in the vicinity of a gate electrode and a silicon nitride film is not provided at the side surface of an opening part for electrode lead-out. SOLUTION: A first interlayer silicon oxide film 5 is provided on a transistor. The upper part of the film becomes a silicon-nitride oxide layer 5a formed by diffusing nitrogen atoms from the outside. Furthermore, a second interlayer silicon oxide film 7, which becomes an insulating-layer intermediate film between a wiring and a substrate, is provided on the layer 5a. A contact hole 8, which is the opening part for drawing the electrode from the source/drain diffused layer, is provided on a high-concentration N-type diffused layer 22 for the source/drain. When the contact hole 8 is opened, the silicon nitride film has already been removed. Therefore, even if titanium nitride titanium 9 is sputtered as an electrode in the inside, the decrease in covering property caused by the eave of the silicon nitride film does not occur.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having a highly integrated fine opening having a high aspect ratio and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, this type of semiconductor device has been disclosed in
As shown in JP-A-243520, a silicon nitride film is present on a side surface of an electrode lead-out opening (hereinafter, referred to as a contact).

FIG. 7 is a sectional view showing a conventional semiconductor device of this type.

Using a known technique, a field silicon oxide film 102, a gate insulating film 103, and a gate polycrystalline silicon 1 partially buried in a P-type silicon substrate 101.
05, a side wall insulating film 107, a silicon oxide film 104, a low concentration N-type diffusion layer 106 serving as a source / drain, and a high concentration N-type diffusion layer 108 are formed.

Subsequently, a three-layer film including a first interlayer silicon oxide film 120, a silicon nitride film 121, and a second interlayer silicon oxide film 122 is formed by a CVD method.

This is because a high yield semiconductor device is manufactured by increasing the etching selectivity when forming the first contact hole 111 of the SAC (self-aligned contact) type and expanding the margin of the contact etching rate. This is to make it possible.

After forming a first contact hole 111 by opening a three-layer structure of a first interlayer silicon oxide film 120, a silicon nitride film 121 and a second interlayer silicon oxide film 122, a stacked polysilicon 112, a capacitor insulating film 113
In addition, a capacitive element made of capacitive polycrystalline silicon 114 is formed. Then, the third silicon oxide film 1 of the BPSG film
15, a second contact hole 116 is opened, and a bit line 117 is formed of metal.

Here, a protruding eave 151 formed of the silicon nitride film 121 is present in the first contact hole 111, but this conventional semiconductor device has no problem because the contact size is large. .

Although not intended in the publication cited here, since the silicon nitride film does not allow hydrogen ions to pass therethrough, transistor characteristic fluctuations (hereinafter, 2nd slow trap) caused by hydrogen ion penetration from the upper layer into the gate oxide film. ) May be applied to the vicinity of the gate electrode with a silicon nitride film.

When a silicon nitride film is formed on a silicon oxide film, nitrogen atoms are diffused at the interface of the silicon oxide film, and a layer of a nitrided silicon oxide film is formed.

[0011]

A first problem of the above prior art is that when the contact size is reduced and the aspect ratio is increased, the conductivity of the electrode is deteriorated and desired characteristics cannot be obtained. That is.

The reason is that a projection-like eaves is formed by a silicon nitride film on the side surface inside the contact,
This is because the coatability of the electrode in the shaded portion of the eaves is deteriorated.

More specifically, after a contact is first opened, a silicon oxide film, that is, a natural oxide film is naturally formed on the silicon surface at the bottom of the contact as time passes. Therefore, if an electrode is formed as it is, conduction failure may be caused by a natural oxide film. Therefore, a natural oxide film is removed by wet etching before forming an electrode (hereinafter, referred to as a pre-sputtering process).

When the pre-sputtering process is performed, the silicon oxide film on the side wall inside the contact is etched simultaneously with the natural oxide film, whereas the silicon nitride film is not etched. As a result, the eaves of the silicon nitride film are formed at those portions, and the metal coatability in the shaded portions of the eaves is deteriorated when the electrodes are formed.

[0015] The higher the aspect ratio of the contact, the worse the coverage, and this is likely to be a problem.

The second problem is that the reliability of the semiconductor device is reduced when the coverage of the electrode metal is deteriorated as described above.

The reason for this is that if there is a portion of the electrode having poor metal coverage, poor conduction tends to occur over time, and the quality of the semiconductor device itself deteriorates.

Accordingly, an object of the present invention is to prevent the deterioration of the metal coverage on the electrodes even if the contact size is reduced, while having the function of suppressing the fluctuation of the transistor characteristics due to the second steep slap. An object of the present invention is to provide a highly reliable semiconductor device and a method for manufacturing the same.

[0019]

A feature of the present invention is that an insulated gate field effect transistor has a silicon oxide film in which nitrogen atoms are diffused in the vicinity of a gate electrode and a silicon nitride film on a side surface in an electrode lead-out opening. In a semiconductor device having no. Here, it is preferable that the silicon oxide film has a layer in which the nitrogen atoms are diffused by a CVD method. Further, the electrode lead-out opening may be an opening for drawing out an electrode from the source / drain diffusion layer.

Another feature of the present invention is that after forming the gate electrode,
Sequentially forming a first interlayer silicon oxide film, forming a silicon nitride film and diffusing nitrogen atoms into the first interlayer silicon oxide film, removing the silicon nitride film, Forming a two-layer silicon oxide film;
Forming an opening for leading out an electrode in the first interlayer silicon oxide film. Here, the silicon nitride film is formed by a CVD method,
During the formation, it is preferable that nitrogen atoms are diffused into the first interlayer silicon oxide film. Further, as a method for removing the silicon nitride film, a dry etching method can be used. Further, as a method for removing the silicon nitride film, a wet etching method can be used. Further, as a method for removing the silicon nitride film, by partially etching the electrode lead-out opening region using a photolithography method and an etching method,
The opening and its surrounding silicon nitride film can be selectively removed.

The present invention has the following functions.

A: In the pre-sputtering process, the silicon nitride film sandwiched between the two interlayer silicon oxide films and causing the projection-like eaves is removed before the contact opening, thereby reducing the contact size. Even so, the formation of eaves on the side surface inside the contact is prevented.
Therefore, a portion with poor metal coverage does not occur in the electrode, and an electrode with good conductivity can be manufactured.

B: Even if the silicon nitride film is removed, the provision of the nitrided silicon oxide layer enables the contact size to be reduced while having the effect of suppressing the transistor characteristic fluctuation due to the second slow trap.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings.

FIG. 1 is a sectional view of a semiconductor device according to the first embodiment of the present invention. In the figure, a thick field silicon oxide film 2 partially buried in a substrate is provided on a field region of a P-type silicon substrate 1, and a gate insulating film is formed on an element region of the silicon substrate 1 defined by the field oxide film 2. 12. Gate electrode and sidewall insulating film 4 made of polycrystalline silicon 3 and tungsten silicon 13
Are formed to form a gate structure. In the element region, an LDD type source / drain diffusion layer including a low concentration N type diffusion layer 21 and a high concentration N type diffusion layer 22 is formed. It constitutes an insulated gate field effect transistor.

A first interlayer silicon oxide film 5 is provided on the transistor, and the upper portion is a silicon nitride oxide layer 5a formed by diffusing nitrogen atoms from the outside.

The silicon nitride oxide layer 5a is a barrier film against intrusion of hydrogen ions from an upper layer which causes a change in transistor characteristics.

A second interlayer silicon oxide film 7 serving as an insulating interlayer film between the wiring and the substrate is further provided thereon, and the source / drain diffusion layer 22 is provided on the high-concentration source / drain N type diffusion layer 22. A contact hole 8 is provided as an opening for drawing out the metal. A peripheral titanium titanium nitride 9 and an electrode of buried tungsten 10 are provided inside the contact hole 8, and a wiring 11 formed by patterning a metal thereon is provided. Is provided.

Next, FIGS. 2A to 3C are cross-sectional views showing the steps of manufacturing the semiconductor device according to the first embodiment of the present invention in the order of steps.

First, in FIG. 2A, the thickness is 690 μm.
Is generally placed on the field region of the P-type silicon substrate 1
A field oxide film 2 partially buried in the substrate is formed by a selective thermal oxidation method called a COS method, and a 9 nm-thick gate is formed on the element region of the silicon substrate 1 partitioned by the field oxide film 2. After forming the oxide film 12,
A 150 nm-thick polycrystalline silicon 3 is grown by a CVD method, a tungsten silicon 13 is deposited to a thickness of 150 nm by a sputtering method, and is patterned by a photolithography method with a width of 0.35 μm to obtain a gate electrode.

After the low concentration N-type diffusion layer 21 is formed by ion implantation using the gate electrode and the field oxide film 2 as a mask, a silicon oxide film is grown to a thickness of 200 nm by CVD on the entire surface to form an anisotropic dry film. Etching is performed to form the sidewall insulating film 4. Then, a high-concentration N-type diffusion layer 22 is formed by high-energy ion implantation.

After that, the film thickness is 150 nm by the CVD method.
Of the first interlayer silicon oxide film 5 is grown.

Next, referring to FIG. 2B, a silicon nitride film 6 represented by Si ₃ N ₄ (dense condition) is grown to a thickness of 20 nm on the entire surface of the first interlayer silicon oxide film 5 by the CVD method. As a result, nitrogen atoms are diffused into the surface of the first interlayer silicon oxide film 5 during this growth, and the silicon nitride oxide layer 5
a is formed inside the first interlayer silicon oxide film 5 at a depth of at least 50 nm from the upper surface thereof.

Since the silicon nitride oxide layer 5a does not allow hydrogen ions to pass therethrough like the silicon nitride film 6, 2n
It has a function of suppressing transistor characteristic fluctuation due to d-slow trap.

Next, in FIG. 2C, the silicon nitride film 6 is removed by an etching method. For this removal, for example, dry etching using an etching gas of CHF ₃ + O ₂ can be used. Alternatively, the silicon nitride film 6 may be removed by using a wet etching method.

Next, in FIG. 2D, a BPSG film is grown to a thickness of 1200 nm over the entire surface by a CVD method, and is etched so that the surface is flattened to a thickness of about 800 n.
m second interlayer silicon oxide film 7 is formed. Thereafter, the anisotropic dry etching method is performed to penetrate the first interlayer silicon oxide film 5 having the second interlayer silicon oxide film 7 and the silicon nitride oxide layer 5a and reach the high concentration N-type diffusion layer 22. A contact hole 8 having a size of 0.5 μm square is formed.

In FIG. 3A, a silicon oxide film naturally generated on the surface of the high-concentration N-type diffusion layer 22 exposed in the contact hole 8, that is, a natural oxide film 31 is indicated by an X mark.

Next, in FIG. 3B, the natural oxide film 31 is removed by a pre-sputtering process. This pre-sputtering treatment is performed by dipping in a 1: 130 diluted buffered hydrofluoric acid solution for about 15 seconds. At this time, since the silicon nitride film does not exist on the side wall inside the contact 8, as shown in the figure, the eaves of the silicon nitride film are formed inside even if the contact size is reduced even after the pre-sputtering process. Never.

Next, in FIG. 3C, titanium titanium nitride 9 (titanium having a thickness of 50 nm, titanium nitride having a thickness of 100 nm) is formed by sputtering, and tungsten 10 is grown to a thickness of 500 nm by a CVD method. An electrode is formed by performing dry etching so as to leave only the portion buried in 8.

Finally, aluminum is sputtered and patterned by photolithography to form a wiring 11 connected to an electrode in the contact hole.

FIG. 4 is a process sectional view showing a main part of the first embodiment of the present invention in comparison with the prior art, and FIGS.
(C) shows the present invention, and (D) to (F) show the prior art.

In the present invention, the silicon nitride film has already been removed when the contact hole 8 is opened (FIG. 4).
(A)). Therefore, even if the contact hole 8 has a reduced dimension and an aspect ratio of 2 or more, FIG.
After the pre-sputtering process for removing the native oxide film 31 shown in FIG. 4C, as shown in FIG. 4C, the eaves of the silicon nitride film does not exist inside, and the inner side wall surface is formed in the contact hole 8 having a flat surface. Become.

Therefore, even if titanium titanium nitride is sputtered inside as an electrode, the coverage is not reduced due to the eaves of the silicon nitride film.

Therefore, an electrode having good conductivity can be formed, and a high-quality semiconductor of the semiconductor device can be maintained.

On the other hand, in the prior art, the silicon nitride film 6 exists on the inner side surface of the opened contact hole 8 (FIG. 4D). Therefore, in the contact hole 8 whose dimensions are reduced and the aspect ratio becomes 2 or more, FIG.
In wet etching which is a pre-sputtering process for etching and removing the natural oxide film 31 shown in FIG.
First interlayer silicon oxide film 5 on inner wall surface of contact hole 8
a and the second interlayer silicon oxide film 7 are also etched, but the silicon nitride film 6 is not etched. The protruding eaves 32 exist. For this reason, when titanium titanium nitride is sputtered inside as an electrode, the coverage is reduced due to the eaves of the silicon nitride film, and the quality of the conductor device is reduced.

Further, as shown in FIG. 5, it has been confirmed by experiments that the present invention has the same effect as that of the prior art in terms of the effect of suppressing the second slow trap, and that there is no problem in long-term reliability.

The contents of the experiment in FIG. 5 are shown below.

The sample used is a 0.5 μm rule CM.
This is a semiconductor device constituted by an OS. Evaluation content is BT
(Bias test): An acceleration test was performed at 175 ° C. for 500 hours, and the amount of variation of Idd (source-drain current when the transistor was turned on) was measured.

◎ indicates the variation of the present invention, ○ indicates the variation of the prior art when the formed silicon nitride film is used as it is, and ● indicates the variation when the silicon nitride film is not formed from the beginning. It is.

The present invention (◎) (corresponding to FIGS. 4A to 4C) and the prior art (○) (corresponding to FIGS. 4D to 4F)
Is equivalent within the range of sample and measurement variations,
The variation is much smaller than when the silicon nitride film is not formed (marked with ●).

That is, from this experiment, since a silicon nitride film is formed on a silicon oxide film by forming a silicon nitride film on the silicon oxide film, even if the silicon nitride film is subsequently removed, the silicon nitride film is removed. It was found that the effect of suppressing the second slow trap was equivalent to that in the case where it was present.

Next, a second embodiment of the present invention will be described.
This will be described with reference to FIG. In FIG. 6, parts that are the same as or similar to those in FIGS. 1 to 4 are given the same reference numerals.

First, similarly to the first embodiment, a field silicon oxide film 2 and an insulated gate field effect transistor are formed on a silicon substrate 1 by using a known technique.
A first interlayer silicon oxide film 5 and a silicon nitride film 6 are formed to form a silicon nitride oxide layer 5a (FIG. 6A).

Next, using photolithography,
A portion other than the region 8a surrounding the contact opening is covered with the photoresist 41 and patterned, and the contact hole and the silicon nitride film 6 around the contact hole are selectively removed by dry etching (FIG. 6B). As in the first embodiment, a second interlayer oxide film 7, a contact 8, electrodes 9, 10 and a wiring 11 are formed (FIG. 6).
(C)).

It is apparent that the same effects as those of the first embodiment can be obtained in the second embodiment.

[0056]

The effect of the present invention is that even if the contact size is reduced due to the high integration, the conductivity of the electrode metal is not deteriorated without deteriorating the coverability of the electrode metal in a state in which the variation in transistor characteristics due to the second slow trap is suppressed. An electrode having good reliability can be formed, and a highly reliable semiconductor device in which conduction failure hardly occurs even in long-term use can be obtained.

The reason is that the silicon nitride film, which causes the eaves during the pre-sputtering process, is removed before the opening of the contact hole, whereby a contact without eaves can be formed. This is because a silicon nitride oxide layer in which nitrogen is diffused in the silicon oxide film is formed.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating a method of manufacturing the semiconductor device according to the first embodiment of the present invention in the order of steps.

FIG. 3 is a cross-sectional view showing a step subsequent to FIG. 2 in order;

FIG. 4 is a cross-sectional view showing a structure of a contact portion of the present invention in comparison with a conventional technology.

FIG. 5 is a diagram showing the results of an experiment in which the effect of suppressing the second slow trap was evaluated.

FIG. 6 is a sectional view illustrating a method of manufacturing a semiconductor device according to a second embodiment of the present invention in the order of steps.

FIG. 7 is a cross-sectional view showing a conventional semiconductor device.

[Explanation of symbols]

 Reference Signs List 1 P-type silicon substrate 2 Field oxide film 3 Polycrystalline silicon 4 Side wall insulating film 5 First interlayer silicon oxide film 5a Silicon nitride oxide layer 6 Silicon nitride film 7 Second interlayer silicon oxide film 8 Contact hole 8a Surrounding contact opening Region 9 Titanium nitride nitride 10 Tungsten 11 Wiring 12 Gate insulating film 13 Tungsten silicon 21 Low concentration N type diffusion layer 22 High concentration N type diffusion layer 31 Natural oxide film 32 Silicon nitride eaves 41 Photoresist 101 P type silicon substrate 102 field Oxide film 103 Gate insulating film 104 Silicon oxide film 105 Gate polycrystalline silicon 106 Low-concentration N-type diffusion layer 107 Side-wall insulating film 108 High-concentration N-type diffusion layer 111 First contact hole 112 Stack polycrystalline silicon 113 Capacitive insulating film 114 Multi-capacity Crystalline silicon 115 eaves third interlayer silicon oxide film 116 second contact hole 117 bit line 120 first interlayer silicon oxide film 121 a silicon nitride film 122 Second interlayer silicon oxide film 151 a silicon nitride film

Claims (8)

[Claims] 1. An insulated gate field effect transistor having a silicon oxide film in which nitrogen atoms are diffused in the vicinity of a gate electrode and not having a silicon nitride film on a side surface in an opening for leading out an electrode. apparatus. 2. The method according to claim 1, wherein the silicon oxide film has
2. The semiconductor device according to claim 1, comprising a layer diffused by a VD method. 3. The semiconductor device according to claim 1, wherein said opening is a contact hole for extracting an electrode from a source / drain diffusion layer. 4. A step of sequentially forming a first interlayer silicon oxide film after forming the gate electrode, a step of forming a silicon nitride film and diffusing nitrogen atoms into the first interlayer silicon oxide film, A semiconductor device comprising: a step of removing a silicon nitride film; a step of forming a second interlayer silicon oxide film; and a step of forming an opening for leading an electrode in the first interlayer silicon oxide film. Manufacturing method. 5. The method according to claim 4, wherein the silicon nitride film is formed by a CVD method, and nitrogen atoms are diffused into the first interlayer silicon oxide film during the formation. 6. The method according to claim 4, wherein a dry etching method is used as the method for removing the silicon nitride film. 7. The method according to claim 4, wherein a wet etching method is used as a method for removing the silicon nitride film. 8. As a method for removing the silicon nitride film, the opening and the silicon nitride film around the opening are partially etched by using a photolithography method and an etching method, with the electrode extraction opening region being partially centered. 8. The method of manufacturing a semiconductor device according to claim 4, wherein the semiconductor device is selectively removed.