JPH10189948A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device superior in transistor characteristics and a manufacture thereof. SOLUTION: A semiconductor device comprises an isolation oxide 2 deposited on a silicon substrate 1 and a gate oxide 3 deposited on the periphery thereof. When an isolation end 4 is set at a part of an insulation layer having a specified thickness which is thicker than the gate oxide 3 on the boundary of the isolation oxide 2 and the gate oxide 3, an upper electrode 10 is formed on the gate oxide 3, a sidewall oxide 7 is deposited, while covering the isolation end 4 and a second gate electrode 11 is formed on the upper electrode 10, the sidewall oxide 7 and the isolation oxide 2. Since no electrode is present directly above the isolation end 4 to cause degradation of the transistor characteristics, dielectric breakdown is retarded and the reliability is enhanced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and its manufacturing method.

[0002]

2. Description of the Related Art FIGS. 17 to 21 are schematic views showing manufacturing steps for forming an element isolation oxide film, a gate oxide film, and a gate electrode by a conventional method of manufacturing a MOS type semiconductor device. 6A is a cross-sectional view showing the semiconductor device in each manufacturing step in the gate width direction after the element is completed, and FIG. 6B is a cross-sectional view showing the same semiconductor device shown in FIG. 6A in the gate length direction. It is.

Referring to each drawing, as shown in FIG. 17, a pad oxide film 52 having a thickness of 10 nm and a silicon nitride film 53 having a desired shape having a thickness of 150 nm are formed on a silicon substrate 51. To do.

Next, as shown in FIG. 18, thermal oxidation is performed at 1000 ° C. for 3 hours in a pyrooxidizing atmosphere to form an element isolation oxide film 54 having a film thickness of 500 nm.
Next, as shown in FIG. 19, the silicon nitride film 53 and the pad oxide film 52 are removed by wet etching, and thereafter, as shown in FIG. 20, thermal oxidation at 900 ° C. for 20 minutes in a pyrooxidizing atmosphere. Is performed to form a gate oxide film 56 having a thickness of 15 nm.

[0005] Finally, as shown in FIG.
After depositing a polycrystalline silicon film by the D method, anisotropic etching is performed using a resist having a desired shape as an etching mask, so that the gate electrode 57 having a desired shape is formed.
To form

[0006]

However, in the conventional method of manufacturing a semiconductor device as described above, when the element isolation oxide film 54 is formed, it is formed at the boundary with the pad oxide film 52, that is, in the vicinity of the element isolation end 55. A stress is generated, and this stress causes not only a locally thin film portion to be formed at the time of forming the gate oxide film 56, but also strain in the silicon crystal, resulting in a gate oxide film withstand voltage, reliability. However, there is a problem in that the deterioration of characteristics, transistor characteristics, etc. is caused.

SUMMARY OF THE INVENTION In view of the foregoing, it is an object of the present invention to provide a method of manufacturing a semiconductor device capable of eliminating the influence of stress when forming an element isolation oxide film, and a semiconductor device with less deterioration in transistor characteristics and the like.

[0008]

According to the present invention, a gate electrode is not formed near an element isolation end which causes deterioration of transistor characteristics and the like. By eliminating the influence, it is possible to manufacture a semiconductor device having excellent transistor characteristics and the like.

That is, in the semiconductor device according to the first aspect of the present invention, the region is defined by the active region whose region is defined by the gate insulating film and the element isolation insulating film existing around the active region. In a semiconductor device including an element isolation region, when a region having an insulating film having a predetermined film thickness thicker than a gate insulating film at a boundary portion between the element isolation region and the active region is a boundary region, A conductive electrode which is not adjacent to an insulating film having a predetermined film thickness in the boundary region is formed.

According to a second aspect of the present invention, the boundary region is defined as a region having an element isolation insulating film having a thickness about twice as large as the gate insulating film. The semiconductor device according to claim 3, wherein a conductive first electrode is formed on the gate insulating film, and a conductive first electrode which is not adjacent to the insulating film having a predetermined thickness in the boundary region is formed on the first electrode. In this case, two electrodes are formed.

According to another aspect of the semiconductor device of the present invention, a conductive first electrode is formed on the gate insulating film, and a conductive second electrode is formed on the element isolation insulating film. The second electrode is electrically connected to the second electrode by a conductive third electrode that is not adjacent to the insulating film having a predetermined thickness in the boundary region.

According to a fifth aspect of the present invention, the gate insulating film and the element isolation insulating film are formed of a silicon oxide film, and the first electrode, the second electrode, and the third electrode are formed of a polycrystalline silicon film. It is a thing.

According to another aspect of the semiconductor device of the present invention, the first electrode and the second electrode are made of polycrystalline silicon, and the third electrode is made of polycrystalline silicon.
The electrode is made of metal or alloy.
In the method of manufacturing a semiconductor device according to a seventh aspect of the present invention, the region is defined by an active region defined by a gate insulating film and an element isolation insulating film existing around the active region. A semiconductor substrate in which an element isolation region and a boundary region defined by a boundary insulating film having a predetermined thickness larger than a gate insulating film at a boundary portion between the active region and the element isolation region are formed; A first step of forming a first electrode having a shape in which the active region is exposed in at least two places, and a second step of depositing an insulating film on each region including the first electrode; A third step of processing the insulating film to leave the insulating film in at least a part of the boundary region; and forming a conductive layer on each region including the first electrode and the insulating film left in the boundary region. Fourth process for depositing a conductive film If, and the first electrode and the conductive film is obtained and a fifth step of processing into a desired shape.

[0014] The method of manufacturing a semiconductor device according to claim 8 is as follows.
An active region whose area is defined by the gate insulating film;
An element isolation region whose area is defined by an element isolation insulating film present around the active region, and a boundary of a predetermined thickness thicker than the gate insulating film at a boundary between the active region and the element isolation region. A first step of forming a first electrode having a shape in which the active region is exposed at at least two places on a semiconductor substrate in which a boundary region whose region is defined by an insulating film is formed; A second step of implanting impurity ions to thicken the insulating film in at least the boundary region, a third step of depositing a conductive film on each region including the first electrode, and the first electrode And a fourth step of processing the conductive film into a desired shape.

According to a ninth aspect of the present invention, there is provided a method of manufacturing a semiconductor device.
Oxygen ions or nitrogen ions are used as impurity ions for ion implantation. The method of manufacturing a semiconductor device according to claim 10, wherein the active region is defined by a gate insulating film, and the element isolation region is defined by an element isolation insulating film existing around the active region. A semiconductor substrate formed at a boundary between the active region and the element isolation region and having a boundary region defined by a boundary insulating film having a predetermined thickness greater than a gate insulating film; A first step of forming a first electrode having a shape exposed at at least two places over the respective regions, and a second step of forming one or a plurality of second electrodes in the element isolation region; The first
A third step of depositing an insulating film in each region excluding the first electrode and the second electrode, and a fourth step of depositing a conductive film on each region including the first electrode and the second electrode. Process, and processing the first electrode, the second electrode and the conductive film, the first electrode and the second electrode pass over the insulating film in the boundary region interposed between the two electrodes A fifth step of forming a shape connected by the conductive film.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device according to the present invention and a method for manufacturing the same will be described below with reference to the drawings.

FIGS. 1 to 7 are schematic views showing a semiconductor device according to a first embodiment of the present invention and its manufacturing steps. In each of the drawings, FIG. FIG.
FIG. 2B is a cross-sectional view illustrating the semiconductor device illustrated in FIG.

Referring to each drawing, as shown in FIG. 1, a silicon substrate 1 is formed on a silicon substrate 1 in the same manner as in the manufacturing flow of FIGS. , 500 nm-thick device isolation oxide film 2
Then, a gate oxide film 3 having a thickness of 15 nm is formed. Reference numeral 4 is an element isolation end.

Next, as shown in FIG.
After depositing a polycrystalline silicon film of m and performing impurity diffusion, it does not exist on the element isolation end 4 in the gate width direction,
Anisotropic etching is performed using a resist that is present only on the gate oxide film 3 and has a shape that exists on the gate oxide film 3, the element isolation end 4, and the element isolation oxide film 2 in the gate length direction as an etching mask. By doing so, the first gate electrode 5 existing at the same position as the resist is formed.

As shown in FIG. 3, the first gate electrode 5
A silicon oxide film 6 having a film thickness of 400 nm is deposited by a low pressure CVD method on the gate oxide film 3, the element isolation end 4, and the element isolation oxide film 2 on which is formed.

As shown in FIG. 4, the first gate electrode 5
By performing anisotropic etching of the silicon oxide film 6 by about 400 nm until the surface of the first gate electrode 5 is exposed, an oxide film sidewall 7 is formed around the first gate electrode 5.

As shown in FIG. 5, after the silicon oxide film on the first gate electrode 5 is completely removed by an aqueous solution of hydrofluoric acid (hydrofluoric acid: water = 1: 20), polycrystalline silicon having a film thickness of 200 nm is formed. By depositing and diffusing impurities,
A polysilicon film 8 is formed on the first gate electrode 5, oxide film sidewall 7 and element isolation oxide film 2.

As shown in FIG. 6, in the gate width direction,
It exists above the gate oxide film 3, the element isolation end 4, and the element isolation oxide film 2, and does not exist above the element isolation end 4 in the gate length direction, but only above the gate oxide film 3. A resist 9 having a different shape is formed on the polysilicon film 8.

Finally, as shown in FIG.
Is used as an etching mask for the polysilicon film 8 and the first
By performing anisotropic etching of the gate electrode 5 of
The upper electrode 10 and the second gate electrode 11 having the shapes as shown are obtained.

In the semiconductor device formed in this manner, the upper electrode 10 is formed on the second gate electrode 11 formed on the gate oxide film 3 and on the element isolation end 4 in the gate width direction. On the formed oxide film sidewall 7;
It exists above the element isolation oxide film 2, does not exist above the element isolation end 4 in the gate length direction, and exists only above the gate oxide film 3. Further, the second gate electrode 11 does not exist on the element isolation end 4 in both the gate width direction and the gate length direction, but exists only on the gate oxide film 3.

That is, the gate electrode of the present transistor, which is composed of the second gate electrode 11 and the upper electrode 10, is not adjacent to the element isolation end 4 having a poor oxide film quality, and the oxide film sidewall 7 is interposed therebetween. It is connected.
Therefore, during operation, the oxide film electric field at the element isolation end 4 is sufficiently smaller than the electric field applied to the gate oxide film 3, and thus the influence of the oxide film reliability deterioration at the element isolation end 4 can be ignored.

Further, as described above, the polysilicon film 8
Since the etching of the first gate electrode 5 and the etching of the first gate electrode 5 are performed in one step using the resist 9, the resulting upper electrode 10 and second gate electrode 11 do not shift in the gate length direction.

As a result, a MOS transistor having excellent transistor characteristics and the like can be realized. 8 to FIG.
It is the schematic which showed the semiconductor device of 2nd Embodiment of this invention, and its manufacturing process, (a) is each sectional drawing which showed the semiconductor device of each manufacturing process in the gate width direction after element completion. FIG. 2B is a cross-sectional view showing the same semiconductor device shown in FIG.

Referring to each drawing, as shown in FIG. 8, a silicon substrate 21 is formed on a silicon substrate 21 in the same manner as in the manufacturing flow of FIGS. Then, an element isolation oxide film 22 having a thickness of 500 nm and a gate oxide film 23 having a thickness of 15 nm are formed. 24 is an element isolation end.

As shown in FIG. 9, after a polycrystalline silicon film having a thickness of 200 nm is deposited and impurity diffusion is performed, it is present only on the element isolation oxide film 22 in the gate width direction, Includes a gate oxide film 23, an element isolation end 24,
A pair of first element isolation oxide film upper electrodes 25 having a shape existing on the element isolation oxide film 22 are formed. Further, in the gate width direction, it does not exist on the element isolation end 24,
It exists only on the gate oxide film 23, and in the gate length direction,
Gate oxide film 23, element isolation end 24, element isolation oxide film 2
A first gate electrode 2 having a shape as it exists on the first gate electrode 2
6 is formed. As shown in FIG. 10, the gate oxide film 2
A silicon oxide film having a thickness of 180 nm is deposited by selective CVD only on the exposed portions of the third and element isolation oxide films 22 to form a silicon oxide film 27.

As shown in FIG. 11, after completely removing the silicon oxide film on the first gate electrode 26 and the first element isolation oxide film upper electrode 25 with a hydrofluoric acid aqueous solution,
Polycrystalline silicon having a film thickness of 200 nm is deposited to form a polysilicon film 28, and impurities are diffused.

Finally, as shown in FIG. 12, in the gate width direction, there is above the gate oxide film 23, the element isolation end 24, and the element isolation oxide film 22, and in the gate length direction there is the element isolation. Gate oxide film 2 that does not exist above edge 24
3, a polysilicon film 28, a first gate electrode 26, and a first element isolation oxide film electrode 2
5 is processed by anisotropic etching to form a connection electrode 29, a second gate electrode 30, and a second element isolation oxide film upper electrode 31 existing at the same position as the resist.

In the semiconductor device formed in this manner, the connection electrode 29 is formed on the second gate electrode 30 formed on the gate oxide film 23 and on the element isolation end 4 in the gate width direction. It exists on the formed silicon oxide film 27 and the second upper electrode 31 for the element isolation oxide film formed on the element isolation oxide film 22, and has the element isolation end 2 in the gate length direction.
4 does not exist above the gate oxide film 23, but exists only above the gate oxide film 23.

In addition, the second gate electrode 30 does not exist above the element isolation end 24 in both the gate width direction and the gate length direction, but exists only on the gate oxide film 23. The oxide film upper electrode 31 does not exist above the element isolation end 24 in both the gate width direction and the gate length direction, but exists only on the element isolation oxide film 22.

That is, the gate electrode of this transistor constituted by the connection electrode 29, the second gate electrode 30, and the second element isolation oxide film upper electrode 31 has the same oxide film quality as that of the above-described embodiment. Element separation end 24 inferior
Are not adjacent to each other, but are connected via a silicon oxide film 27. Therefore, during operation, the element isolation end 2
4, the electric field of the oxide film is sufficiently smaller than the electric field applied to the gate oxide film 23. Therefore, the influence of the deterioration of the reliability of the oxide film at the element isolation end 24 can be ignored.

Also, as described above, the polysilicon film 2
8, the first gate electrode 26 and the first element isolation oxide film upper electrode 25 are processed in one step, so that the obtained connection electrode 29 and second gate electrode 30 are formed.
Does not occur in the gate length direction.

As a result, a MOS transistor having excellent transistor characteristics and the like can be realized. In the above-described embodiment, the silicon oxide film 27 is formed by the selective CVD method. However, instead of this method, a silicon oxide film is deposited on the entire surface and anisotropically etched to have a sidewall shape. A silicon oxide film is formed in the peripheral portion of the first gate electrode 26 and the first element isolation oxide upper film electrode 25, and is sandwiched between the first gate electrode 26 and the first element isolation oxide upper electrode 25. A silicon oxide film may be formed on the upper part of the element isolation end 24.

13 to 16 are schematic views showing a semiconductor device and its manufacturing process of the third embodiment of the present invention. In each drawing, (a) shows the semiconductor device of each manufacturing process after element completion. 3B is a cross-sectional view of the semiconductor device shown in FIG. 3A in the gate width direction, and FIG. 6B is a cross-sectional view of the semiconductor device shown in FIG.

Explaining with reference to each drawing, as shown in FIG. 13, in the same manner as the manufacturing flow of FIGS. 17 to 20 in the conventional method for manufacturing a semiconductor device described above,
An element isolation oxide film 42 having a thickness of 500 nm and a gate oxide film 43 having a thickness of 15 nm are formed on a silicon substrate 41. 44 is an element isolation end.

As shown in FIG. 14, after a polycrystalline silicon film having a thickness of 200 nm is deposited and subjected to impurity diffusion, the polycrystalline silicon film exists only on the gate oxide film 43 in the gate width direction, and in the gate length direction. Are the gate oxide film 43, the element isolation end 44,
By processing the polycrystalline silicon film by anisotropic etching using the resist 45 having a shape as existing on the element isolation oxide film 42 as a mask, the resist 45 is formed.
A first gate electrode 46 having the same shape as the above is formed.

As shown in FIG. 15, using the resist 45 as an implantation mask, oxygen ions are implanted into a part of the gate oxide film 43 not covered by the resist 45, the element isolation oxide film 42, and the element isolation end 44. By doing so, an improved element isolation end 47 having an increased substantial oxide film thickness (insulating film thickness) is obtained.

Finally, as shown in FIG. 16, the resist 45 is removed, a 200 nm-thick polycrystalline silicon film is deposited, and impurities are diffused. Then, the polycrystalline silicon film and the first gate electrode are removed. 46, a gate oxide film 43, an improved element isolation end 47, an element isolation oxide film 4 in the gate width direction.
2 is formed on the gate electrode 43 by anisotropic etching so as to be present above the gate oxide film 43 but not above the element isolation end 44 in the gate length direction. 48 and a second gate electrode 49 are formed.

In the above-described embodiment, since the improved element isolation end 47 is formed by increasing the thickness of the insulating film in the vicinity of the element isolation end that causes the deterioration of the transistor characteristics and the like, the electrical influence is eliminated. You can

Also in this embodiment, since the connection electrode 48 and the second gate electrode 49 are processed in one step, the connection electrode 48 and the second gate electrode 49 are displaced in the gate length direction. There is no fear.

As a result, a MOS transistor having excellent transistor characteristics and the like can be realized.

[0046]

As described above, according to the present invention, it is possible to eliminate the electrical influence of the inferior gate oxide film region near the element isolation end, which causes deterioration of transistor characteristics and the like.
A semiconductor device having excellent transistor characteristics can be obtained, and its practical effect is great.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view showing a first step of manufacturing a semiconductor device of a first embodiment of the present invention, (a) showing the semiconductor device in a gate width direction after element completion, and (b) showing Shown in the gate length direction.

FIGS. 2A and 2B are schematic cross-sectional views showing a second step of manufacturing the semiconductor device, wherein FIG. 2A shows the semiconductor device in a gate width direction after completion of the element, and FIG.

FIG. 3 is a schematic cross-sectional view showing a third step of manufacturing the same semiconductor device, (a) showing the semiconductor device in the gate width direction after element completion, and (b) showing the gate length direction.

FIG. 4 is a schematic cross-sectional view showing a fourth step of manufacturing the same semiconductor device, (a) showing the semiconductor device in the gate width direction after element completion, and (b) showing the gate length direction.

FIGS. 5A and 5B are schematic cross-sectional views showing a fifth step of manufacturing the semiconductor device. FIG. 5A shows the semiconductor device in a gate width direction after completion of the element, and FIG.

FIG. 6 is a schematic cross-sectional view showing a sixth step of manufacturing the same semiconductor device, (a) showing the semiconductor device in the gate width direction after element completion, and (b) showing the gate length direction.

FIG. 7 is a schematic cross-sectional view showing a seventh step of manufacturing the same semiconductor device, (a) showing the semiconductor device in the gate width direction after element completion, and (b) showing the gate length direction.

8A and 8B are schematic cross-sectional views showing a first step of manufacturing a semiconductor device according to a second embodiment of the present invention, wherein FIG. 8A shows the semiconductor device in the gate width direction after completion of the element, and FIG. Shown in the gate length direction.

FIG. 9 is a schematic cross-sectional view showing a second step of manufacturing the same semiconductor device, (a) showing the semiconductor device in the gate width direction after element completion, and (b) showing the gate length direction.

FIGS. 10A and 10B are schematic cross-sectional views showing a third step of manufacturing the semiconductor device, wherein FIG. 10A shows the semiconductor device in the gate width direction after the completion of the element, and FIG.

FIG. 11 is a schematic cross-sectional view showing a fourth step of manufacturing the same semiconductor device, (a) showing the semiconductor device in the gate width direction after element completion, and (b) showing the gate length direction.

FIGS. 12A and 12B are schematic cross-sectional views showing a fifth step of manufacturing the semiconductor device. FIG. 12A shows the semiconductor device in the gate width direction after the completion of the element, and FIG. 12B shows the gate length direction.

FIGS. 13A and 13B are schematic cross-sectional views showing a first step of manufacturing the semiconductor device according to the third embodiment of the present invention, wherein FIG. 13A shows the semiconductor device in the gate width direction after completion of the element, and FIG.
Is shown in the gate length direction.

14A and 14B are schematic cross-sectional views showing a second step of manufacturing the semiconductor device, wherein FIG. 14A shows the semiconductor device in the gate width direction after the completion of the element, and FIG. 14B shows the semiconductor device in the gate length direction.

FIGS. 15A and 15B are schematic cross-sectional views showing a third step of manufacturing the same semiconductor device. FIG. 15A shows the semiconductor device in the gate width direction after the device is completed, and FIG. 15B shows the gate length direction.

FIG. 16 is a schematic cross-sectional view showing a fourth step of manufacturing the semiconductor device, wherein (a) shows the semiconductor device in the gate width direction after the completion of the element, and (b) shows the semiconductor device in the gate length direction.

FIG. 17 is a schematic cross-sectional view showing a first step of manufacturing a conventional semiconductor device, (a) showing the semiconductor device in the gate width direction after element completion, and (b) showing the gate length direction.

FIGS. 18A and 18B are schematic cross-sectional views showing a second step of manufacturing the same semiconductor device. FIG. 18A shows the semiconductor device in the gate width direction after the device is completed, and FIG.

FIGS. 19A and 19B are schematic cross-sectional views showing a third step of manufacturing the semiconductor device. FIG. 19A shows the semiconductor device in the gate width direction after the completion of the element, and FIG.

FIG. 20 is a schematic cross-sectional view showing a fourth step of manufacturing the same semiconductor device, (a) showing the semiconductor device in the gate width direction after element completion, and (b) showing the gate length direction.

21A and 21B are schematic cross-sectional views showing a fifth step of manufacturing the same semiconductor device, wherein FIG. 21A shows the semiconductor device in the gate width direction after the completion of the element, and FIG. 21B shows it in the gate length direction.

[Description of Signs] 1 Silicon substrate 2 Element isolation oxide film 3 Gate oxide film 4 Element isolation end 7 Oxide film sidewall 10 Upper electrode 11 Second gate electrode 21 Silicon substrate 22 Element isolation oxide film 23 Gate oxide film 24 Element isolation End 27 Silicon oxide film 29 Connection electrode 30 Second gate electrode 31 Second element isolation oxide film upper electrode 41 Silicon substrate 42 Element isolation oxide film 43 Gate oxide film 47 Improved element isolation end 48 Connection electrode 49 Second gate electrode

Claims (10)

[Claims] 1. A semiconductor device comprising an active region whose region is defined by a gate insulating film, and an element isolation region whose region is defined by an element isolation insulating film existing around the active region, When a region having an insulating film having a predetermined thickness thicker than the gate insulating film at a boundary portion between the element isolation region and the active region is a boundary region, it is adjacent to the insulating film having a predetermined thickness in the boundary region. A semiconductor device characterized in that a conductive electrode is formed without a conductive electrode. 2. The semiconductor device according to claim 1, wherein the boundary region is defined as a region having an element isolation insulating film having a thickness about twice as large as the gate insulating film. 3. A conductive first electrode is formed on a gate insulating film, and a conductive second electrode which is not adjacent to the insulating film having a predetermined thickness in a boundary region is formed on the first electrode. The semiconductor device according to claim 1, wherein the semiconductor device is formed. 4. A conductive first electrode is formed on a gate insulating film, a conductive second electrode is formed on an element isolation insulating film, and the first electrode and the second electrode are 3. The semiconductor device according to claim 1, wherein the semiconductor device is electrically connected by a conductive third electrode that is not adjacent to the insulating film having a predetermined film thickness in the boundary region. 5. The semiconductor device according to claim 1, wherein the gate insulating film and the device isolation insulating film are formed of a silicon oxide film, and the first electrode, the second electrode, and the third electrode are formed of a polycrystalline silicon film. Item 5. The semiconductor device according to item 4. 6. The semiconductor device according to claim 4, wherein the first electrode and the second electrode are made of polycrystalline silicon, and the third electrode is made of a metal or an alloy. 7. An active region whose region is defined by a gate insulating film, an element isolation region whose region is defined by an element isolation insulating film present around the active region, and the active region and the element isolation region. In a semiconductor substrate in which a boundary region, which is defined by a boundary insulating film having a predetermined thickness that is thicker than the gate insulating film, is formed at a boundary portion with
A first step of forming a first electrode having a shape in which the active region is exposed in at least two places;
A second step of depositing an insulating film on each region including the electrode, a third step of processing the insulating film and leaving the insulating film in at least a part of the boundary region; Fourth step of depositing a conductive film on each region including the electrode of FIG. 4 and the insulating film left in the boundary region, and a fifth step of processing the first electrode and the conductive film into a desired shape. And a step of manufacturing the semiconductor device. 8. An active region whose region is defined by a gate insulating film, an element isolation region whose region is defined by an element isolation insulating film present around the active region, and the active region and the element isolation region. At a boundary portion between the semiconductor substrate and a boundary region formed by a boundary insulating film having a predetermined thickness larger than the gate insulating film.
A first step of forming a first electrode having a shape in which the active region is exposed in at least two places;
Second step of implanting impurity ions into each region except the electrode to thicken the insulating film in at least the boundary region, and a third step of depositing a conductive film on each region including the first electrode. A method of manufacturing a semiconductor device, comprising: a step; and a fourth step of processing the first electrode and the conductive film into a desired shape. 9. The method according to claim 8, wherein the impurity ions to be implanted are oxygen ions or nitrogen ions. 10. An active region whose area is defined by a gate insulating film, an element isolation region whose area is defined by an element isolation insulating film present around the active region,
The active region is formed on a semiconductor substrate in which a boundary region, which is defined by a boundary insulating film having a predetermined thickness that is thicker than a gate insulating film, is formed at a boundary portion between the active region and the element isolation region. A first step of forming a first electrode having a shape exposed at least at two places over the respective regions, and a second step of forming one or a plurality of second electrodes in the element isolation region, A third step of depositing an insulating film in each region excluding the first electrode and the second electrode; and depositing a conductive film on each region including the first electrode and the second electrode. A fourth step, processing the first electrode, the second electrode, and the conductive film to form an insulating film in a boundary region in which the first electrode and the second electrode are interposed between the electrodes. A fifth step of forming a shape connected by the conductive film passing therethrough; The method of manufacturing a semiconductor device characterized by having.