JPH10189913A - Semiconductor wafer, semiconductor memory device and method for separating the semiconductor memory device from the semiconductor wafer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the sizes of a chip and efficiently replace a function failure line by redundant memory cell array. SOLUTION: A plurality of semiconductor memory parts 2 are arranged in a matrix form on a semiconductor wafer 1. Redundant memory parts 3 and 4 which have redundant memory cells for saving a function failure normal memory cell are arranged between semiconductor memory parts 2 which adjoin in the row and column directions. Cutting lines are provided between the redundant memory parts 3, 4 and semiconductor memory parts 2, for separation from the semiconductor wafer 1 as a semiconductor memory device (chip) at a later step, under the condition that the redundant memory parts 3 and 4 be connected to the memory part 2, as needed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor wafer in which a regular semiconductor memory section and a redundant memory section for relieving a regular memory cell having a malfunction are arranged in a matrix on a semiconductor substrate. The present invention relates to a semiconductor memory device having a necessary number of redundant memory units in a semiconductor memory unit, and a method for separating a semiconductor memory device from a semiconductor wafer.

[0002]

2. Description of the Related Art Generally, a semiconductor memory device such as a dynamic random access memory (DRAM) is provided with a redundant memory cell array and a fuse circuit for controlling redundancy in the vicinity of a regular memory cell array. . In such devices as DRAM,
When a malfunctioning memory cell occurs in the normal memory cell array, the line to which the memory cell is connected (that is, the row line along the word line direction or the column line along the bit line direction) is fused. By using a circuit to replace a corresponding line in a redundant memory cell array, a normal memory cell having the malfunction is remedied.

[0003]

On the other hand, recently, the size of semiconductor memory devices (chips) has been further reduced. However, as the miniaturization progresses, the ratio of the area occupied by the redundant memory cell array and the fuse circuit in the chip becomes relatively large, and this is one of the main factors that hinder the miniaturization of the chip and the high integration thereof. ing.

To cope with this, as an example of a conventionally known technique, for example, Japanese Unexamined Patent Publication No. Hei 6-325589 discloses a technique in which a laser cutting fuse is arranged on a scribe line of a wafer and a redundant memory cell array is provided in a chip. In addition, a technique for arranging a fusing fuse is disclosed. In this technique, data of a fuse for blowing is created by cutting a fuse for laser cutting, and trimming of the fuse for blowing is performed by applying a predetermined voltage from a pad provided on a scribe line. In other words, the chip area is reduced by disposing the laser cutting fuse outside the chip. However, even in this technique, there is a limit in reducing the chip size due to the presence of the redundant memory cell array in the chip.

[0005] Another example of the technology is disclosed in Japanese Unexamined Patent Publication No.
Japanese Patent No. 54695 discloses a technique in which redundant memory cells are arranged so as to be shared by two memory cell array regions. In this technique, a memory cell array region is selected using a switching element, and a defective memory cell in the selected memory cell array region is replaced with a redundant memory cell, thereby improving a defective product remedy rate. . However, this technique does not consider reducing the chip size. That is, also in this technique, since the redundant memory cell is provided in the semiconductor memory device (chip), there is a problem in that the chip size is reduced.

Further, as another example of the technology, Japanese Patent Publication No.
Japanese Patent Publication No. 28012 discloses a semiconductor memory in which redundant memory cell groups are arranged on four sides of a normal memory cell group, and the shape of each memory cell in the normal memory cell group is made uniform. In this technique, the chip size is reduced by making the regular memory cell group uniform in shape. However, also in this technique, since the redundant memory cell group is provided in the semiconductor memory (that is, in the chip), there is a limit in reducing the chip size.

Further, as another example of the technology, Japanese Patent Laid-Open No.
Japanese Patent Laid-Open No. -5098 discloses a semiconductor memory device having a nonvolatile redundant memory cell section for recording inspection information in wafer inspection on a chip. According to this technique, after the assembly is completed, detailed inspection and selection of electrical characteristics are performed based on inspection information of a redundant memory cell portion, so that the inspection and selection can be easily performed without writing data. However, the redundant memory cell section used in this technique is not for relieving a normal memory cell having a malfunction, but for recording inspection information. Also, this technique does not consider reducing the chip size.

A main object of the present invention is to provide a semiconductor wafer and a semiconductor memory device capable of further reducing the chip size and efficiently relieving a malfunctioning memory cell by a redundant memory portion. is there.

Another object of the present invention is to further reduce the chip size and to enable efficient repair of a malfunctioning memory cell by using a redundant memory portion, and consequently a non-defective product (semiconductor) obtained from a semiconductor wafer. It is an object of the present invention to provide a method for separating a semiconductor memory device, which can contribute to a large increase in the number of memory devices.

[0010]

A semiconductor memory device according to the present invention comprises a plurality of semiconductor memory sections arranged in a matrix on a semiconductor substrate and each including a normal memory cell array, and a memory having a malfunction in the normal memory cell array. A plurality of redundant memory units each provided with a redundant memory cell array for relieving the memory cell when a cell is present, wherein the plurality of redundant memory units are sandwiched between two adjacent semiconductor memory units. And a redundant memory unit connected to the two semiconductor memory units and connected between each of the redundant memory units adjacent to each of the semiconductor memory units and the semiconductor memory unit. In each of the semiconductor memory units, a cutting line for separating the semiconductor memory unit from the semiconductor wafer in a state where the redundant memory unit is connected as necessary is set. That.

In one embodiment of the semiconductor memory device of the present invention, the normal memory cell array includes a plurality of blocks each having a first line group in which each line is connected to a normal memory cell. The redundant memory cell array has a second line group in which each line corresponds to each of the plurality of blocks and is connected to a redundant memory cell, and a malfunctioning line is included in the first line group. If present, the corresponding line in the second group of lines to be redundant is activated in place of the malfunctioning line.

In one embodiment of the semiconductor memory device according to the present invention, a first fuse is provided for each line of the first line group in each of a plurality of blocks constituting the normal memory cell array, and the redundancy is provided. A second fuse is provided for each line of the second line group included in the memory cell array, and when a malfunction line exists in the first line group, the second fuse corresponds to the malfunction line. And the second fuse is cut such that the corresponding line in the second line group to be redundantly activated in place of the malfunctioning line is activated. You are disconnected.

[0013] In one embodiment of the semiconductor memory device of the present invention, in a portion where the first and second redundant memory portions are respectively disposed adjacent to opposite sides of one semiconductor memory portion, In the case where one malfunctioning line exists in the first line group in each of a plurality of blocks forming a normal memory cell array of the one semiconductor memory unit, the first and second redundant memories are provided. One corresponding line in the second line group included in any one of the redundant memory cell arrays is activated, and two malfunctioning lines are included in the first line group. If there is, one corresponding line in the second line group included in the redundant memory cell arrays of both the first and second redundant memory units is activated.

In one embodiment of the semiconductor memory device according to the present invention, the first line group is constituted by column lines along a direction of a bit line in the normal memory cell array, and the second line group is constituted by: The redundant memory cell array includes corresponding redundant column lines.

In one embodiment of the semiconductor memory device according to the present invention, the first line group is constituted by row lines along a word line direction in the normal memory cell array, and the second line group is constituted by the second line group. It is composed of corresponding redundant row lines in the redundant memory cell array.

In one embodiment of the semiconductor memory device according to the present invention, the plurality of redundant memory units are disposed adjacent to only one side of one semiconductor memory unit and connected to the one semiconductor memory unit. And a redundant memory unit.

A method of separating a semiconductor memory device according to the present invention is a method of separating a semiconductor memory device from a semiconductor wafer, wherein the semiconductor wafer is arranged in a matrix on a semiconductor substrate and includes a regular memory cell array. A plurality of semiconductor memory units; and a plurality of redundant memory units each including a redundant memory cell array for relieving the memory cells when a malfunctioning memory cell is present in the normal memory cell array. The memory unit includes a redundant memory unit disposed between two adjacent semiconductor memory units and connected to the two semiconductor memory units, and each of the redundant memory units adjacent to the respective semiconductor memory units. A cutting line is set between the memory unit and the semiconductor memory unit, and the cutting line is set for the semiconductor wafer. When separating a plurality of semiconductor memory devices each including one semiconductor memory unit, each redundant memory unit is left connected to one of two semiconductor memory units adjacent to the redundant memory unit. One of the cutting lines set on both sides of the redundant memory unit is selected and cut.

In one embodiment of the method for separating a semiconductor memory device according to the present invention, the normal memory cell array includes:
The redundant memory cell array includes a plurality of blocks each having a first line group in which each line is connected to a normal memory cell, and the redundant memory cell array is configured such that each line corresponds to each of the plurality of blocks and is connected to a redundant memory cell. And a first line group in each of a plurality of blocks constituting the normal memory cell array.
A first fuse is provided for each line of the line group of
A second fuse is provided for each line of the second line group included in the redundant memory cell array, and when separating a plurality of semiconductor memory devices from the semiconductor wafer, the second fuse of the first line group is provided. If a malfunctioning line is present, the first fuse corresponding to the malfunctioning line is blown and the second line group to be redundantly replaced in place of the malfunctioning line. The second fuse is blown so that the corresponding line is activated.

In one embodiment of the method for separating a semiconductor memory device according to the present invention, the semiconductor wafer is inspected to identify defective memory cells present in the plurality of semiconductor memory sections, and the identified result is Then, one of the cutting lines set on both sides of each of the redundant memory units is selected and cut so that the number of rescuable semiconductor memory units among the plurality of semiconductor memory units is maximized.

A method for separating a semiconductor memory device according to the present invention is a method for separating a semiconductor memory device from a semiconductor wafer, wherein the semiconductor wafer is arranged in a matrix on a semiconductor substrate and includes a regular memory cell array. A plurality of semiconductor memory units; and a plurality of redundant memory units each including a redundant memory cell array for relieving the memory cells when a malfunctioning memory cell is present in the normal memory cell array. The memory unit includes a redundant memory unit disposed between two adjacent semiconductor memory units and connected to the two semiconductor memory units, and each of the redundant memory units adjacent to the respective semiconductor memory units. A cutting line is set between the memory unit and the semiconductor memory unit, and the cutting line is set for the semiconductor wafer. When separating a plurality of semiconductor memory devices each including one semiconductor memory unit, if there is a malfunctioning memory cell in a regular memory cell array of each semiconductor memory unit, a redundant memory cell functioning instead of the memory cell The cutting line is appropriately selected and cut so as to leave a redundant memory section having a redundant memory cell array having a state connected to a semiconductor memory section adjacent to the redundant memory section.

In one embodiment of the method for separating a semiconductor memory device according to the present invention, the normal memory cell array comprises:
The redundant memory cell array includes a plurality of blocks each having a first line group in which each line is connected to a normal memory cell, and the redundant memory cell array is configured such that each line corresponds to each of the plurality of blocks and is connected to a redundant memory cell. The first line group in each of a plurality of blocks constituting a normal memory cell array of each semiconductor memory unit when separating a plurality of semiconductor memory devices from the semiconductor wafer. A redundant memory unit having a redundant memory cell array having a corresponding line in the second line group to be replaced in place of the line when a malfunction line exists in the redundant memory unit. The cutting line is appropriately selected and cut so as to remain connected to the semiconductor memory unit adjacent to the above.

In one embodiment of the method for separating a semiconductor memory device according to the present invention, a first fuse is provided for each line of the first line group in each of a plurality of blocks constituting the normal memory cell array. A second fuse is provided for each line of the second line group included in the redundant memory cell array, and when separating a plurality of semiconductor memory devices from the semiconductor wafer, the first line group is provided. In the case where there is a malfunctioning line, the first fuse corresponding to the malfunctioning line is blown, and the second line group to be redundantly replaced in place of the malfunctioning line. The second fuse is cut such that the corresponding line therein is activated.

A semiconductor memory device according to the present invention is a polygonal semiconductor memory section having a normal memory cell array, and a redundant memory for relieving a memory cell having a malfunction in the normal memory cell array. A cell array; and a connection group connected to the redundant memory array on each side of the polygon of the semiconductor memory unit, wherein at least one of the polygons of the semiconductor memory unit is provided.
The redundant memory array adjacent to one of the first sides and connected to the semiconductor memory unit via the connection group; and the other of the semiconductor memory unit other than at least one of the first sides of the polygon. The connection group formed on the second side, which is a side, is provided as a connection group that is not connected to the redundant memory array.

A semiconductor memory device according to the present invention comprises: a semiconductor memory section having a normal memory cell array; a redundant memory cell array for relieving a memory cell having a malfunction in the normal memory cell array; The peripheral region of the semiconductor memory unit includes a connection group connected to the redundant memory array, and is connected to the semiconductor memory unit via the connection group adjacent to at least a part of the peripheral region of the semiconductor memory unit. The connection group formed in the redundant memory array and the other peripheral region of at least a part of the semiconductor memory unit is provided as a connection group not connected to the redundant memory array.

A semiconductor memory device according to the present invention is a polygonal semiconductor memory section having a normal memory cell array, and a redundant memory for relieving a memory cell having a malfunction in the normal memory cell array. A cell array and, on each side of the polygon of the semiconductor memory unit, a connection group connected to the redundant memory array, and the connection group adjacent to at least one side of the polygon of the semiconductor memory unit. The distance between the redundant memory array connected to the semiconductor memory unit via the semiconductor memory unit and the redundant memory array adjacent to the semiconductor memory unit is approximately 80.
It is selected in the range of μm to 120 μm.

A semiconductor memory device according to the present invention comprises: a semiconductor memory unit having a normal memory cell array; a redundant memory cell array for relieving a memory cell having a malfunction in the normal memory cell array; The peripheral region of the semiconductor memory unit includes a connection group connected to the redundant memory array, and is connected to the semiconductor memory unit via the connection group adjacent to at least a part of the peripheral region of the semiconductor memory unit. The interval between the redundant memory array and the redundant memory array adjacent to the semiconductor memory unit is selected in a range of approximately 80 μm to 120 μm.

A semiconductor memory device according to the present invention includes a semiconductor memory unit having a regular memory cell array, and a connection group for connecting to a redundant memory array formed in the peripheral region of the semiconductor memory unit, and at least a part thereof. Are provided as connection groups that are not connected to the redundant memory array.

A semiconductor memory device according to the present invention includes a polygonal semiconductor memory section having a regular memory cell array, and a connection group for connecting to a redundant memory array on each side of the polygon of the semiconductor memory section. And the connection group formed on at least one side of the polygon of the semiconductor memory unit is provided as a connection group that is not connected to a redundant memory array.

In one embodiment of the semiconductor memory device according to the present invention, the normal memory cell array is composed of a plurality of blocks each having a first line group in which each line is connected to a normal memory cell, and The cell array has a second line group in which each line corresponds to each of the plurality of blocks and is connected to a redundant memory cell, and non-functional lines in the first line group are non-functional. The second block corresponding to a block that is activated and includes the malfunctioning line.
Are activated.

In one embodiment of the semiconductor memory device according to the present invention, a first fuse is provided for each line of the first line group in each of the plurality of blocks constituting the normal memory cell array, and the redundancy is provided. A second fuse is provided for each line of the second line group included in the memory cell array, and when a malfunction line exists in the first line group, the second fuse corresponds to the malfunction line. And the second fuse is cut such that the corresponding line in the second line group to be redundantly activated in place of the malfunctioning line is activated. You are disconnected.

In one embodiment of the semiconductor memory device of the present invention, first and second redundant memory sections are connected adjacent to each other on opposite sides of the semiconductor memory section, respectively. In the case where one malfunctioning line is present in the first line group in each of the plurality of blocks constituting the memory cell array, one of the first and second redundant memory units When one corresponding line in the second line group included in the cell array is activated and two malfunctioning lines exist in the first line group, the second line group is activated. One corresponding line in the second line group included in the redundant memory cell arrays of both the first and second redundant memory units is activated.

[0032]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings. FIG. 1 schematically shows a planar configuration of a semiconductor wafer according to an embodiment of the present invention. In the figure, 1 indicates a semiconductor wafer,
On the semiconductor wafer 1, a plurality of rectangular semiconductor memory units 2 each designed to realize a predetermined function are arranged in a matrix. The semiconductor memory unit 2
It includes peripheral circuits such as an input / output interface circuit, a decoder circuit, and an I / O control circuit. Further, a redundant memory unit 3 or 4 is arranged adjacent to each side of each rectangular semiconductor memory unit 2, and each of the redundant memory units 3 and 4 is connected to the adjacent semiconductor memory unit 2. I have.

That is, a redundant memory unit 3 for relieving a memory cell having a malfunction in the column direction in each semiconductor memory unit 2 is provided between two adjacent semiconductor memory units 2 in the vertical direction (that is, the column direction). And the uppermost semiconductor memory unit 2 on the semiconductor wafer 1
Is provided on the upper side. Similarly, each semiconductor memory unit 2
Is provided between two adjacent semiconductor memory units 2 in the left-right direction (that is, the row direction) to relieve a memory cell having a malfunction in the row direction in FIG. , And on the left side of the semiconductor memory unit 2 arranged on the leftmost side on the semiconductor wafer 1.

As shown by broken lines in FIG. 1, between each semiconductor memory unit 2 and each of the redundant memory units 3 and 4,
If necessary, a cutting line for cutting the semiconductor wafer 1 is set at that portion. In the illustrated example, cutting lines X ₁ are provided on both sides of each redundant memory unit 4 in the column direction.
To X ₁₆ are set respectively, cutting lines Y ₁ to Y ₁₁ on either side of each redundant memory section 3 is set respectively in the row direction.

In the present embodiment, in consideration of the current state of the art to which the present invention belongs, the distance d between each rectangular semiconductor memory unit 2 and each of the redundant memory units 3 and 4 adjacent thereto is approximately 80 μm.
It is selected in the range of 120 μm. Also, this interval d
Each cutting line X _{1 to} X ₁₆ and Y ₁ to
The thickness of Y ₁₁ is selected in a range of approximately 30 μm to 50 μm. Preferably, the interval d is set to about 100 μm, and the thickness of each cutting line is set to about 40 μm.

Each semiconductor memory unit 2 is separated from the semiconductor wafer 1 as a "chip" at a later stage.
This separation is performed in a state where the necessary number of redundant memory units 3 and 4 are connected to each semiconductor memory unit 2 or the semiconductor memory unit 2
In the case where there is no malfunctioning memory cell, the cutting is performed by cutting the corresponding cutting line in a state where the connection with the adjacent redundant memory units 3 and 4 is disconnected.

FIG. 2 schematically shows an example of an arrangement form of each line included in each memory cell array of the semiconductor memory section and the redundant memory section. In the figure, reference numeral 11 denotes a normal memory cell array included in the semiconductor memory unit 2, 12a and 12b
1 schematically shows redundant memory cell arrays included in redundant memory units 4a and 4b adjacent to the semiconductor memory unit 2, respectively. As shown in FIG. 2, the normal memory cell array 11 is composed of a plurality of blocks B0 to B7 each having a first line group L0 to L7 in which each line is connected to a normal memory cell (not shown). . On the other hand, each of the redundant memory cell arrays 12a and 12b
Each line has a second line group R0 to R7 corresponding to each of the plurality of blocks B0 to B7 and connected to a redundant memory cell (not shown).

Based on this configuration, the first line groups L0 to L0 included in each of the blocks B0 to B7 of the semiconductor memory unit 2
Of the L7, the functionally normal line is activated, and the second line group R0 in the redundant memory cell arrays 12a and 12b corresponding to the block including the line.
Lines in .about.R7 are deactivated. The defective line is inactivated, and the redundant memory cell array 12a, 12b,
Lines in the second line group R0 to R7 in 12b are activated.

That is, the first line group L0 to L7 of each of the blocks B0 to B7 forming the normal memory cell array 11
7 has a malfunctioning line, the second line groups R0 to R7 in the redundant memory cell arrays 12a and 12b
Is replaced by the corresponding line in.
In the arrangement shown in FIG. 2, the redundant memory units 4a and 4b are arranged on both sides of the semiconductor memory unit 2, respectively.
Even if two lines (for example, L0 and L7) malfunction in the same block (for example, B0) in the semiconductor memory unit 2, one line L0 is connected to the other line by the corresponding line R0 in the left redundant memory unit 4a. Can be repaired by the corresponding line R7 in the redundant memory section 4b on the right side.

Hereinafter, a method for relieving a semiconductor memory portion having a malfunctioning line (memory cell) will be described with reference to FIG. Here, in the row direction using the redundant memory unit, a case where one word line in a specific block in the memory cell array in the semiconductor memory unit is replaced with a corresponding one word line in the redundant memory unit will be exemplified.

As shown, the semiconductor memory units 2a and 2b adjacent to the redundant memory unit 4 have normal decoders D1 and D2 for decoding digital address signals (two bits of Ai and Aj in the example shown). Each of the normal decoders D1, D2 has a word line WL1, WL
2, normal memory cell arrays 11a and 11b are connected. Similarly, the redundant memory unit 4 includes a redundant decoder D3 for decoding a digital address signal (2 bits of Ai and Aj and 2 bits of AXi and AXj whose logic is inverted in the illustrated example). D
3 has a redundant memory cell array 1 via a word line WL3.
2 are connected. As shown, the regular decoder D1
(D2) includes MOS transistors Q10 to Q14 (Q2
0 to Q24), while the redundancy decoder D3 is configured using MOS transistors Q0 to Q6.

The redundant decoder D3 cuts off the connection between the semiconductor memory sections 2a and 2b adjacent on both sides and the line (word line WL3) connected to the redundant memory cell in the redundant memory cell array 12. Fuses H1 and H2 are provided. Further, address signals Ai, Aj and AX are provided to redundant decoder D3.
i, AXj for cutting fuse H2,
H3, H4, and H5 are provided. On the other hand, each of the normal decoders D1 and D2 is provided with fuses H7 and H8 for disconnecting these connections between the corresponding memory cell arrays 11a and 11b, respectively. In this embodiment, laser fuses are used as the fuses H1 to H8. Note that VDD is a power supply voltage,
PR indicates a precharge voltage, and PX indicates a pulse voltage signal.

For example, when repairing the word line WL1 in the semiconductor memory section 2a, the normal decoder D1 is replaced with a redundant decoder D3 as described below. That is, the normal decoder D1 is deactivated by cutting the fuse H7, and the fuses H1, H2 and H3 are turned off.
H6 is turned off to activate the redundant decoder D3. With this operation, the logic of the redundant decoder D3 can be made to match the normal decoder D1. In this case, of the redundant memory section 4 and the cutting line is set between the both sides of the semiconductor memory unit 2a and 2b X _i and X _{i + 1,} the cutting line X _i of the semiconductor memory portion 2a side
Is selected and disconnected.

As described above, the case of relief in the row direction has been described, but the same can be achieved in the column direction.

Next, with reference to FIG. 4, a description will be given of a specific method of relieving a semiconductor memory section in which a malfunctioning memory cell occurs in the row direction and the column direction.
Here, a case where the semiconductor memory unit 2 is divided into four blocks will be exemplified.

As shown in the figure, each block has a memory cell array 21a (21b to 21d) and row decoders 24a (24b to 24d) and column decoders 23a (23b to 23d) as its peripheral circuits. Each 2
Data buffers 22a and 22b are provided so as to be shared by one block. Also, four redundant memory units are arranged adjacent to each side of the semiconductor memory unit 2 composed of these four blocks. The redundant memory section adjacent to the upper side of the semiconductor memory section 2 includes redundant rows 26a, 26b provided for the respective memory cell arrays 21a, 21b.
26b and redundant row decoders 28a and 28b, and the redundant memory section adjacent to the left side is a redundant column 25 provided corresponding to each of the memory cell arrays 21a and 21c.
a, 25c and redundant column decoders 27a, 27c, and redundant memory units adjacent on the right side are redundant columns 25b, 25d and redundant column decoders 27b, 27d provided corresponding to the respective memory cell arrays 21b, 21d.
The redundant memory section adjacent to the lower side includes redundant rows 26c and 26d and redundant row decoders 28c and 28d provided corresponding to the respective memory cell arrays 21c and 21d.
have.

In such a configuration, the memory cell array 2
If a defective column exists in 1a, redundancy is performed by cutting a fuse (not shown) provided in redundant column decoder 27a and replacing it with a part of column decoder 23a. At this time, when the number of defective columns is small, the redundant column decoder 27a and the redundant column 25a are used. When the number of defective columns is large, the redundant column decoder 27c and the redundant column 25c are also used.

Similarly, when a defective column exists in memory cell array 21c, redundant column decoder 27c and redundant column 25c are used, and when the number of defective columns is large, redundant column decoder 27a and redundant column 25a are used.
Also use Similarly, when a defective column exists in the memory cell array 21b, the redundant column decoder 27b and the redundant column 25b are used. When the number of defective columns is large, the redundant column decoder 27d and the redundant column 25d are used.
Also use Similarly, when a defective column exists in the memory cell array 21d, the redundant column decoder 27d and the redundant column 25d are used. When the number of defective columns is large, the redundant column decoder 27b and the redundant column 25b are used.
Also use

As described above, the case of relief in the column direction has been described, but relief can be similarly performed in the row direction.

Next, a method for separating each semiconductor memory device from the semiconductor wafer 1 will be described.

First, a malfunctioning memory cell existing in all the semiconductor memory units 2 is specified by a predetermined inspection.
Then, the specified result, the number and position of the malfunctioning memory cells, and the adjacent redundant memory units 3 and 4
Therefore, one of the cutting lines set on both sides of each of the redundant memory units 3 and 4 is selected and cut so that the number of the rescuable semiconductor memory units 2 is maximized.

The semiconductor memory devices (that is, chips) that can be separated from the semiconductor wafer 1 in this manner can be separated according to the cutting method of each of the cutting lines X _{1 to} X ₁₆ and Y _{1 to} Y ₁₁ (see FIG. 1). As schematically shown in FIGS. 5A to 5P, there are a total of 16 cases.

As described above, in the present embodiment, the redundant memory units 3 and 4 are provided not between the semiconductor memory units 2 but between the semiconductor memory units 2. The redundant memory units 3 and 4 are separated as semiconductor memory devices in a state where they are connected to the unit 2 as necessary. Therefore, the area of the semiconductor memory device (chip) after separation becomes the sum of the area of each semiconductor memory unit 2 and the minimum necessary area of the redundant memory units 3 and 4, and the semiconductor memory device is extremely efficiently manufactured. The area can be reduced.

Each semiconductor memory device is separated from the semiconductor wafer 1 so that the number of the rescuable semiconductor memory units 2 is maximized, so that a good semiconductor memory device (chip) obtained from one semiconductor wafer 1 is obtained. ) Can be greatly increased.

[0055]

According to the semiconductor wafer of the present invention, each of the plurality of rectangular semiconductor memory sections arranged in a matrix is arranged so that each redundant semiconductor memory section is sandwiched between opposing sides of two adjacent semiconductor memory sections. A memory section is provided, each redundant memory section is connected to the two semiconductor memory sections, and a cutting line is provided between each redundant memory section adjacent to each semiconductor memory section and the semiconductor memory section. Are set respectively. That is, the redundant memory section is provided not between the semiconductor memory sections but between the semiconductor memory sections, and is separated from the semiconductor wafer as a semiconductor memory device in a state where the redundant memory sections are connected to each semiconductor memory section as necessary. Will be done. Therefore, the area of the semiconductor memory device (chip) is equal to the area of the semiconductor memory unit plus the minimum required area of the redundant memory unit, and the chip size can be extremely efficiently reduced.

According to the semiconductor memory device of the present invention, the redundant memory section is provided adjacent to at least one of the four sides of the rectangular semiconductor memory section. in this case,
Only when a defective memory cell exists in the normal memory cell array of the semiconductor memory unit, only the redundant memory unit including the redundant memory cell array functioning in place of the memory cell is connected to the semiconductor memory unit. The area of the memory device (chip) is equal to the area of the semiconductor memory unit plus the minimum necessary area of the redundant memory unit. Therefore, the chip size can be extremely efficiently reduced.

Further, according to the method for separating a semiconductor memory device of the present invention, when a defective memory cell is present in a regular memory cell array of a semiconductor memory portion, the semiconductor memory section has a redundant memory cell that functions instead of the memory cell. A cutting line is appropriately selected and cut so as to leave a redundant memory unit including a redundant memory cell array connected to the semiconductor memory unit. Therefore, the semiconductor memory device is separated from the semiconductor wafer as a semiconductor memory device with the redundant memory portion connected to each semiconductor memory portion as necessary. Therefore, the area of each of the separated semiconductor memory devices (chips) is the sum of the area of the semiconductor memory section and the minimum required area of the redundant memory section. can do.

[Brief description of the drawings]

FIG. 1 is a plan view schematically showing a configuration of a semiconductor wafer according to an embodiment of the present invention.

FIG. 2 is a schematic diagram illustrating an example of an arrangement form of each line included in each memory cell array of a semiconductor memory unit and a redundant memory unit.

FIG. 3 is a circuit diagram schematically showing an internal configuration of a redundant memory unit and a semiconductor memory unit for repairing a malfunctioning line;

FIG. 4 is a block diagram illustrating a specific configuration example of a semiconductor memory unit adjacent to a redundant memory unit;

FIG. 5 is a schematic diagram showing various forms of a semiconductor memory device that can be created by the separation method of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Semiconductor wafer 2, 2a, 2b Semiconductor memory part 3, 4, 4a, 4b Redundant memory part 11, 11a, 11b Normal memory cell array 12a, 12b Redundant memory cell array L0-L7 First line group R0-R7 Second Line group B0 to B7 Block D1 to D3 Regular decoder WL1 to WL3 Word line H1 to H8 Fuse 21a to 21d Memory cell array 22a, 22b Data buffer 23a to 23d Column decoder 24a to 24d Row decoder 25a to 25d Redundant column 26a to 26d Redundant row 27a~27d redundant column decoder 28a~28d redundant row decoder _{X 1 ~X 16, Y 1 ~Y} 11 cutting line

Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 27/10 471 H01L 21/82 R

Claims (22)

[Claims] 1. A plurality of semiconductor memory units arranged in a matrix on a semiconductor substrate and each provided with a normal memory cell array, and rescuing the memory cells when a malfunctioning memory cell exists in the normal memory cell array. And a plurality of redundant memory units each including a redundant memory cell array for storing the plurality of redundant memory units, wherein the plurality of redundant memory units are disposed so as to be sandwiched between two adjacent semiconductor memory units, and A redundant memory section connected to each of the semiconductor memory sections, and between each of the redundant memory sections adjacent to the semiconductor memory section and the corresponding one of the semiconductor memory sections, a redundant memory is provided for each of the semiconductor memory sections at a later stage as necessary. A semiconductor wafer, wherein cutting lines for separating the semiconductor wafer from the semiconductor wafer in a state where the parts are connected are respectively set. 2. The normal memory cell array is composed of a plurality of blocks each having a first line group in which each line is connected to a normal memory cell. A second line group corresponding to each of the blocks and connected to the redundant memory cell; and when a malfunction line exists in the first line group, the malfunction line 2. The semiconductor wafer according to claim 1, wherein a corresponding line in the second line group to be redundantly activated is activated instead. 3. A first fuse is provided for each line of the first line group in each of a plurality of blocks constituting the normal memory cell array, and the second line group included in the redundant memory cell array is provided. A second fuse is provided for each line, and when a malfunction line exists in the first line group, the first fuse corresponding to the malfunction line is blown. And the second fuse is blown so that a corresponding line in the second line group to be redundantly replaced with the malfunctioning line is activated. 3. The semiconductor wafer according to 2. 4. In a portion where the first and second redundant memory portions are respectively disposed adjacent to opposite sides of one semiconductor memory portion, the normal memory cell array of the one semiconductor memory portion is When there is one malfunctioning line in the first line group in each of the plurality of constituent blocks, the malfunctioning line is included in one of the first and second redundant memory units in the redundant memory cell array. If one corresponding line in the second line group is activated and two malfunctioning lines exist in the first line group, the first and second lines are activated. 3. The semiconductor wafer according to claim 2, wherein one corresponding line in the second line group included in both redundant memory cell arrays of the two redundant memory units is activated. 5. The first line group is composed of column lines along the direction of a bit line in the normal memory cell array, and the second line group is a corresponding redundant column line in the redundant memory cell array. The semiconductor wafer according to claim 2, wherein the semiconductor wafer is configured. 6. The first line group is constituted by row lines along a word line direction in the normal memory cell array, and the second line group is constituted by corresponding redundant row lines in the redundant memory cell array. 3. The semiconductor wafer according to claim 2, wherein: 7. The redundant memory unit further includes a redundant memory unit disposed adjacent to only one side of one semiconductor memory unit and connected to the one semiconductor memory unit. 7. A method according to claim 1, wherein:
The semiconductor wafer according to item. 8. A method for separating a semiconductor memory device from a semiconductor wafer, wherein the semiconductor wafer is arranged in a matrix on a semiconductor substrate and includes a plurality of semiconductor memory units each including a normal memory cell array; A plurality of redundant memory units each provided with a redundant memory cell array for relieving the memory cell when a malfunctioning memory cell is present in the memory cell array;
A redundant memory unit disposed between the two adjacent semiconductor memory units and connected to the two semiconductor memory units, and each of the redundant memory units adjacent to each of the semiconductor memory units; A cutting line is set between the semiconductor memory unit and each of the redundant memory units when separating a plurality of semiconductor memory devices including one semiconductor memory unit from the semiconductor wafer. So that it remains connected to one of the two semiconductor memory sections adjacent to the section.
A method for separating a semiconductor memory device, comprising selecting and cutting one of the cutting lines set on both sides of the redundant memory unit. 9. The normal memory cell array is composed of a plurality of blocks each having a first line group in which each line is connected to a normal memory cell, and the redundant memory cell array is configured such that each line corresponds to the plurality of blocks. A second line group corresponding to each of the plurality of blocks, the second line group being connected to a redundant memory cell; and a first line group in each of the plurality of blocks constituting the normal memory cell array. A fuse is provided, and a second fuse is provided for each line of the second line group included in the redundant memory cell array. When separating a plurality of semiconductor memory devices from the semiconductor wafer, the second fuse is provided. When a malfunctioning line exists in one line group, the first fuse corresponding to the malfunctioning line is blown. 9. The method according to claim 8, wherein the second fuse is cut so that a corresponding line in the second line group to be redundantly activated in place of the malfunctioning line is activated. The method for separating a semiconductor memory device according to the above. 10. A semiconductor memory capable of inspecting the semiconductor wafer to identify a malfunctioning memory cell existing in the plurality of semiconductor memory units and relieving the plurality of semiconductor memory units based on the identified result. 10. The method according to claim 9, wherein one of the cutting lines set on both sides of each of the redundant memory sections is selected and cut so that the number of sections is maximized. . 11. A method for separating a semiconductor memory device from a semiconductor wafer, wherein the semiconductor wafer is arranged in a matrix on a semiconductor substrate and includes a plurality of semiconductor memory units each including a normal memory cell array; A plurality of redundant memory units each provided with a redundant memory cell array for relieving the memory cell when a malfunctioning memory cell is present in the memory cell array;
A redundant memory unit disposed between the two adjacent semiconductor memory units and connected to the two semiconductor memory units, and each of the redundant memory units adjacent to each of the semiconductor memory units; A cutting line is set between the semiconductor memory unit and a normal memory cell array of each semiconductor memory unit when separating a plurality of semiconductor memory devices each including one semiconductor memory unit from the semiconductor wafer; State in which a redundant memory unit having a redundant memory cell array having a redundant memory cell functioning in place of the memory cell is connected to a semiconductor memory unit adjacent to the redundant memory unit when there is a malfunctioning memory cell A method for separating a semiconductor memory device, wherein the cutting line is appropriately selected and cut so as to be left. 12. The normal memory cell array is composed of a plurality of blocks each having a first line group in which each line is connected to a normal memory cell, and the redundant memory cell array is configured such that each line is a line of the plurality of blocks. A second one corresponding to each and connected to the redundant memory cell
When separating a plurality of semiconductor memory devices from the semiconductor wafer, the first line group in each of a plurality of blocks constituting a normal memory cell array of each semiconductor memory unit When a malfunctioning line is present, a redundant memory unit including a redundant memory cell array having a corresponding line in the second line group to be replaced in place of the line is adjacent to the redundant memory unit 12. The method according to claim 11, wherein the cutting line is appropriately selected and cut so as to remain connected to the semiconductor memory unit. 13. The second line group included in the redundant memory cell array, wherein a first fuse is provided for each line of the first line group in each of a plurality of blocks forming the normal memory cell array. A second fuse is provided for each of the lines, and when a plurality of semiconductor memory devices are separated from the semiconductor wafer, if a malfunctioning line exists in the first line group, Cutting the first fuse corresponding to the malfunctioning line and activating the corresponding line in the second line group to be redundant in place of the malfunctioning line; 13. The method according to claim 12, wherein the second fuse is cut. 14. A polygonal semiconductor memory unit having a normal memory cell array, a redundant memory cell array for relieving a memory cell having a malfunction in the normal memory cell array, and the semiconductor memory. A connection group connected to the redundant memory array on each side of the polygon of the semiconductor memory unit; and a connection group adjacent to at least one first side of the polygon of the semiconductor memory unit via the connection group. The redundant memory array connected to the semiconductor memory unit, and the connection group formed on a second side other than the at least one first side of the polygon of the semiconductor memory unit. Are provided as a connection group not connected to the redundant memory array. 15. A semiconductor memory unit having a normal memory cell array, a redundant memory cell array for relieving a memory cell having a malfunction in the normal memory cell array, and a periphery of the semiconductor memory unit The region includes a connection group connected to the redundant memory array, and the redundant memory connected to the semiconductor memory unit via the connection group adjacent to at least a part of the peripheral region of the semiconductor memory unit A semiconductor memory device comprising: an array; and the connection group formed in at least a part of the other peripheral region of the semiconductor memory unit, as a connection group not connected to the redundant memory array. 16. A polygonal semiconductor memory unit having a normal memory cell array, a redundant memory cell array for relieving a memory cell having a malfunction in the normal memory cell array, and the semiconductor memory. A connection group connected to the redundant memory array on each side of the polygon of the unit; and the semiconductor memory unit adjacent to at least one side of the polygon of the semiconductor memory unit via the connection group. A semiconductor memory device, wherein an interval between the redundant memory array connected to the semiconductor memory unit and the redundant memory array adjacent to the semiconductor memory unit is selected in a range of approximately 80 μm to 120 μm. 17. A semiconductor memory unit having a normal memory cell array, a redundant memory cell array for relieving a memory cell having a malfunction in the normal memory cell array, and a periphery of the semiconductor memory unit The region includes a connection group connected to the redundant memory array, and the redundant memory connected to the semiconductor memory unit via the connection group adjacent to at least a part of the peripheral region of the semiconductor memory unit A semiconductor memory device, wherein an interval between the array and the redundant memory array adjacent to the semiconductor memory unit is selected in a range of approximately 80 μm to 120 μm. 18. A semiconductor memory unit including a regular memory cell array, and a connection group for connecting to a redundant memory array formed in the peripheral region of the semiconductor memory unit, wherein at least a part of the connection group includes: A semiconductor memory device comprising a connection group not connected to a redundant memory array. 19. A polygonal semiconductor memory section having a regular memory cell array, and a connection group for connecting to a redundant memory array on each side of the polygon of the semiconductor memory section; Wherein the connection group formed on at least one side of the polygon of the portion is provided as a connection group not connected to a redundant memory array. 20. The normal memory cell array is composed of a plurality of blocks each having a first line group in which each line is connected to a normal memory cell, and the redundant memory cell array is configured such that each line corresponds to the plurality of blocks. A second line group corresponding to each of them and connected to a redundant memory cell, wherein a malfunctioning line in the first line group is inactivated; 2. A line in the second line group corresponding to a block including the line is activated.
8. The semiconductor memory device according to claim 7. 21. A first fuse is provided for each line of the first line group in each of a plurality of blocks constituting the normal memory cell array, and the second line group included in the redundant memory cell array is provided. A second fuse is provided for each line, and when a malfunction line exists in the first line group, the first fuse corresponding to the malfunction line is blown. And the second fuse is blown so that a corresponding line in the second line group to be redundantly replaced with the malfunctioning line is activated. 21. The semiconductor memory device according to 20. 22. First and second redundant memory sections are connected adjacent to each other on the opposite side of the semiconductor memory section, respectively, in each of a plurality of blocks constituting a normal memory cell array of the semiconductor memory section. If there is one malfunctioning line in the first line group, the first line group
And a corresponding one line in the second line group included in one of the redundant memory cell arrays of the second redundant memory unit is activated, and a function is included in the first line group. When there are two defective lines, one corresponding line in the second line group included in the redundant memory cell arrays of both the first and second redundant memory units is activated. 21. The semiconductor memory device according to claim 20, wherein