JPH10178161A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To speed up the operation of a semiconductor memory. SOLUTION: When the data stored in a capacitor 61 is read out to a bit-line BL, pre-charge signals EQ1/and EQ2/are supplied to gates of NMOSs 91, 92, and 93. When the signals EQ1/ and EQ2/exceed a threshold value, the NMOSs 91-93 are turned on, so that the bit-line BL is pre-charged to a pre-charge voltage. When a control signal exceeds a threshold value, an NMOS 71b is turned on, and an NMOS 62 turns on following it, and data in the capacitor 61 is read into the bit-line BL. The voltage of the bit-line BL is amplified with a sense amplifier 30. Here, since the threshold value of a pre-charge transistor is set lower than that of the other transistors, pre-charge operation is performed at high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory such as a dynamic random access memory (hereinafter, referred to as a DRAM) constituted by using transistors.

[0002]

2. Description of the Related Art A memory cell of a DRAM includes a plurality of capacitors arranged at intersections of a plurality of word lines and a plurality of bit lines for storing data, and a plurality of capacitors for turning on and off each of the capacitors and the bit lines. And a memory cell transistor. Each memory cell transistor is, for example, an N-channel MOS transistor (hereinafter referred to as NMOS).
And the gate of the memory cell transistor is connected to one word line. When the voltage of the word line applied to the gate exceeds the threshold, the memory cell transistor is turned on, and data stored in the capacitor is read out to the bit line.

[0003] A DRAM is composed of one bit line consisting of two bit lines.
There is a bit line folding type using one bit line pair as an access unit. A bit line pair of the DRAM includes a sense amplifier constituted by an NMOS or a P-channel type MOS transistor (hereinafter referred to as a PMOS) for detecting and amplifying the voltage of each bit line, and a bit line constituted by an NMOS, for example. An equalizer or the like for setting the paired voltages to the precharge voltage is connected. The word line is connected to a word line driving transistor that drives the word line with a voltage. The DRAM is further provided with a logic circuit such as a decoder, an I / O circuit for inputting and outputting memory cell access data, a power supply circuit for supplying a power supply voltage to each unit, and the like. Peripheral circuits such as a logic circuit, an I / O circuit, and a power supply circuit are also constituted by MOS transistors, and are formed on the same semiconductor substrate together with a memory cell, a sense amplifier, an equalizer, and a word line driving transistor. . A DRAM has a simple structure of a memory cell, so that a large-capacity semiconductor memory can be formed. In recent years, bit line folding type DRAMs in which a DRAM is highly integrated and a bit line pair is used as an access unit have become mainstream.

[0004]

However, the conventional DRAM has the following problems. FIG. 2 is a circuit diagram showing a configuration example of a conventional DRAM. This DRA
M is a bit line folded type DRAM, which includes a memory cell 10. The memory cell 10 includes a capacitor 11 provided at the intersection of a word line WL and a bit line pair BL or BL /, and a memory cell transistor that turns on and off the capacitor 11 and the bit line BL or BL /. And an NMOS 12. NMO
The gate of S12 is connected to the word line WL. The NMOS 12 is turned on when the voltage of the word line WL connected to the gate exceeds a threshold value, and connects the capacitor 11 to the bit line BL. Thereby, the capacitor 1
The data stored in 1 is read out on the bit line BL.

The word lines WL are connected to NMOS transistors 21a and 21b of word line driving transistors. N
The gate of the MOS 21a is connected to the NAND circuit 22 of the decoder.
Output terminal. The NMOS 21a has an NA
When the signal supplied from the ND circuit 22 exceeds a threshold, the word line WL is connected to the ground.
The gate of the NMOS 21b is connected to the output terminal of the NAND 22 via the inverter 23. NMOS 21
“b” connects the word line WL to the power supply voltage Vcc when the signal supplied from the inverter 23 exceeds the threshold value. The sense amplifier 30 is connected to the bit line pair BL, BL /. The sense amplifier 30 is an NMO
It is composed of a differential amplifier using S and PMOS, etc.
For example, it has a function of amplifying the data read to the bit line BL by amplifying the potential difference between the bit line pair BL and BL /. Equalizers 40A and 40B are further connected to bit line pair BL and bit line BL /. The equalizer 40A is composed of two NMOSs 41 and 42 to which an equalize signal EQ1 is commonly applied to each gate. The drain of NMOS 41 is bit line B
L and the source of the NMOS 41 is connected to the NMOS 42
Drain is connected. The source of the NMOS 42 is connected to the bit line BL /. Equalizer 40B
Is an NMO having an equalizing signal EQ2 applied to its gate.
This is composed of S43. The drain of the NMOS 43 is connected to the bit line BL, and the source of the NMOS 43 is connected to the bit line BL /.

The DRAM of FIG. 2 further includes an HVcc generation circuit 50. HVcc generation circuit 50
Is a circuit for generating a voltage HVcc which is half the voltage value of the power supply voltage Vcc. The output side of the HVcc generation circuit 50 is connected to, for example, NMOSs 51 and 52. N
The MOS 51 outputs the equalize signal EQ input to the gate.
When 1 / exceeds the threshold value, the voltage HVcc is
Is connected to a connection point between the source of the NMOS 42 and the drain of the NMOS 42. When the equalizing signal EQ1 / inputted to the gate exceeds the threshold, the NMOS 52 outputs the voltage H
Vcc is applied to one electrode of the capacitor 11.

In such a DRAM, when the memory is in the standby state, the bit lines BL and BL / are set to the voltage HV.
Precharge to cc. That is, the equalizing signal EQ1
/ Rises the NMOSs 41 and 42, and raises the equalization signal EQ2 /
S43 is turned on. As a result, the voltage HVcc
Is applied to bit lines BL and BL / to be equalized. Immediately before accessing the memory cell 10, the equalizing signals EQ1 / and EQ2 / fall,
The NMOSs 41, 42, and 43 are turned off. If the voltage of the word line WL or the bit lines BL and BL / rises before the precharge is completed, it naturally causes a malfunction. Therefore, considering the high-speed operation of the DRAM, the time required for the precharge (equalization) is considered. Shorter is better. However, the NMOS 4 that controls the speed of this equalizing operation
The thresholds of 1, 42, and 43 cannot be set independently for simplification of the process. On the other hand, in the peripheral circuits and the memory cell transistors other than the equalizers 40A and 40B, in order to ensure the operation reliability of the single transistor, the leakage current between the source and the drain is 1E when the gate voltage is 0V.
Some transistors need to be set to about −12 A or less. Therefore, the NMOSs 41, 42, 4
In most cases, the threshold value of 3 is set to a threshold value similar to that of a transistor or a memory cell transistor of the peripheral circuit. In particular, the memory cell transistor is also NMO
In the current DRAM composed of S, the value may be set to a value close to 1 V, which has been a major obstacle in increasing the speed of the memory operation.

Further, for the transistors in the sense amplifier 30, for the same reason as in the case of the NMOSs 41, 42, and 43, the memory operation can be speeded up by setting the threshold value low. The threshold value is set to be substantially the same as that of the middle transistor and the memory cell transistor, which is an obstacle to speeding up the memory operation. The NMOSs 21a and 21b of the word line driving transistors are also NM
For the same reason as in the case of the OSs 41, 42, and 43, the memory operation can be speeded up by setting the threshold value low. However, in an actual DRAM, the threshold value is set to be approximately the same as that of transistors in peripheral circuits and memory cell transistors. It has been set and is an obstacle to speeding up the memory operation.

[0009]

According to a first aspect of the present invention, there is provided a semiconductor memory formed on a common substrate, wherein a word line and a word line intersect with the word line via an insulating layer. And a memory element, a word line driving transistor, a memory cell transistor, a sense amplifier, a precharge transistor, and a peripheral circuit as described below. The storage element is arranged at the intersection with the bit line, and stores data. The word line driving transistor has a control electrode and two conductive electrodes that are turned on or off in accordance with the level of the voltage of the control electrode with respect to the threshold value. Is supplied with a predetermined voltage and the other conductive electrode is connected to a word line, and is turned on based on a control signal to drive the word line with a voltage. The memory cell transistor has a control electrode and two conductive electrodes that are turned on or off according to the level of the voltage of the control electrode with respect to a threshold, and the control electrode is connected to a word line;
The conductive electrodes are connected to the bit line and the storage element, respectively, and are turned on when the voltage of the word exceeds the threshold value to read the data of the storage element to the bit line.

The sense amplifier has a sense amplifier transistor having a control electrode connected to the bit line and two conductive electrodes that turn on or off according to the level of the voltage of the control electrode with respect to a threshold. Is detected with the threshold value of the sense amplifier transistor, and the data level is amplified. The precharging transistor has a control electrode to which a precharge signal is applied, and two conductive electrodes that are turned on or off in accordance with the level of the voltage of the control electrode with respect to a threshold value. A voltage for use is supplied and the other conductive electrode is connected to the word line, and is turned on based on the precharge signal to precharge the bit line.
The peripheral circuit has a peripheral transistor having a control electrode and two conductive electrodes that are turned on or off in accordance with the level of the voltage of the control electrode with respect to a threshold value.
It generates a precharge signal, a precharge voltage, and a power supply for a sense amplifier, and inputs and outputs data on bit lines. The threshold value of the precharge transistor is set lower than the threshold values of the memory cell transistor and the peripheral transistor.

The fifth to eighth inventions relate to a semiconductor memory having a word line, a bit line, a storage element, a word line driving transistor, a memory cell transistor, a sense amplifier, a precharge transistor and a peripheral circuit. The threshold value of the transistor is set lower than the threshold values of the memory cell transistor and the peripheral transistor. The ninth to twelfth inventions are directed to a semiconductor memory having a word line, a bit line, a storage element, a word line driving transistor, a memory cell transistor, a sense amplifier, a precharge transistor, and a peripheral circuit. , The threshold value of the word line driving transistor is set lower than the threshold values of the memory cell transistor and the peripheral transistor.

When a semiconductor memory reads data from a bit line, a precharge signal is applied to a control electrode of a precharge transistor. When the precharge signal exceeds the threshold, the precharge transistor is turned on, and the bit line is charged (precharged) to the precharge voltage. When the control signal exceeds the threshold value, the word line driving transistor is turned on, and the data in the storage element is read out to the bit line. The bit line voltage is a voltage obtained by superimposing the data level on the precharge voltage. The sense amplifier detects and amplifies the bit line voltage with a threshold value, and sets the bit line voltage to a voltage corresponding to the data. Here, according to the first to fourth aspects of the present invention, since the threshold value of the precharge transistor is set low, the precharge operation is performed quickly. According to the fifth to eighth aspects, the threshold value of the sense amplifier transistor is set to be low, so that the sensing operation is speeded up. According to the ninth to twelfth aspects, the threshold value of the word line driving transistor is set low, so that the rise of the word line is accelerated. Therefore, the above problem can be solved.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIG. 1 is a circuit diagram of a DRAM showing a first embodiment of the present invention. This DRAM is a bit line folded type DR.
This is an AM in which the threshold of an equalizing transistor, which is a pre-charging transistor for charging a bit line, is lower than the thresholds of other transistors, thereby enabling high-speed memory operation. Word line WL and bit line B
L and BL / are insulated through an insulating layer (not shown), and the word lines WL and the bit lines BL are arranged so as to intersect. The memory cell 60 of the DRAM of FIG.
61 which is a storage circuit provided at a crossing point between the gate and the bit line pair BL or BL /, and the capacitor 61
, Which is a memory cell transistor that turns on and off between one electrode of the bit line and the bit line BL or BL /
And 2. A gate, which is a control electrode of the NMOS 62, is connected to the word line WL. This NMOS 62
Is set to Vt1.

The word lines WL are connected to NMOS transistors 71a and 71b, which are word line driving transistors. The threshold value of each of the NMOSs 71a and 71b is also set to Vt1. The gate of the NMOS 71a is connected to the output terminal of the NAND circuit 72 of the decoder constituting the peripheral circuit. The NMOS 71a connects the word line WL to the ground GND when the control signal given from the NAND circuit 72 exceeds the threshold value Vt1. NMO
The gate of S71b is connected to the output terminal of the NAND 72 via the inverter 73. NMOS 71b
When the control signal supplied from the inverter 73 exceeds the threshold value Vt1, the word line WL is connected to the power supply voltage Vcc. A sense amplifier 80 is connected to the bit line pair BL and the bit line BL /. The sense amplifier 80 includes NMOSs 81 and 82 of a sense amplifier transistor whose gates are connected to the bit lines BL and BL / and PM
It is composed of a differential amplifier using OSs 83 and 84. The sense amplifier 80 has a function of amplifying the data read to the bit line BL by amplifying the potential difference between the pair of bit lines BL and BL /. The thresholds of the NMOSs 81 and 82 and the PMOSs 83 and 84 in the sense amplifier 80 are also set to Vt1.

The equalizers 90A and 90B are further connected to the bit line pair BL and the bit line BL /. The equalizer 90A includes two precharge transistors NMOS 91 and 92 to which an equalize signal EQ1 /, which is a precharge signal, is commonly supplied to each gate. The drain of one conductive electrode of the NMOS 91 is connected to the bit line BL, and the drain of the NMOS 92 is connected to the source of the other conductive electrode of the NMOS 91. The source of the NMOS 92 is connected to the bit line BL /. The equalizer 90B includes an equalizing NMOS 93 whose gate receives an equalizing signal EQ2 /. The drain of the NMOS 93 is connected to the bit line BL.
And the source of the NMOS 93 is connected to the bit line BL /
It is connected to the. The thresholds of these NMOSs 91, 92 and 93 are set to Vt2 lower than the threshold Vt1. The DRAM further includes a peripheral circuit HVc.
A c generation circuit 100, a control circuit (not shown) for generating a precharge signal, an I / O circuit (not shown) for inputting and outputting access data, and the like are provided. HVcc generation circuit 1
00 is a voltage HVcc which is half the voltage value of the power supply voltage Vcc.
The output side of the HVcc generation circuit 100 is connected to, for example, an NMOS 101 and an NMOS 102. The threshold value of each NMOS 101, 102 is
Vt1. When the equalizer signal EQ1 / inputted to the gate exceeds the threshold value Vt1, the NMOS 101 applies the voltage HVcc to the source of the NMOS 91 and NMO.
This connection is applied to the drain connection point of S92.
The NMOS 102 is connected to apply the voltage HVcc to the other electrode of the capacitor 61 when the equalizer signal EQ1 / input to the gate exceeds the threshold Vt1.

The threshold value Vt2 of the NMOS transistors 91, 92 and 93 and the threshold value Vt1 of the other transistors are, for example, NMOS
Alternatively, the differentiation can be made by changing the channel ion concentration of the PMOS or by increasing the thickness of the gate oxide film which is the insulating film. When changing the channel ion concentration, ion implantation is performed in a plurality of times. That is, normal photolithography and ion implantation are each increased one or more times in the ion implantation step of the wafer process, and a part of the ion implantation is performed by the NMOSs 91 and 9.
NMOS 9 is performed by masking the channels of 2,93.
The channel ion concentrations of 1, 92 and 93 can be made thinner than other transistors. Even when the thickness of the gate oxide film is increased, the gate oxide film forming process is divided into a plurality of steps, and the other transistors are masked to form the NMOSs 91, 92, and 93.
If the gate oxide film is formed, the NMOS 9
1, 92, 93 gate oxide films can be thickened.

FIG. 3 is a time chart showing the operation of FIG. 1. The operation of the DRAM of FIG. 1 will be described with reference to FIG. First, when the memory is in the standby state, the voltage of the equalize signal EQ1 / is raised,
The NMOSs 91, 92, 101, and 102 are turned on, the equalizing signal EQ2 / is raised, and the NMOS 93 is turned on. Thereby, the bit lines BL and BL / are set to the voltage HVcc.
Is precharged and equalized. When the equalizing signals EQ1 / and EQ2 / are raised, the NMOS 9
1, 92, 101, 102 and the NMOS 93 are turned off. In this state, a control signal is supplied, the NMOS 71a is turned off, the NMOS 71b is turned on, and the word line WL
driven to cc. When the word line WL is driven by voltage, N
The MOS 62 is turned on, and the capacitor 61 is connected to the bit line BL.
Is read out. The sense amplifier 80 detects this at the threshold value t1, and amplifies the voltage of the bit line BL. As a result of the amplification, the voltage of the bit line BL is set to a level corresponding to the data as shown in FIG. Hereafter, the voltage of this bit line BL is increased. The signal is output to the outside or written again to the capacitor 61. As described above, in the first embodiment, since the thresholds of the NMOSs 91, 92, and 93 are lower than the thresholds of the other transistors, the precharge time performed based on the equalizing signals EQ1 / and EQ2 /. Can be shortened. This is apparent from the fact that the response to the equalizing signal EQ1 / in FIG. 3 is short, and the memory operation can be speeded up. Also,
Since the threshold value is changed depending on the ion concentration and the gate oxide film thickness, the shapes of the transistors can be integrated, and the degree of freedom in layout can be secured.

Second Embodiment FIG. 4 is a circuit diagram of a DRAM showing a second embodiment of the present invention. In this DRAM, the threshold value of the sense amplifier transistor in the sense amplifier is lower than the threshold values of the other transistors, and the point that the sense amplifier 80 is changed to the sense amplifier 110 and the equalizers 90A, 90
The connection is the same as that of FIG. 1 except that B is changed to equalizers 120A and 120B. The sense amplifier 110 is connected to the bit lines BL and BL /, and the gates of the sense amplifier transistors NMOS 111 and 112 and the PMOS 11 are connected to the bit lines BL and BL /.
It comprises a differential amplifier using 3,114.
The sense amplifier 110 has a function of amplifying the data read to the bit line BL by amplifying the potential difference between the pair of bit lines BL and BL /. The NMOSs 111 and 112 and the PMOS 113,
Each of the thresholds 114 is set to Vt2 lower than the threshold Vt1.

The equalizers 120A and 120B are connected to a bit line pair BL and a bit line BL /. The equalizer 120A is composed of two equalizing transistors NMOS 121 and 122 to which an equalizing signal EQ1 /, which is a precharge signal, is commonly supplied to each gate. The drain of the NMOS 121 is connected to the bit line BL, and the source of the NMOS 121 is connected to the drain of the NMOS 122. The source of the NMOS 122 is connected to the bit line BL /. Equalizer 120B
Is composed of an equalizing NMOS 123 whose gate receives an equalizing signal EQ2 /. NMOS 12
3 is connected to the bit line BL and the NMOS 1
23 sources are connected to the bit line BL /. The threshold values of the NMOSs 121 to 123 are set to the threshold value Vt1. NMOS or P in the sense amplifier 110
The threshold value Vt2 of the MOS and the threshold value Vt1 of the other transistors can be differentiated by changing the channel ion concentration or by increasing the thickness of the gate oxide film which is the insulating film. More specifically, as in the first embodiment, this is realized by performing the ion implantation step or the gate oxide film forming step a plurality of times. The DRAM of FIG. 4 basically performs the same operation as that of the first embodiment. As described above, in the second embodiment, the threshold Vt2 of the sense amplifier 110 is set lower than the thresholds Vt1 of the other transistors, so that the sensing time can be reduced. This is apparent from the short response time of the bit line BL in FIG. The speed of the memory operation can be increased.

Third Embodiment FIG. 5 is a circuit diagram of a DRAM showing a third embodiment of the present invention. In this DRAM, the threshold value of the word line driving transistor is lower than the threshold values of the other transistors.
71A and 71B are changed to NMOS 131a and 131b, and equalizers 90A and 90B are equalizer 1
FIG. 1 except for the difference in that it has been changed to 20A and 120B.
It has the same connection as. The gate of the NMOS 131a is connected to the output terminal of the NAND circuit 72. N
The gate of the MOS 131b is connected to the output terminal of the NAND 72 via the inverter 73. These NMOs
The threshold values of S131a and 131b are set to Vt2 lower than the threshold value Vt1. The NMOS 131a is a NAN
When the control signal given from the D circuit 72 exceeds the threshold value Vt2, the word line WL is connected to the ground,
S131b connects the word line WL to the power supply voltage Vcc when the control signal supplied from the inverter 73 exceeds the threshold value Vt2. Equalizer 120A,
120B is the same as in the second embodiment. NMOS1
The threshold values Vt2 of the transistors 31a and 131b and the threshold value Vt1 of the other transistors can be differentiated by changing the channel ion concentration or by increasing the thickness of the gate oxide film as the insulating film. More specifically, as in the first embodiment, this is realized by performing the ion implantation step or the gate oxide film forming step a plurality of times.

The DRAM of FIG. 5 basically performs the same operation as that of the first embodiment. As described above, in the third embodiment, the threshold value Vt2 of the NMOSs 131a and 131b is set lower than the threshold value Vt1 of the other transistors, so that the time required to drive the word lines can be reduced. This is apparent from the fact that the rise of the word line WL in the word line BL in FIG. 3 is short, and the memory operation can be speeded up. Note that the present invention is not limited to the above embodiment, and various modifications are possible. For example, there are the following modifications.

(1) In the first to third embodiments, one memory cell 60 is described for simplicity. However, a plurality of memory cells 10 include a plurality of word lines WL and a plurality of bit lines. It is needless to say that the present invention can also be applied to a case where they are arranged on a matrix at the intersections of. (2) In the first to third embodiments, the example of the DRAM of the bit line folded type is described. However, even if the present invention is applied to a DRAM other than the bit line folded type, the first to third embodiments are not limited. The same effect as the form can be expected. (3) The configuration of the sense amplifier shown in FIGS. 1, 4 and 5 may be another configuration. (4) In the first to third embodiments, the threshold value is differentiated by changing the ion concentration or the gate oxide film thickness.
This may be performed by changing the two-dimensional shape of the transistor, such as changing the length or width of the gate. In this case, the number of steps can be simplified. Further, the threshold value may be differentiated by another suitable method.

[0023]

As described in detail above, the first to fourth embodiments
According to the invention, since the threshold value of the precharge transistor is set lower than the threshold values of the memory cell transistor and the peripheral transistor, the precharge time for the bit line can be reduced, and the semiconductor memory can operate at high speed. According to the fifth to eighth aspects, since the threshold value of the sense amplifier transistor is set lower than the threshold values of the memory cell transistor and the peripheral transistor, the sensing time can be reduced, and the semiconductor memory can operate at high speed. According to the ninth to twelfth aspects, the threshold value of the word line driving transistor is set lower than the threshold values of the memory cell transistor and the peripheral transistor, so that the time required to start up the word line can be reduced, and the speed of the semiconductor memory can be increased. Becomes possible.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a DRAM according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration example of a conventional DRAM.

FIG. 3 is a time chart showing the operation of FIG.

FIG. 4 is a circuit diagram of a DRAM showing a second embodiment of the present invention.

FIG. 5 is a circuit diagram of a DRAM showing a third embodiment of the present invention.

[Explanation of symbols]

Reference Signs List 60 memory cell 61 capacitor (storage element) 62 memory cell transistor 71a, 71b, 131a, 131b word line driving transistor 80, 110 sense amplifier 81 to 84, 111 to 114 sense amplifier transistor 90A, 90B, 120A, 120B equalizer 91, 92, 121, 122 Precharge transistors BL, BL / bit line WL word line

Claims (14)

[Claims] 1. A word line, a bit line crossing the word line via an insulating layer, and a bit line intersecting the word line and the bit line,
A storage element for storing data; and a control electrode and two conductive electrodes that are turned on or off in accordance with the level of the voltage of the control electrode with respect to a threshold value. A predetermined voltage is applied to one of the electrodes, and the other conductive electrode is connected to the word line; a word line driving transistor for turning on the word line based on the control signal and driving the word line; And two conductive electrodes that are turned on or off in accordance with the voltage level of the control electrode with respect to the control electrode. The control electrode is connected to a word line, and the conductive electrodes are connected to the bit line and the storage element. A memory cell transistor connected to each other, turned on when the voltage of the word exceeds a threshold value, and reading data of the storage element to the bit line; a control electrode connected to the bit line; A sense amplifier transistor having two conductive electrodes that are turned on or off according to the level of the voltage of the control electrode with respect to the control electrode, and the level of data on the bit line is detected by a threshold value of the sense amplifier transistor. A sense amplifier that amplifies the level of the control electrode; and a control electrode to which a precharge signal is applied, and two conductive electrodes that are turned on or off according to the level of the voltage of the control electrode with respect to a threshold value. A pre-charge voltage is supplied to the bit line, the other conductive electrode is connected to the bit line, and a pre-charge transistor that turns on and pre-charges the bit line based on the pre-charge signal; A peripheral transistor having two conductive electrodes that are turned on or off according to the level of the voltage of the electrode; And a peripheral circuit for generating the voltage, the precharge signal, the precharge voltage, and the power supply of the sense amplifier, and performing input / output of data of the bit line, wherein these are formed on a common semiconductor substrate. In the memory, the threshold value of the precharge transistor is set lower than the threshold values of the memory cell transistor and the peripheral transistor. 2. The threshold value of the precharge transistor is determined by making the ion concentration of a channel region of the precharge transistor different from the ion concentration of a channel region of the memory cell transistor and the peripheral transistor. 2. The semiconductor memory according to claim 1, wherein the threshold value is set lower than the threshold values of the memory cell transistor and the peripheral transistor. 3. The threshold value of the precharging transistor is such that an insulating film thickness between each of the conductive electrodes and the control electrode in the precharging transistor is equal to a thickness of the conductive electrode in the memory cell transistor and the peripheral transistor. 2. The semiconductor memory according to claim 1, wherein the semiconductor memory is manufactured so as to have a thickness different from an insulating film thickness between the control electrode and the control electrode, and is set lower than threshold values of the memory cell transistor and the peripheral transistor. 4. The threshold value of the precharge transistor is manufactured by making the two-dimensional shape of the control electrode in the precharge transistor different from the two-dimensional shape of the control electrode in the memory cell transistor and the peripheral transistor. 2. The semiconductor memory according to claim 1, wherein the threshold value is set lower than the threshold values of the memory cell transistor and the peripheral transistor. 5. The word line, the bit line, the storage element, the word line driving transistor, the memory cell transistor, and the peripheral circuit according to claim 1, a control electrode connected to the bit line, and a control electrode connected to the bit line. A sense amplifier transistor having two conductive electrodes that are turned on or off in accordance with the level of the voltage; a data level on the bit line is detected by a threshold value of the sense amplifier transistor to amplify the data level A sense electrode; a control electrode to which the precharge signal is applied; and two conductive electrodes that are turned on or off in accordance with the voltage level of the control electrode with respect to a threshold, and one of the conductive electrodes has the pre-charge signal. A charging voltage is applied and the other conductive electrode is connected to the bit line, and is turned on based on the precharge signal to precharge the bit line. And a plurality of bit line precharge transistor for Yaji, said sense amplifier threshold of the transistor, the semiconductor memory characterized in that it is set lower than the threshold in the memory cell transistor and the peripheral transistor. 6. The threshold of the sense amplifier transistor is formed by making the ion concentration of a channel region of the sense amplifier transistor different from the ion concentration of a channel region of the memory cell transistor and the peripheral transistor. 6. The semiconductor memory according to claim 5, wherein the threshold value is set lower than the threshold values of the memory cell transistor and the peripheral transistor. 7. The threshold value of the sense amplifier transistor is such that an insulating film thickness between each of the conductive electrodes and the control electrode of the sense amplifier transistor is equal to a value of each of the conductive electrodes of the memory cell transistor and the peripheral transistor. 6. The semiconductor memory according to claim 5, wherein said semiconductor memory is manufactured so as to have a thickness different from an insulating film thickness between said electrodes and is set lower than threshold values of said memory cell transistor and said peripheral transistor. 8. The threshold value of the sense amplifier transistor is manufactured such that a two-dimensional shape of the control electrode in the sense amplifier transistor is different from a two-dimensional shape of the control electrode in the memory cell transistor and the peripheral transistor. 6. The semiconductor memory according to claim 5, wherein the threshold value is set lower than the threshold values of the memory cell transistor and the peripheral transistor. 9. A plurality of word lines and a plurality of bit lines according to claim 1, a plurality of storage elements for storing data, a plurality of memory cell transistors, sense amplifiers and peripheral circuits, and a precharge according to claim 5. Transistor, and a control electrode and two conductive electrodes that are turned on or off according to the level of the voltage of the control electrode with respect to a threshold value. A control signal is supplied to the control electrode, and one of the conductive electrodes is Is provided with a plurality of word line driving transistors to which a predetermined voltage is applied and the other conductive electrode is connected to each of the word lines, and which is turned on based on the control signal to respectively drive the voltage of each of the word lines. Wherein the threshold value of the word line driving transistor is set lower than the threshold values of the memory cell transistor and the peripheral transistor. Body memory. 10. The threshold value of the word line driving transistor is manufactured such that an ion concentration of a channel region of the word line driving transistor is different from an ion concentration of a channel region of the memory cell transistor and the peripheral transistor. 10. The semiconductor memory according to claim 9, wherein the threshold value is set lower than the threshold values of the memory cell transistor and the peripheral transistor. 11. The threshold value of the word line driving transistor is such that the insulating film thickness between each of the conduction electrodes and the control electrode in the word line driving transistor is equal to the conduction thickness in the memory cell transistor and the peripheral transistor. 10. The semiconductor memory according to claim 9, wherein an insulating film thickness between the electrode and the control electrode is made different so as to be set lower than threshold values of the memory cell transistor and the peripheral transistor. . 12. The threshold value of the word line driving transistor is such that a two-dimensional shape of the control electrode in the word line driving transistor is different from a two-dimensional shape of the control electrode in the memory cell transistor and the peripheral transistor. 10. The semiconductor memory according to claim 9, wherein the threshold voltage of the memory cell transistor and the peripheral transistor is set lower than that of the memory cell transistor. 13. The method according to claim 2, wherein the number of steps of implanting ions into the respective channel regions is changed for each of the transistors, so that the respective ion concentrations are different. Semiconductor memory. 14. The semiconductor device according to claim 3, wherein the number of steps of forming each of the insulating film thicknesses is changed for each of the transistors, so that the difference in the insulating film thickness is formed. Or the semiconductor memory according to 11.