JP3450974B2 - Semiconductor memory - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory such as a dynamic random access memory (hereinafter referred to as DRAM) configured by using a transistor.

[0002]

2. Description of the Related Art A memory cell of a DRAM includes a plurality of capacitors arranged at intersections of a plurality of word lines and a plurality of bit lines for storing data, and a plurality of capacitors for turning on / off the capacitors and the bit lines. And a memory cell transistor. Each memory cell transistor is, for example, an N-channel MOS transistor (hereinafter referred to as NMOS)
And the gates of the memory cell transistors are connected to one word line. When the voltage of the word line applied to the gate exceeds the threshold value, the memory cell transistor is turned on, and the data stored in the capacitor is read to the bit line.

In a DRAM, one bit line consists of two bit lines.
There is a bit line folded type in which one bit line pair is used as an access unit. The bit line pair of this DRAM is composed of an NMOS, a P-channel type MOS transistor (hereinafter referred to as PMOS), etc., and a sense amplifier for detecting and amplifying the voltage of each bit line, and a bit line composed of, for example, NMOS. An equalizer or the like for setting the pair voltage to the precharge voltage is connected. A word line driving transistor that drives the word line by voltage is connected to the word line. This DRAM is further provided with a logic circuit such as a decoder, an I / O circuit for inputting / outputting access data of memory cells, a power supply circuit for supplying a power supply voltage to each unit, and the like. Peripheral circuits such as these logic circuits, I / O circuits, and power supply circuits are also composed of MOS transistors, and these are formed on the same semiconductor substrate together with the memory cells, sense amplifiers, equalizers, and word line driving transistors. . Since the DRAM has a simple memory cell structure, a large-capacity semiconductor memory can be constructed. In recent years, a bit line folded type DRAM, which has a highly integrated DRAM and uses a bit line pair as an access unit, has become mainstream.

[0004]

However, the conventional DRAM has the following problems. FIG. 2 is a circuit diagram showing a configuration example of a conventional DRAM. This DRA
M is a bit line folded type DRAM, which includes a memory cell 10. The memory cell 10 includes a capacitor 11 provided at an intersection of a word line WL and a bit line pair BL or BL /, and a memory cell transistor for turning on / off the capacitor 11 and the bit line BL or BL /. And NMOS 12, respectively. NMO
The gate of S12 is connected to the word line WL. The NMOS 12 is turned on when the voltage of the word line WL connected to the gate exceeds a threshold value, and connects the capacitor 11 and the bit line BL. As a result, the capacitor 1
The data stored in 1 will be read onto the bit line BL.

To the word line WL, NMOSs 21a and 21b of word line driving transistors are connected. N
The gate of the MOS 21a is the NAND circuit 22 of the decoder.
Is connected to the output terminal of. NMOS 21a is NA
When the signal given from the ND circuit 22 exceeds the threshold value, the word line WL and the ground are connected.
The gate of the NMOS 21b is connected to the output terminal of the NAND 22 via the inverter 23. NMOS 21
The line b connects the word line WL and the power supply voltage Vcc when the signal supplied from the inverter 23 exceeds the threshold value. A sense amplifier 30 is connected to the bit line pair BL, BL /. The sense amplifier 30 is an NMO
Comprised of a differential amplification amplifier using S and PMOS,
For example, it has a function of amplifying the data read to the bit line BL by amplifying the potential difference between the bit line pair BL, BL /. Equalizers 40A and 40B are further connected to the bit line BL and the bit line BL /. The equalizer 40A has an equalize signal E for each gate.
It is composed of two NMOSs 41 and 42 to which Q1 / is commonly given. The drain of the NMOS 41 is the bit line B
It is connected to L and the source of the NMOS 41 is connected to the NMOS 42.
The drain of is connected. The source of the NMOS 42 is connected to the bit line BL /. Equalizer 40B
Is an NM whose gate is supplied with an equalize signal EQ2 /
It is composed of the OS 43. The drain of the NMOS 43 is connected to the bit line BL, and the source of the NMOS 43 is connected to the bit line BL /.

The DRAM of FIG. 2 is further provided with an HVcc generation circuit 50. HVcc generation circuit 50
Is a circuit that generates a voltage HVcc that is half the voltage value of the power supply voltage Vcc. For example, NMOSs 51 and 52 are connected to the output side of the HVcc generation circuit 50. N
The MOS 51 has an equalizing signal EQ inputted to its gate.
When 1 / exceeds the threshold value, the voltage HVcc is applied to the NMOS 41
Is connected to the connection point between the source of the source and the drain of the NMOS 42. The NMOS 52 receives the voltage H when the equalizing signal EQ1 / input to the gate exceeds the threshold value.
The connection is such that Vcc is applied to one electrode of the capacitor 11.

In such a DRAM, when the memory is in the standby state, the bit lines BL and BL / are set to the voltage HV.
Precharge to cc. That is, the equalize signal EQ1
The voltage of / is raised to turn on the NMOSs 41 and 42, and the equalize signal EQ2 / is raised to NMO.
S43 is turned on. As a result, the voltage HVcc
Are applied to the bit lines BL and BL / and are equalized. Immediately before accessing the memory cell 10, the equalize signals EQ1 / and EQ2 / fall,
The NMOSs 41, 42 and 43 are turned off. If the voltage of the word line WL and the bit lines BL, BL / rises before the completion of this precharge, it naturally causes a malfunction. Therefore, considering the high speed operation of the DRAM, the time required for precharge (equalization). Is better to be shorter.
However, the NMOS that controls the speed of this equalizing operation
The threshold values of 41, 42, and 43 cannot be set independently for the sake of process simplification. On the other hand, in the peripheral circuits and memory cell transistors other than the equalizers 40A and 40B, in order to secure the operational reliability of a single transistor, the leakage current between the source and drain is 1E when the gate voltage is 0V.
There are some transistors that need to be set to about -12 A or less. Therefore, the NMOS 41, 42, 4
In most cases, the threshold value of 3 was set to the same threshold value as that of the transistors or memory cell transistors of the peripheral circuit. In particular , memory cell transistors are also NMOS
In the current DRAM configured in, sometimes set at a value close to 1V, upon the speed of memory operation, the size
Was an obstacle.

Further, for the transistors in the sense amplifier 30, the speed of the memory operation can be increased by setting the threshold value low for the same reason as in the case of the NMOSs 41, 42 and 43. The threshold is set to the same level as that of the internal transistor and the memory cell transistor, which is an obstacle to speeding up the memory operation. The NMOSs 21a and 21b of the word line driving transistors are also NM
For the same reason as in the case of the OSs 41, 42, and 43, setting the threshold value low makes it possible to speed up the memory operation. It is set and it is an obstacle to speeding up the memory operation.

[0009]

In order to solve the above problems, in the invention according to claim 1, in a semiconductor memory,
The word line and the word line intersect with each other through an insulating layer.
Intersection of the bit line, and the bit line and the word line
And a word line drive, which are arranged in the
Drive transistor, memory cell transistor, sensor
Amplifier, precharge transistor, and peripheral circuits
And are formed on a common semiconductor substrate.
It The word line driving transistor includes a control electrode and a threshold voltage.
Depending on the level of the voltage of the control electrode with respect to the value,
Or two conducting electrodes that are turned off, and the control electrode
A control signal is applied and a predetermined voltage is applied to one of the conducting electrodes.
And the other conducting electrode is connected to the word line.
Then, it is turned on based on the control signal to drive the word line with a voltage.
It is a transistor. The memory cell transistor
The voltage of the control electrode with respect to the control electrode and the threshold value.
With two conducting electrodes that turn on or off depending on
The control electrode is connected to the word line and
The conductive electrodes are connected to the bit line and the memory element, respectively.
And is turned on when the voltage of the word exceeds a threshold value.
A transistor for reading the data of the storage element to the bit line.
It The sense amplifier is a control connected to the bit line.
Depending on the level of the control electrode and the voltage of the control electrode with respect to the threshold value
Sensor with two conducting electrodes that turn on or off
It has an amplifier transistor and stores the data on the bit line.
The level is detected by the threshold of the sense amplifier transistor
It is a circuit that amplifies the level of data. The preacher
The transistor for power supply is controlled by the precharge signal.
Depending on the level of the voltage of the control electrode with respect to the control electrode and the threshold value
And two conducting electrodes that are turned on or off between
A precharge voltage is applied to one of the through electrodes and the other
Connected to the bit line and the precharge
The signal is turned on based on a signal to precharge the bit line.
It is a randista. The peripheral circuit has a control electrode and a threshold.
Depending on the level of the voltage of the control electrode to the
It has a peripheral transistor with two conducting electrodes that are turned off.
The control signal, the voltage, the precharge signal,
Generates power for the precharge voltage and the sense amplifier.
Circuit for generating data and inputting / outputting data of the bit line
Is. Then, in the word line driving transistor,
The threshold is set to the memory cell transistor and the periphery.
It is set lower than the threshold value of the transistor.

According to the invention of claim 2, the semiconductor of claim 1
In the body memory, the word line driving transistor
The threshold value is the channel in the word line driving transistor.
The ion concentration of the memory cell transistor
Ion concentration in the channel region of the peripheral transistor
The memory cell is manufactured at a different temperature.
Than the threshold in transistors and peripheral transistors
It is set low. In the invention according to claim 3,
In the semiconductor memory of No. 1, the word line driving transistor is
The threshold of the transistor should be set in the word line driving transistor.
The insulation film thickness between each of the conducting electrodes and the control electrode is
In the memory cell transistor and the peripheral transistor
Insulating film thickness between each of the conducting electrodes and the control electrode in
Is manufactured differently from the memory cell
Below threshold in transistors and peripheral transistors
Has been set. In the invention according to claim 4, claim 1
In the semiconductor memory of
The threshold value of the transistor in the transistor for driving the word line is
The two-dimensional shape of the control electrode is the memory cell transistor.
Of the control electrode in the transistor and the peripheral transistor.
The memo is made by making it different from the three-dimensional shape.
Threshold in recell transistor and peripheral transistor
Is set lower than.

According to the invention of claim 5, the memory cell transistor
A memory cell for storing data,
A bit line connected to the memory cell and the memory cell
In response to the word line connected to the transistor and the select signal
A word line driving transistor that activates the word line.
And a word line driver
The threshold value of the driving transistor is the memory cell transistor
Is set lower than the threshold value of the data. Invention according to claim 6
Has a memory cell transistor and stores data
Memory cell and bit line connected to the memory cell
And a word line connected to the memory cell transistor
In response to the select signal, the word line activation circuit is activated.
It has a transistor for driving the power line and a peripheral transistor
In a semiconductor memory having a peripheral circuit
The threshold value of the transistor for driving the line is
Is set lower than the threshold value of the data. Invention according to claim 7
Then, in the semiconductor memory according to claim 6, the word line
The threshold of the driving transistor is the memory cell transition
It is set lower than the threshold value of the star.

According to the inventions of claims 1 to 7,
By adopting such a configuration, when the semiconductor memory reads data to the bit line, the precharge signal is applied to the control electrode of the precharge transistor. When the precharge signal exceeds the threshold value, the precharge transistor is turned on and the bit line is charged (precharged) to the precharge voltage. When the control signal exceeds the threshold value, the word line driving transistor is turned on, and the data in the storage element is read to the bit line. The voltage of the bit line is a voltage obtained by superimposing the data level on the precharge voltage. The sense amplifier detects the voltage of the bit line with a threshold value, amplifies it, and sets the voltage of the bit line to a voltage corresponding to the data. Here, the sum
The threshold of the power line drive transistor is set low
Therefore, the rise of the word line becomes faster.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION (First Reference Example) FIG. 3 is a circuit diagram of a DRAM showing a first reference example of the present invention. This DRAM is a bit line folded type DRA.
The threshold value of the equalizing transistor, which is M, which is a precharging transistor for charging the bit line, is set lower than the threshold values of the other transistors, thereby making it possible to speed up the memory operation. The word line WL and the first and second bit lines BL and BL / are insulated by an insulating layer (not shown), and the word line WL and the bit lines BL and BL / are arranged in a cross manner. The memory cell 60 of the DRAM of FIG.
Is a capacitor 61 which is a memory element provided at the intersection of the word line WL and the bit line pair BL or BL /,
It has an NMOS 62 which is a memory cell transistor for turning on and off between one electrode of the capacitor 61 and the bit line BL or BL /. The gate, which is the control electrode of the NMOS 62, is connected to the word line WL.
The threshold value of the NMOS 62 is set to Vt1.

To the word line WL, NMOSs 71a and 71b which are word line driving transistors are connected. The thresholds of the NMOSs 71a and 71b are also set to Vt1. The gate of the NMOS 71a is connected to the output terminal of the NAND circuit 72 of the decoder forming the peripheral circuit. The NMOS 71a connects the word line WL and the ground GND when the control signal given from the NAND circuit 72 exceeds the threshold value Vt1. NMO
The gate of S71b is connected to the output terminal of the NAND circuit 72 via the inverter 73. NMOS 71b
Indicates that the control signal given from the inverter 73 is the threshold value Vt.
When it exceeds 1, the word line WL is connected to the power supply voltage Vcc. A sense amplifier 80 is connected to the bit line BL and the bit line BL /. The sense amplifier 80 includes NMOSs 81 and 82 of sense amplifier transistors whose gates are connected to the bit lines BL and BL / and PM.
It is composed of a differential amplification amplifier using the OSs 83 and 84. The sense amplifier 80 has a function of amplifying the data read to the bit line BL by amplifying the potential difference between the bit line pair BL, BL /. The thresholds of the NMOSs 81 and 82 and the PMOSs 83 and 84 in the sense amplifier 80 are also set to Vt1.

Equalizers 90A and 90B are further connected to the bit line BL and the bit line BL /. The equalizer 90A is composed of two NMOSs 91 and 92 which are precharging transistors to which the equalize signal EQ1 / which is a precharge signal is commonly applied to each gate. The drain of one conduction electrode of the NMOS 91 is connected to the bit line BL, and the drain of the NMOS 92 is connected to the source of the other conduction electrode of the NMOS 91. The source of the NMOS 92 is connected to the bit line BL /. The equalizer 90B is composed of an equalize NMOS 93, which is a short-circuit transistor, whose gate receives an equalize signal EQ2 / which is a control signal.
The drain of the NMOS 93 is connected to the bit line BL, and the source of the NMOS 93 is connected to the bit line BL /. The threshold value of these NMOSs 91, 92, 93 is the threshold value V
It is set to Vt2 which is lower than t1. This DRAM
Further, the HVcc generation circuit 10 which is a peripheral circuit
0, a control circuit (not shown) that generates a precharge signal,
An I / O circuit (not shown) for inputting and outputting access data is provided. The HVcc generation circuit 100 is a circuit that generates a voltage HVcc that is half the voltage value of the power supply voltage Vcc. For example, an NMOS 101 and an NMOS 102 are connected to the output side of the HVcc generation circuit 100. The threshold of each NMOS 101, 102 is set to Vt1. The NMOS 101 is connected so as to apply the voltage HVcc to the connection point between the source of the NMOS 91 and the drain of the NMOS 92 when the equalizer signal EQ1 / input to the gate exceeds the threshold value Vt1. NMOS 10
2 indicates that when the equalizing signal EQ1 / input to the gate exceeds the threshold value Vt1, the voltage HVcc is transferred to the capacitor 61.
Is connected to the other electrode of.

The threshold values Vt2 of the NMOSs 91, 92 and 93 and the threshold value Vt1 of the other transistors are, for example, NMOS.
Alternatively, it is possible to differentiate by changing the channel ion concentration of the PMOS or by increasing the thickness of the gate oxide film which is an insulating film. When changing the channel ion concentration, ion implantation is performed in multiple times. That is, normal photolithography and ion implantation are increased once or more in the ion implantation step of the wafer process, and a part of the ion implantation is performed by the NMOSs 91 and 9.
By masking 2,93 channels, the NMOS9
The channel ion concentrations of 1, 92 and 93 can be made thinner than those of other transistors. Also in the case of thickening the gate oxide film, the gate oxide film forming process is divided into a plurality of times and the other transistors are masked to form the NMOS 91, 92, 93.
If the gate oxide film is formed on the
The gate oxide film of 1, 92, 93 can be thickened.

FIG . 4 is a time chart showing the operation of FIG. 3, and the operation of the DRAM of FIG. 3 will be described with reference to this figure. First, when the memory is in the standby state, the voltage of the equalize signal EQ1 / is raised,
The NMOSs 91, 92, 101 and 102 are turned on, the equalize signal EQ2 / is raised, and the NMOS 93 is turned on. As a result, the bit lines BL and BL / have the voltage HVcc.
Is precharged and equalized. When the equalize signals EQ1 / and EQ2 / fall, the NMOS 9
1, 92, 101, 102 and the NMOS 93 are turned off. In this state, the control signal is given, the NMOS 71a is turned off, the NMOS 71b is turned on, and the word line WL is set to the voltage V.
driven to cc. When the word line WL is driven by voltage, N
The MOS 62 is turned on, and the capacitor 61 is connected to the bit line BL.
The data stored in is read. The sense amplifier 80 detects it at the threshold value Vt1 and amplifies the voltage of the bit line BL. As a result of the amplification, the voltage of the bit line BL is set to the level corresponding to the data as shown in FIG. After that, the voltage of the bit line BL is output to the outside or written in the capacitor 61 again. As described above, in the first reference example , the threshold V of the NMOSs 91, 92, 93 is
Since t2 is set to be lower than the threshold value Vt1 of the other transistors, the precharge time performed based on the equalize signals EQ1 / and EQ2 / can be shortened. This is shown in Figure 3.
It is obvious from the fact that the response to the equalize signal EQ1 / of 1 becomes short, and the memory operation can be speeded up. Further, since the threshold value is changed according to the ion concentration and the gate oxide film thickness, the shapes of the respective transistors can be put together and the degree of freedom in layout can be secured.

(Second Reference Example) FIG. 5 is a circuit diagram of a DRAM showing a second reference example of the present invention. In this DRAM, the threshold value of the sense amplifier transistor in the sense amplifier is set lower than the threshold values of the other transistors, and the sense amplifier 80 is changed to the sense amplifier 110 and the equalizers 90A and 90B.
Is the same as that of FIG. 3 except that the equalizers 120A and 120B are changed. The sense amplifier 110 is connected to the bit lines BL and BL /, and its gates are connected to the bit lines BL and BL /.
It is composed of a differential amplification amplifier using 114. The sense amplifier 110 has a function of amplifying the data read to the bit line BL by amplifying the potential difference between the bit line pair BL and BL /. This sense amplifier 110
Inside the NMOS 111, 112 and the PMOS 113, 114
Each of the thresholds is set to Vt2 which is lower than the threshold Vt1.

The equalizers 120A and 120B are connected to the bit line BL and the bit line BL /. The equalizer 120A is composed of two equalize transistor NMOSs 121 and 122 whose gates are commonly provided with an equalize signal EQ1 / which is a precharge signal. The drain of the NMOS 121 is connected to the bit line BL, and the source of the NMOS 121 is connected to the drain of the NMOS 122. The source of the NMOS 122 is connected to the bit line BL /. The equalizer 120B is
It is composed of an equalize NMOS 123 whose gate is supplied with an equalize signal EQ2 /. The drain of the NMOS 123 is connected to the bit line BL.
Source is connected to the bit line BL /. These N
The threshold value of the MOS 121 to 123 is set to the threshold value Vt1. NMOS or PMO in the sense amplifier 110
The threshold value Vt2 of S and the threshold value Vt1 of other transistors are
Differentiation can be achieved by changing the channel ion concentration or by increasing the thickness of the gate oxide film which is an insulating film. Specifically, similar to the first reference example , it is realized by separately performing the ion implantation step or the gate oxide film forming step a plurality of times. DR of FIG.
The AM basically performs the same operation as that of the first reference example . As described above, in the second reference example , the sense amplifier 11
Since the threshold value Vt2 of 0 is set lower than the threshold values Vt1 of the other transistors, the sensing time can be shortened. This is apparent from the fact that the response on the bit line BL in FIG. 4 is short, and the memory operation can be speeded up.

(Embodiment) FIG. 1 is a circuit diagram of a DRAM showing an embodiment of the present invention. In this DRAM, the threshold of the word line driving transistor is set lower than the thresholds of the other transistors, and the word line driving transistor NMOS71 is used.
a and 71b are changed to NMOS 131a and 131b, and equalizers 90A and 90B are equalizer 120.
The connection is the same as that of FIG. 3 except that it is changed to A and 120B. The gate of the NMOS 131a is
It is connected to the output terminal of the NAND circuit 72. NMO
The gate of S131b is connected to the output terminal of the NAND 72 via the inverter 73. These NMOS1
The thresholds of 31a and 131b are Vt lower than the threshold Vt1.
It is set to 2. The NMOS 131a connects the word line WL and the ground GND when the control signal given from the NAND circuit 72 exceeds the threshold value Vt2, and NM
The OS 131b connects the word line WL and the power supply voltage Vcc when the control signal given from the inverter 73 exceeds the threshold value Vt2. Equalizer 120
A and 120B are the same as in the second reference example . NMOS
The threshold value Vt2 of 131a and 131b and the threshold value Vt1 of other transistors can be differentiated by changing the channel ion concentration or by increasing the thickness of the gate oxide film which is an insulating film. In particular,
Similar to the first reference example , it is realized by separately performing the ion implantation step or the gate oxide film forming step a plurality of times.

The DRAM of FIG . 1 also basically operates in the same manner as in the first reference example . As described above, in this embodiment , the threshold Vt2 of the NMOS 131a and 131b is set lower than the threshold Vt1 of the other transistors, so that the time required for driving the word line can be shortened. This is apparent from the fact that the rise of the word line WL in the bit line BL in FIG. 4 takes a short time, and the memory operation can be speeded up. The present invention is not limited to the above-mentioned reference examples and embodiments, and various modifications are possible. As a modification,
For example:

(1) In the reference examples and the embodiments, one memory cell 60 is described for simplification, but the plurality of memory cells 60 include a plurality of word lines WL and a plurality of bit lines BL, BL. It goes without saying that the present invention can also be applied to the case where they are arranged in a matrix at intersections of /. (2) In the reference examples and embodiments, an example of a bit line folded type DRAM is shown. However, even if the present invention is applied to a DRAM other than the bit line folded type DRAM, the same effect as that of the reference example or the embodiment is obtained. Can be expected. (3) The configuration of the sense amplifier shown in the reference example or the embodiment may be other configurations. (4) In the reference examples and the embodiments, the threshold value is differentiated by changing the ion concentration and the gate oxide film thickness, but the two-dimensional shape of the transistor is changed by changing the gate length and width. You may go in. In this case, the number of steps can be simplified. Further, the threshold value may be differentiated by another suitable method.

[0023]

As described in detail above, the first to third aspects are described .
According to the invention of claim 7, since the threshold value in the word line driving transistor is set lower than the threshold values in the memory cell transistor and the peripheral transistor, the time for starting the word line can be shortened and the speed of the semiconductor memory can be increased. Become.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a DRAM showing an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration example of a conventional DRAM.

FIG. 3 is a circuit diagram of a DRAM showing a first reference example of the present invention.
Is.

FIG. 4 is a time chart showing the operation of FIG.

FIG. 5 is a circuit diagram of a DRAM showing a second reference example of the present invention.

[Explanation of symbols]

60 memory cell 61 capacitor (memory element) 62 memory cell transistor 71a, 71b, 131a, 131b word line drive transistor 80, 110 sense amplifier 81-84, 111-114 sense amplifier transistor 90A, 90B, 120A, 120B equalizer 93, 123 short-circuit transistors 91, 92, 121, 122 precharge transistors BL, BL / bit line WL word line

Front page continued (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/8242 G11C 11/409 H01L 27/108

Claims (7)

(57) [Claims] And 1. A word line, and said word line is located at the intersection between the bit line and the bit line crossing through the insulating layer, and the word line,
Depending on the storage element for storing data and the voltage level of the control electrode with respect to the control electrode and the threshold value
Two conducting electrodes that are turned on or off between
A control signal is applied to the control electrode and one of the conducting electrodes is
When a predetermined voltage is applied and the other conductive electrode is the word
Connected to a line and turned on according to the control signal to turn on the word line.
And a word line driving transistor for driving the voltage of the
Two conducting electrodes that are turned on or off between
A control electrode is connected to the word line and
Poles are connected to the bit line and the storage element, respectively.
Is turned on when the voltage of the word exceeds a threshold value, the memory element is turned on.
Memory cell transistor for reading child data to the bit line
A motor, a control electrode connected to said bit lines, said relative threshold
Turns on or off depending on the voltage of the control electrode
Has a sense amplifier transistor with two conducting electrodes
The level of data on the bit line to the sense amplifier.
Amplify the level of the data by detecting with the threshold of the transistor
Sense amplifier, control electrode to which precharge signal is applied and threshold
Depending on the level of the voltage of the control electrode, the space is turned on or off.
Two conducting electrodes, and one of the conducting electrodes is
A charge voltage is applied and the other conducting electrode is
Connected to the power line and turned on based on the precharge signal.
Precharge transition for precharging the bit line
Of the control electrode and the voltage of the control electrode with respect to the threshold value.
With two conductive electrodes that turn on or off
A transistor, the control signal, the voltage, the
Recharge signal, the precharge voltage and the sense
The power of the amplifier is generated and the data of the bit line is
A semiconductor memory that has a peripheral circuit that performs input and output and these are formed on a common semiconductor substrate.
Oite, threshold in the word line driver transistor, said
In the memory cell transistor and the peripheral transistor
A semiconductor characterized by being set lower than a threshold
memory. 2. A threshold before Symbol word line driving transistors
Is the channel region of the word line driving transistor.
The ion concentration of the region is the memory cell transistor and
Ion concentration in the channel region of the peripheral transistor
Are produced differently, so that the memory cell
Lower than threshold in transistors and peripheral transistors
The semiconductor memo according to claim 1, which is set.
Li. 3. The threshold value of the word line driving transistor
Is the conduction of each of the word line driving transistors.
The insulation film thickness between the electrode and the control electrode is the memory cell.
Each of the transistors and the peripheral transistors
Differentiate the insulation film thickness between the conducting electrode and the control electrode.
The memory cell transistor and
And lower than the threshold value of the peripheral transistor
The semiconductor memory according to claim 1, wherein: 4. The threshold of the word line driving transistor
Is the control voltage in the word line driving transistor.
The two-dimensional shape of the pole is the memory cell transistor and the two-dimensional shape.
Two-dimensional shape of the control electrode in the peripheral transistor and
Are produced differently, so that the memory cell
Lower than threshold in transistors and peripheral transistors
The semiconductor memo according to claim 1, which is set.
Li. 5. Data having a memory cell transistor
A memory cell for storing a memory cell, a bit line connected to the memory cell, a word line connected to the memory cell transistor, and a word activating the word line in response to a selection signal.
A semiconductor memory with a line driving transistor
Te, the threshold of the word line drive transistor, the memory
A semiconductor characterized by being below the threshold of a cell transistor
Body memory. 6. Data having a memory cell transistor
A memory cell for storing a memory cell, a bit line connected to the memory cell, a word line connected to the memory cell transistor, and a word activating the word line in response to a selection signal.
A semiconductor device including a line driving transistor and a peripheral circuit having a peripheral transistor.
In the memory, the threshold of the word line driving transistor is
Semiconductor memory characterized by being lower than the threshold of the transistor
Li. 7. The threshold value of the word line driving transistor
Is lower than the threshold of the memory cell transistor
The semiconductor memory according to claim 6, which is characterized in that.