JPH10177543A - Bus control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the using efficiency of a data bus and to decrease the processing interruption frequency by adding the information on the width of buses used for every bus master and managing the data bus in each byte. SOLUTION: When a bus arbitration part 302 recognizes a bus request 311 of a bus master A301, the part 302 compares the data bus width with the value obtained by adding together the data bus width 319 under use and the using request data width 312 and outputs this comparison result to a bus arbitration circuit. When the bus arbitration circuit decides that the bus width whose use is requested can be secured on one of data buses 340 to 343, a bus use enabling signal 313 is transmitted to the master A301. Thus, it is possible to simultaneously transmit the 16-bit data transferred from the master A301 and the 16-bit data transferred from a bus master B304 to one of data buses 340 to 343 of 32-bit width.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus control circuit in a system having a multi-bus master configuration.

[0002]

2. Description of the Related Art First, a multi-bus master system will be described. A conventional bus control method for a multi-master system having a multi-CPU configuration is disclosed in
No. 7934. FIG. 9 shows a conceptual diagram of a configuration example of a multi-bus master system. In FIG. 9, a multi-bus master system includes a bus master A 100, a bus master B 101, a bus arbitration circuit 102, a 16-bit width memory 103, a 32-bit width memory 104, an 8-bit width I / O device 105, a data bus 106, and a bus master A. Bus request signal 120, bus grant (transfer permission) signal 121, bus transfer end signal 122, bus request signal 123 of bus master B, bus grant signal 12
4. Assume that it is composed of a bus transfer end signal 125.

When the bus master A 100 accesses the data bus 104 via the data bus 106, the data bus 106
Is notified to the bus arbitration circuit 102 by a bus request signal 120. The bus arbitration circuit 102 makes a determination based on the bus usage status of the bus master B 101 at that time, and if it determines that the bus is not used, the bus arbitration circuit 102
The bus transfer permission is given by outputting the bus grant signal 121 to the bus master 100, and the bus transfer cycle of the bus master A100 is started. On the other hand, when the bus master B 101 is already using the data bus 106, the bus master A 10
0 outputs a bus request signal 120 and makes a bus request, the bus arbitration circuit 102 determines that the bus is in use, and until the transfer cycle of the bus master B 101 indicates the end by the bus transfer end signal 125, the bus grant signal Since bus 121 is not activated, bus master A 100
Enters a standby state. When the bus master B101 completes the transfer cycle and activates the bus transfer end signal 125, the transfer of the bus master A100 is started.
As described above, in a system with a multi-bus master configuration, while one bus master is using the bus,
Other processors can no longer use the bus,
The bus master processor using the bus suspends the processing using the data bus until the data bus is released.

FIG. 10 is a timing diagram showing the bus access as a cycle on the horizontal axis and data and various control signals transmitted to the circuit on the vertical axis. In this example,
It is assumed that the data bus and the address bus are separated, the data width is 32 bits, and a transfer cycle is generated in a burst of 8 words on the data bus. The address is determined at the start of the burst transfer, and the address is not used during the subsequent burst period.

The bus master B 101 activates the bus request signal 123 during cycle 1. During the cycle 2, the bus arbitration circuit 102 outputs the bus grant signal 1
24 to the bus master B101. In the period of cycle 3, the bus master B101 starts burst transfer, sends out the address A1 to the address bus, and outputs 16-bit data as the lower data DL3. In the same period, the upper data DH3 becomes invalid data. In cycles 4 to 10, burst data DL4 to DL10 following the lower data DL3 are output. During the same period, DH
4 to DH10 are invalid data. The period of cycles 4 to 10 is an invalid address. In cycle 4, the bus master A 100 outputs a bus request signal 120. At the time of cycle 5, since the bus is used by the bus master B101, the bus permission signal 121 of the bus master A100 is not output. In the cycle 10, the last burst data of the bus master B101 is output, and at the same time, the bus transfer permission signal 121 of the bus master A100 is output. In cycle 11, the burst transfer cycle of the bus master A100 is started, and A2 is transferred to the address bus.
And outputs data to DL11.

[0006]

In the case of the prior art described above, if the data bus has a 32-bit width and the data width used by the bus master B101 for burst data transfer is 16 bits, During burst transfer, invalid data is always on the data bus. However, the bus master A100, which is the other bus master, is connected to the bus line on which the invalid data is on.
Transfer is impossible because the right to use the bus cannot be obtained until the bus master B101 activates the bus transfer end signal. Therefore,
In the data transfer of the bus master B 101, the bus master B 101 uses only a part of the data bus.
Until the data transfer of the bus master 101 is completed.
0 means that processing must be interrupted.

Accordingly, it is an object of the present invention to provide a bus control circuit for speeding up data transfer in a bus control method in a multi-bus master system.

[0008]

In order to solve the above-mentioned problems, a bus control method according to the present invention uses a bus width, a bus request, a bus grant, and a bus transfer completion information for each bus master. By managing the data bus on a byte-by-byte basis, if the bus width is less than the width of a bus not used for data transfer when a use request is made, data can flow to an unused area, It improves the efficiency of use of the data bus and reduces interruption of bus master processing.

According to a first aspect of the present invention, there is provided a register for holding a data width during transfer, a bus area used for data transfer, and a bus transfer request and transfer output from a bus master. Enter the required data width,
A comparison circuit for comparing the sum of the data width held in the register and the bus transfer request width with the width of the data bus; and determining a bus transfer permission to the bus master from the output of the comparison circuit and the bus transfer request. A bus arbitration circuit, a bus state control unit that detects an unused area of the bus from a bus area used for data transfer held in the register,
A bus control circuit comprising: a selector for outputting data to be output to a data bus according to an output of the bus state control unit; and a bus driving circuit for driving the bus only in an effective area.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to FIGS.

(Embodiment 1) FIG. 3 shows a configuration example of a bus control circuit of a multi-bus master according to the present invention. In FIG.
Reference numeral 301 denotes a 32-bit bus master, 302 denotes a bus arbitration unit, 303 denotes a bus state register, 311 denotes a bus request signal for requesting the bus master A 301 to access the data bus 340 to 343, and 312 denotes a bus master A3.
01 is a data width requested when accessing the data buses 340 to 343, and 313 is a data width of the data buses 340 to 343.
A bus use approval signal 314 is a bus master A.
This is a bus transfer end signal indicating that the transfer of 301 has been completed.

Reference numeral 331 denotes a local data bus having a width of 32 bits which is in direct contact with the bus master A 301 and is inputted to the byte selection circuit 305. 321 is a byte selection circuit 30
The data delimited every 8 bits by 5 is 340 to 34
3 is a byte selection circuit control signal for determining which data bus to transfer to. Reference numeral 320 denotes a bus drive circuit control signal indicating which of the buses 340 to 343 is to be driven in the bus cycle generated by the bus master A301.

Reference numeral 350 denotes a data width in use, and 351 denotes a data area in use, which is included in the bus state register 303. 319 is output data of the used data width 350 and 333 is output data of the used data area 351, and is supplied to the bus arbitration unit 302.

Reference numeral 304 denotes a 32-bit bus master B, 315
Is a bus request signal for requesting the bus master B304 to access the data buses 340 to 343, 316 is a data width requested when the bus master B304 accesses the data buses 340 to 343, and 317 is a bus use for the data buses 340 to 343. An acceptance signal 318 is a bus transfer end signal indicating that the transfer of the bus master B 304 has been completed.

Reference numeral 332 denotes a 32-bit data bus which is in direct contact with the bus master B 304 and is input to the byte selection circuit 306. Reference numeral 323 denotes a byte selection circuit control signal for determining to which of the data buses 340 to 343 the data divided every eight bits by the byte selection circuit 306 is transferred. Reference numeral 322 denotes a bus selection signal 340 to 343 in the bus cycle generated by the bus master B 304. Is a bus drive circuit control signal indicating which bus is to be driven.

Reference numeral 329 denotes an address output from the bus master A 301, and reference numeral 330 denotes an address output from the bus master B 304. 324 is the address 329
And 330, an address selector control signal for determining which address to use, and is input to the address selector 307. The address selected by the address selector 307 is output to the address bus 327.
The address decode circuit 308 receives the address 327 and generates a memory selection signal 326.

Reference numeral 309 denotes an area selection circuit, which is 340 to 3
Forty-three data buses are input, 16-bit data is selected from 32-bit data by a byte selection signal 325, and output to a 16-bit memory bus 328.

Reference numeral 310 denotes a memory having a 16-bit data width. When the memory selection signal 326 is active, 16-bit data is input from the memory bus 328.

FIG. 4 shows the byte selection circuit 305 in FIG.
2 shows the internal configuration of FIG. The internal configuration of the byte selection circuit 306 is the same as that of the byte selection circuit 305. In FIG. 4, 4
00 is the most significant byte of 331, 401 is the most significant byte 4
Byte one lower than 00, 402 is most significant byte 40
403 indicates the least significant byte, and 403 indicates the least significant byte.
413 is input. Reference numerals 410 to 413 are input to the respective 4 by the byte selection circuit control signal 321.
00, 401, 402, 403, which output is to be determined, and selection data 420, 4
21, 422 and 423 are output. Selection data 420 ~
423 is a bus drive circuit 430 to 43 corresponding to each.
3, the selection data 430 to 433 determine whether the input data is output to the data buses 340 to 343 or set to high impedance according to the bus drive circuit control signal 320.

FIG. 5 is a diagram showing the internal configuration of the bus arbitration unit 302 in FIG. In FIG. 5, reference numeral 500 denotes a selector for inputting use request data widths 312 and 316;
Reference numeral 1 denotes an addition circuit that receives an output from the selector 500 and a data width 350 from the bus state register 303 as inputs. Reference numeral 502 denotes a constant that gives the width of the data bus, and the output is 32 in the first embodiment. A comparison circuit 503 compares the data bus width 502 with the output of the addition circuit 501, and supplies the comparison result to the bus arbitration circuit 504.
Reference numeral 504 denotes the output of the comparison circuit 503 and the bus master A301.
, And a bus transfer end signal 314 and a bus request signal 315 and a bus transfer end signal 318 output from the bus master B 304, and output bus use permission signals 313 and 317. 50
Reference numeral 5 denotes a bus state control unit, which receives an output of the bus arbitration circuit 504, a bus license signal 313, a selector output 508, a bus license signal 317, and a data area 333, and inputs control signals 320 and 321 and a bus master to a bus master A301. Control signals 322 and 323 are output to B304, and the updated used data area 506 and the updated used data width 507 are stored in the bus state register 3.
03 is output.

The operation contents when the bus master B 304 of the 32-bit data bus uses the lower 16-bit data bus and the other bus master A 301 transfers 16-bit data to the memory 310 will be described below. At this point, the data bus has the lower one, as shown in FIG.
The data output from the bus master B 304 is carried in the 6-bit 602 and 603, and the upper 16 bits 600 and 603 are stored.
Reference numeral 601 denotes an unused area.

First, when the bus master A 301 causes a bus cycle, it outputs a bus request 311 and a use request data width 312 to the bus arbitration unit 302. When the bus arbitration unit 302 recognizes the bus request 311, the comparison circuit 503 compares the value obtained by adding the data width 319 in use and the selector output 508 with the value of the data bus width 502, and determines the result. When the bus arbitration circuit 504 determines that the requested bus width can be secured on any of the data buses 340 to 343, the bus arbitration circuit 504 sends the bus licensing signal 313 to the bus master A301. Send. The bus master A 301 that has obtained the bus use license outputs the address 329 and sends the data to the byte selection circuit 305 via the local data bus 331. The bus state control unit 505 outputs the output of the bus arbitration circuit 504, the data area 333, and the data bus width 50.
2. The control signals 320 and 321 are output according to the flow of FIG. The byte selection circuit 305 determines to output the 16-bit data output by the bus master A 301 to the data buses 340 and 341 according to the control signal 321 output from the bus arbitration unit 302,
In response to the control signal 320, the bus driving circuits 430 and 431 drive the data buses 340 and 341 and
42 and 343 are set to high impedance. FIG. 7 shows an arrangement of outputs of the bus driving circuits 430, 431, 432, and 433 at this time.

With the above operation, the 16-bit data transferred by the bus master A 301 and the 16-bit data transferred by the bus master B 304 can be simultaneously transmitted to the data bus as shown in FIG.

The operation for writing the data of the bus master A 301 sent to the data bus by the above operation to the memory 310 will be described below. The address 329 output by the bus master A 301 is input to the address selector 307.
Since the bus arbitration unit 302 licenses the bus of the bus master A301, the control signal 324 is set to the address selector 3
07 operates so that the address of the bus master A301 is selected. The address of the bus master A 301 selected by the address selector 307 is supplied to the memory 310 through the address bus 327, and the memory is addressed. On the other hand, the fact that the data output by the bus master A 301 is output to the data buses 340 and 341 indicates that the byte selection signal 325 output by the bus arbitration unit 302.
The area selection circuit 309 transfers data by operating the byte selection signal 325 to the data buses 340 and 3.
The address and data output from the bus master A 301 are aligned in the memory 310 as 16-bit data input from the memory 41 and supplied as 16-bit data via the bus 328, thereby enabling writing.

FIG. 2 is a timing chart showing the above operation as a cycle on the horizontal axis, data transmitted to the circuit on the vertical axis, and various control signals. The timing diagram of FIG. 2 assumes that the data bus is generating a transfer cycle in bursts of 8 words with a width of 32 bits.

During cycle 1, bus master B 304
Activates the bus request signal 315 and outputs a signal indicating that the bus request signal 315 is 16 bits by the use request data width 316.

During the cycle 2, the bus arbitration unit 302 outputs the bus license signal 317 to the bus master B 304.

In cycle 3, the bus master B 304 sends the address A to the address bus 330,
16-bit data is transferred to the data bus 342 by D33 and 343.
Is output to D43. In the same period, D13 of the upper data bus 340 and D23 of the 341 become invalid data.

In cycle 4, bus master A301
Bus request signal 311 becomes active, and the bus width used by the bus master
This is indicated by the use request data width 312. D34 and D45 are data output by the bus master B304.

In cycle 5, data buses 340 and 34
Since a total of 16 bits of 1 are unused, bus master A
A bus license signal 313 is output to 301. D35 and D45 are data output by the bus master B304.

In cycle 6, bus master A301
Output on the address bus 329,
The data output from the bus master A301 is D1 at 340.
6, 341 and output as D26 to the bus master B30.
4 is output to the lower data buses 342 and 343 as D36 and D46.

In cycles 7 to 11, D37 to D3
11, D47 to D411 output data of the bus master B304, and D17 to D111 and D27 to D211 output data of the bus master A301.

In the above description, data is managed for each byte. However, management for other data widths can be similarly performed.

[0034]

As described above, by constructing a system using the bus control circuit according to the present invention, when a plurality of bus masters handle one data bus, one bus master has a data width less than the data bus width. When another bus master makes a data transfer request while transferring data, if the total width of both data is less than the data width, it is possible to transfer both data redundantly. Efficiency is improved, and the waiting time for a data transfer request from each bus master is reduced, so that the operation of the bus master can be accelerated.

In the present invention, it is typically effective that
In this case, one of the plurality of bus masters always monitors a slave device having a narrow data width, and data output from the slave device cannot be lost. In the above case, the access of the slave device is the bus transfer with the highest priority,
This transfer hinders data bus access by other bus masters, and hinders speeding up of the system. By using the present invention, the data bus line on the data bus can be used even during the data transfer of the device, so that the data bus can be accessed, which is effective in increasing the speed of the system. is there.

[Brief description of the drawings]

FIG. 1 is a processing flowchart of a bus state control unit 505.

FIG. 2 is a conceptual diagram showing a bus control signal pattern of the multi-bus master according to the first embodiment of the present invention.

FIG. 3 is a configuration diagram of a bus control circuit of the multi-bus master according to the first embodiment of the present invention;

FIG. 4 is an internal configuration diagram of a byte selection circuit in FIG. 3;

FIG. 5 is an internal configuration diagram of a bus arbitration unit in FIG. 3;

FIG. 6 is a diagram showing an arrangement of data when 304 outputs 16-bit data to a lower 16-bit area of a 32-bit data bus in the first embodiment;

FIG. 7 is a diagram illustrating a configuration in which the first embodiment outputs 430, 431, and 43 when 16-bit data is output to the data bus;
Diagram showing arrangement of data output by 2,433

FIG. 8 is a diagram showing the arrangement of 32-bit data when the data buses 301 and 304 are simultaneously used.

FIG. 9 is a basic bus configuration diagram in a conventional multi-bus master system.

FIG. 10 is a conceptual diagram showing a signal pattern of a conventional bus control of a multi-bus master.

[Explanation of symbols]

 301 Bus master A 302 Bus arbitration unit 303 Bus state register 304 Bus master B 305 Byte selection circuit of bus master A 306 Byte selection circuit of bus master B 310 16-bit memory 311 Bus request of bus master A 312 Requested data width of bus master A 313 To bus master A 314 Bus master A transfer end signal 315 Bus master B bus request 316 Bus master B use request data width 317 Bus master B bus license 318 Bus master B transfer end signal 319 Bus width output during use 320 Bus master A 321 Bus drive circuit control signal of bus master A 322 Bus drive circuit control signal of bus master B 323 Byte select circuit control signal of bus master B 324 SEL 325 Byte selection signal 326 Memory selection signal 327 Address bus 430 to 433 Bus driving circuit 501 Adder circuit 502 Data bus width 503 Comparison circuit 504 Bus arbitration circuit 505 Bus state controller 506 Updated data area in use 507 Updated in-use data width

Claims (2)

[Claims] 1. A register for holding a data width during transfer, a bus area used for data transfer, a bus transfer request output from a bus master and a data width requested for transfer, are input to the register. A comparison circuit that compares the sum of the held data width and the bus transfer request width with the width of the data bus; and a bus arbitration circuit that determines a bus transfer permission to the bus master from the output of the comparison circuit and the bus transfer request. A bus state control unit for detecting an unused area of a bus from a bus area used for data transfer held in the register; and outputting data to be output to a data bus by an output of the bus state control unit. A bus control circuit, comprising: a selector for controlling a bus and a bus driving circuit for driving a bus only in an effective area. 2. The bus control circuit according to claim 1, wherein the bus state control unit changes a data area to be connected according to a control signal output from the bus arbitration circuit.