JPH10177081A - Internal clock system for artificial satellite - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an internal clock system for artificial satellite that can obtain a time of high accuracy while maintaining the compatibility with conventional time system and, at the same time, can guarantee the continuation of time data processing even when the supply of signals from GPS(global positioning system) satellite is discontinued. SOLUTION: A retiming circuit 3 retimes asynchronous time signals from a GPS satellite 5 received through a GPS receiver 2 by using clock pulses from the internal oscillator 1 of the satellite 5 and, at the same time, generates time signals which have errors equal to or smaller than the interval of the clock pulses and are synchronized to the clock pulses. The retiming circuit 3 always counts the interval of the time signals from the satellite 5 as the number of the clock pulses. The circuit 3 usually transmits time signals obtained by retiming the time signals from the satellite 5 to the internal equipment 4 of the satellite 5 and, when the supply of the time signals from the satellite 5 is discontinued, continues time generation by using the measured pulse interval.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a satellite internal time system, and more particularly to a GPS (Global Posi) system.
The present invention relates to an internal time system that obtains absolute time data by using a switching system.

[0002]

2. Description of the Related Art Conventionally, in mission operation of a high-resolution observation satellite or an optical communication satellite, an accuracy of about 10 to 100 msec is required in order for a data processing system inside the satellite to specify the position of the satellite itself with an accuracy of several meters. It is necessary to obtain the satellite internal absolute time in real time.

In general, in the conventional satellite time system, the absolute time inside the satellite is obtained based on the output of an oscillator mounted inside the satellite, so that the accuracy of the satellite time depends only on the accuracy of the oscillator, and drift occurs. Accumulation of error due to

[0004] Therefore, it is conceivable to increase the accuracy of satellite time by taking in time data from GPS satellites constituting a GPS into the satellite and not relying only on the accuracy of the oscillator.

[0005] For example, as shown in FIG. 7, a satellite internal device 13 transmits a frame pulse from a satellite internal oscillator 11 and a satellite internal time, and a timing pulse and an absolute time code from a GPS satellite 14 received by a GPS receiver 12. A first configuration for direct input is conceivable. In the first configuration, a circuit for synchronizing the satellite internal time that governs the timing at which the data processing portion of the satellite internal device 13 performs satellite telemetry / command operations and a GPS time signal that is input asynchronously therewith is provided. You need to have.

As shown in FIG. 8, the satellite internal oscillator 15 is calibrated using the timing pulse from the GPS satellite 14 and the absolute time code received by the GPS receiver 16, and the satellite internal oscillator 15 is A second configuration for supplying the frame pulse and the absolute time code to 17 is also conceivable.

[0009] Further, as shown in FIG. 9, a timing pulse and an absolute time code from a GPS satellite 14 received by a GPS receiver 19 by a satellite internal time generation device 18 are directly sent to a satellite internal device 17 as a frame pulse and an absolute time code. A third configuration for supplying is also conceivable.

[0008]

In the above-mentioned conventional satellite time system, since the absolute time inside the satellite is obtained with reference to the output of the oscillator mounted inside the satellite, the accuracy of the internal satellite time is determined by the accuracy of the oscillator. It is unavoidable that the accumulation of errors due to drift is inevitable, and even if the time is calibrated by commands from the ground due to the drift of the satellite internal clock, the errors accumulate in several hours to several days,
The error between the satellite time and the absolute time cannot satisfy the requirement.

In the case of a configuration in which the satellite internal clock is directly calibrated by a time signal from the GPS, time discontinuity occurs at the time of calibration, which is disadvantageous for the operation of a satellite-mounted device driven by counting the internal clock. Occurs.

Further, when the internal device is directly driven by the time signal from the GPS, it is necessary to newly design the time signal processing system of the mounted device, and it is necessary to abandon the existing design. In this case, since the time signal from the GPS is asynchronous with the internal clock of the satellite, when the time signal from the GPS receiver is directly distributed to the onboard device inside the satellite, a circuit is added for retiming and receiving each device. Need to be done.

Furthermore, since the time signal from the GPS is generated by a signal from the outside of the satellite of the user, there is a possibility that the function of the time generation system of the satellite stops when the time signal is interrupted.

On the other hand, in the case of the above-mentioned first configuration example, the satellite internal time which governs the timing at which the data processing portion of the satellite internal equipment performs satellite telemetry / command operation, and the GPS time signal which is asynchronously input thereto It is necessary for each user device to have a circuit for synchronizing with the user. Further, when the signal from the GPS satellite is interrupted, the function of maintaining the timing pulse and the absolute time signal needs to be shared by the GPS receiver, so that the GPS receiver needs to have an oscillator and a pseudo-absolute time generation function. Would.

In the second configuration example, since the satellite internal oscillator is calibrated using the timing pulse from the GPS receiver, the drift amount of the time caused by the error of the satellite internal oscillator is corrected by the GPS time. Every time the calibration operation is interrupted due to a change in the duty of the frame rate pulse or the interruption of the calibration operation due to the interruption of the signal from the GPS satellite for a long time, the count value discontinuity occurs when the calibration is resumed. Troubles in the operation of telemetry / commands.

Further, in the third configuration example, since the timing pulse and the time signal from the GPS receiver are used directly as the frame pulse and the satellite internal time, the generation of the frame pulse depends on the timing signal from the GPS receiver. In addition, it is difficult to switch to an alternative signal output when a signal from a GPS satellite is interrupted.

An object of the present invention is to solve the above-mentioned problems and to provide an artificial satellite internal time system capable of obtaining a highly accurate time while maintaining compatibility with a conventional time system. is there.

Another object of the present invention is to provide an artificial satellite internal time system capable of guaranteeing continuation of time data processing even when a signal from a GPS satellite is interrupted.

[0017]

SUMMARY OF THE INVENTION An artificial satellite internal time system according to the present invention is an artificial satellite internal time system including a clock generation circuit for generating a clock signal.
A receiving unit for receiving time information from an artificial satellite used in a wide area positioning system, and the clock information is provided independently of the clock generation circuit and an internal device of the artificial satellite, and the time information received by the receiving unit is the clock. Synchronizing means for synchronizing with a signal and supplying the signal to the internal device.

In another artificial satellite internal time system according to the present invention, in addition to the above configuration, a time signal generating means for generating a time signal based on the time information and the clock signal and supplying the time signal to the internal device. Switching means for switching between output from the synchronizing means to the internal device and output from the time signal generating means to the internal device when the time information is interrupted.

Another artificial satellite internal time system according to the present invention, in addition to the above-mentioned configuration, is a counting means for counting an interval of a pulse signal included in the time information based on the clock signal, and a counting means for counting the time information. A pulse signal generating means for generating the pulse signal based on the counting result of the counting means at the time of interruption.

That is, the internal time system of the present invention comprises:
In addition to the conventional time generation system that depends on the internal oscillator,
A timing pulse output from the internal oscillator is compared with a time signal from a GPS satellite, and a pulse closest to the time signal from the GPS satellite and an absolute time data bus for distributing its absolute time data are added. Therefore, it is possible to obtain a highly accurate time while maintaining compatibility with the conventional time system.

The absolute time data bus is always GP
The interval of the time signal from the S satellite is stored as the pulse count of the internal clock, and when the GPS receiver loses lock, the time distribution is continued using this pulse count. Therefore, continuation of the time data processing can be guaranteed even when the time signal from the GPS satellite is interrupted.

Therefore, by adding a dedicated time line for distributing a time signal from the GPS satellite synchronized with the conventional satellite internal clock, the interface modification on the user equipment side can be minimized and the G
An alternative signal can be supplied when the time signal from the PS satellite is interrupted.

[0023]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention. In the figure, the artificial satellite internal time system according to one embodiment of the present invention includes a satellite internal oscillator 1, a GPS receiver 2, a retiming circuit 3, and a satellite internal device 4.

The GPS receiver 2 receives a signal from the GPS satellite 5 and generates a timing pulse indicating every second and a code indicating the absolute time of the timing pulse. The retiming circuit 3 retiming the timing pulse and the absolute time code received from the GPS receiver 2 with the clock pulse received from the satellite internal oscillator 1, converts the signal into a signal synchronized with the internal clock, and distributes the signal to the satellite internal device 4.

The GPS receiver 2 outputs to the retiming circuit 3 a GPS signal interruption flag for notifying that the signal from the GPS satellite 5 has been interrupted. The retiming circuit 3 stores the interval between the timing pulses received from the GPS receiver 2 (clock pulse count value from the satellite internal oscillator 1), and when the GPS signal interruption flag is sent from the GPS receiver 2, The next timing pulse output time is obtained from the timing pulse output time and the internally stored timing pulse interval, and output is continued. At the same time, a flag indicating the interruption of the GPS signal is set in the time code.

FIG. 2 is a block diagram showing a configuration example of the retiming circuit 3 of FIG. In the figure, a retiming circuit 3 is a retiming flip-flop (retimin).
gflip-flop) (hereinafter, referred to as retiming FF) 31, switch circuits 32, 34, 38, and 43;
Time code register
ter) 33 and a counter (A35)
, A counter (Counter) B36, a pulse counter (Pulse counter) 37, an adder (Adder) 39, and a comparator (Comparato).
r) 40, and AND circuits 41 and 42.

The retiming FF 31 is connected to the satellite internal oscillator 1
A timing pulse based on a signal from the GPS satellite 5 that is asynchronous to a clock pulse (Clockpulse) and an absolute time code [Pulse / Time code]
e (Unsyncronous)] to the GPS receiver 2
, The timing pulse and the absolute time code are synchronized with the clock pulse from the satellite internal oscillator 1, and the timing pulse [Pulse (Syncrono)
us)] and a time code [Time code (Syn)
(close))].

The switch circuit 32 includes a retiming FF 31
Of the time code from the GPS receiver 2 and the addition result of the adder 39, the GPS signal interruption flag (G
The output is switched to the time code register 33 in accordance with the PSR disable flag.

That is, if the GPS signal interruption flag is not input from the GPS receiver 2, the switch circuit 32 outputs the time code from the retiming FF 31 to the time code register 33, and the GPS signal interruption flag is input from the GPS receiver 2. For example, the addition result of the adder 39 is output to the time code register 33.

The time code register 33 includes the switch circuit 3
2 to hold the absolute time code from the retiming FF 31 or the addition result of the adder 39 in synchronization with the clock pulse from the satellite internal oscillator 1, and output the held content to the adder 39.

The switch circuit 34 converts the clock pulse from the satellite internal oscillator 1 into a counter A 35 and a counter B 3 according to the timing pulse from the retiming FF 31.
6 is output.

Each of the counter A 35 and the counter B 36 is provided with a satellite internal oscillator 1 inputted through a switch circuit 34.
, And outputs the counted value to the switch circuit 38. The switch circuit 38 has a counter A3
5 and one of the count values from the counter B 36 are selected according to the timing pulse from the retiming FF 31, and the count value is output to the comparator 40.

For example, when the switch circuit 34 selects the counter B36 as an output destination when the timing pulse from the retiming FF 31 is at a high level, the counter B3
6 counts clock pulses from the satellite internal oscillator 1. At this time, the switch circuit 38 selects the output of the counter A35 different from the output destination of the switch circuit 34, and outputs the count value of the counter A35 to the comparator 40. That is,
Counter A35 and counter B36 are retiming FFs.
The interval (interval) of the timing pulse from the re-timing FF 31 is measured alternately, and the count value obtained when the previous measurement of the interval of the timing pulse from the re-timing FF 31 is output to the comparator 40.

The pulse counter 37 counts clock pulses from the satellite internal oscillator 1 and compares the counted value with a comparator 40.
Output to The pulse counter 37 is reset by a clock pulse from the comparator 40.

The comparator 40 compares one of the count values from the counter A 35 and the counter B 36 input via the switch circuit 38 with the count value from the pulse counter 37, and when they match, generates a clock pulse. Output to the counter 37 and the AND circuit 42. That is,
The comparator 40 outputs a clock pulse at the latest interval of the timing pulse from the retiming FF 31.

The adder 39 adds “1” to the time code from the retiming FF 31 held in the time code register 33 or the addition result of its own circuit, and outputs the addition result to the switch circuit 32 and the AND circuit 42. .

The AND circuit 41 takes the AND of the timing pulse and the time code from the retiming FF 31, and
The calculation result is output to the switch circuit 43. That is, when the timing pulse from the retiming FF 31 is at the high level, the AND circuit 41
Is output to the switch circuit 43.

The AND circuit 42 performs an AND operation on the addition result of the adder 39 and the clock pulse from the comparator 40, and outputs the operation result to the switch circuit 43. That is,
The AND circuit 42 outputs the addition result of the adder 39 when the clock pulse from the comparator 40 is at a high level.
Output to 3.

The switch circuit 43 includes AND circuits 41 and 42.
Is switched according to the GPS signal interruption flag from the GPS receiver 2 and is output to the satellite internal device 4.
That is, the switch circuit 43 outputs the G
If the PS signal interruption flag is not input, the AND circuit 41
, That is, the timing pulse and the time code from the retiming FF 31 are output to the satellite internal device 4,
If the GPS signal interruption flag is input from the PS receiver 2, the output of the AND circuit 41, that is, the addition result of the adder 39 (the time code generated inside the retiming circuit 3)
And a clock pulse (timing pulse generated inside the retiming circuit 3) from the comparator 40 is output to the satellite internal device 4.

As described above, in the normal operation of the retiming circuit 3, the timing pulse and the absolute time code output from the GPS receiver 2 are used for the retiming FF.
Synchronized with the clock pulse from the satellite internal oscillator 1 by 31 and output to the satellite internal device 4.

At the same time, the absolute time code from the GPS receiver 2 is recorded in the time code register 33,
The interval of the timing pulse from the GPS receiver 2 (the number of clock pulses from the satellite internal oscillator 1 from when the timing pulse goes high to the next high level) is counted by the counter A35 or the counter B36. .

The retiming circuit 3 generates a timing pulse and a time code constantly calibrated with the timing pulse and the absolute time code from the GPS receiver 2 based on the above data, and determines that the GPS receiver 2 cannot be used. As soon as the GPS signal interruption flag is set,
The output is switched to the internally generated timing pulse and time code.

FIG. 3 is a timing chart showing the retiming process of the retiming circuit 3 of FIG. 1, and FIG. 4 is a flowchart showing the fault avoiding process when the signal from the GPS satellite 5 is interrupted by the retiming circuit 3 of FIG. It is. The operation of the embodiment of the present invention will be described with reference to FIGS.

The satellite internal oscillator 1 has a TCXO (Tempe
ratture Compensate Crystal
Oscillator (a crystal oscillator with a temperature compensation function) is a timing pulse and satellite time generation circuit that uses the original oscillation. Here, the timing pulse generated by the satellite internal oscillator 1 is frequency-divided in an appropriate cycle, and a clock pulse (a signal defining the length and timing of a data word on a telemetry / command data bus) and a frame rate pulse (telemetry frame) are used. (A signal that defines the length and timing of the signal).

The GPS receiver 2 receives a signal from the GPS satellite 5, and outputs a timing pulse indicating every second of the absolute time and an absolute time code indicating the absolute time of the timing pulse based on the signal. Since the output of the GPS receiver 2 is generated based on the signal from the GPS satellite 5, it is asynchronous with the time generated by the satellite internal oscillator 1.

The retiming circuit 3 receives the clock pulse from the satellite internal oscillator 1, the timing pulse and the absolute time code from the GPS receiver 2, and, as shown in FIG. Retiming the pulse with a clock pulse (sample the timing pulse every second at the rising edge of the clock pulse,
By outputting a pulse only when the signal is at the high level, a timing pulse of every second synchronized with the clock pulse from the satellite internal oscillator 1 is generated.

Following the timing pulse, the retiming circuit 3 adds an absolute time code indicating the absolute time of the timing pulse from the GPS receiver 2 and distributes it to the satellite internal equipment 4.

Further, the retiming circuit 3 has a logic as shown in FIG. 4, and even when the time signal from the GPS satellite 5 is interrupted, the generation of the timing pulse is continued using the timing pulse interval immediately before. I do.

When the retiming circuit 3 receives the clock pulse (Clk pulses) from the satellite internal oscillator 1 (step S1 in FIG. 4), it checks the signal reception status (GPS fail flg set) from the GPS receiver 2 (FIG. 4). In step S2), when GPS data is available (when GPS fail flg is not set), a timing pulse is generated using a timing pulse every second from the GPS receiver 2 (FIG. 4).
Steps S3, S4, S6 to S8).

That is, when the timing pulse of every second from the GPS receiver 2 becomes high level (Step S3 in FIG. 4), the retiming circuit 3 outputs the timing pulse (output pulses) to be output to the satellite internal equipment 4.
Is set to the high level (step S6 in FIG. 4), and the pulse count value (P1) at the timing pulse interval at that time is recorded in the counter A35 or the counter B36 (pulses).
counter value store → P1)
(Step S7 in FIG. 4).

Thereafter, the pulse counter 37 is reset (pulse counter reset) (FIG. 4).
Step S8). If the timing pulse of every second from the GPS receiver 2 does not become high level (step S3 in FIG. 4), the counter A35 or the counter B36 and the pulse counter 37 are respectively incremented (p
uls counter increment) (FIG. 4)
Step S4).

On the other hand, when the GPS data is not available, the retiming circuit 3 outputs the pulse count value (P1) of the previous GPS receiver 2 at the interval of the timing pulse every second.
Is used to generate a timing pulse (step S in FIG. 4).
4-S8).

That is, the comparator 40 uses the pulse counter 3
7 is equal to the count value (P1) of the counter A35 or the counter B36 (pulse counter).
≧ P1) (Step S5 in FIG. 4), the retiming circuit 3 outputs a timing pulse (outp) to be output to the satellite internal device 4.
out pulses) to a high level (step S in FIG. 4).
6) Record the pulse count value (P1) of the timing pulse interval at that time in the counter A35 or the counter B36 (pulse counter value s).
(store → P1) (Step S7 in FIG. 4).

Thereafter, the pulse counter 37 is reset (pulse counter reset) (FIG. 4).
Step S8). Note that the comparator 40 uses the pulse counter 37.
Is not equal to the count value (P1) of the counter A35 or the counter B36 (pulse count).
er <P1) (step S5 in FIG. 4), pulse counter 3
7 is incremented (pulse counter
increment (step S4 in FIG. 4).

FIG. 5 is a diagram showing an example in which the internal time system according to one embodiment of the present invention is applied to observation mission equipment, and FIG. 6 is a timing chart showing the operation of the application example of FIG. An example in which the internal time system according to one embodiment of the present invention is applied to observation mission equipment will be described with reference to FIGS.

The observation mission equipment (satellite internal equipment) 4 fetches a clock pulse and a word rate pulse (or a frame rate pulse) into the mission data formatter 41 in order to output the mission telemetry in synchronization with the satellite internal clock.

At the same time, in the observation mission equipment 4, the mission data formatter 41 sends the mission data generator 44 [if the observation equipment is a CCD (Charge Co.)
Mission data generated by a light receiving element such as a multiple device) is edited, and the mission data formatter 41 edits and outputs a frame format synchronized with a satellite internal clock.

At this time, the observation mission device 4 supplies a clock pulse and a word rate pulse (or a frame rate pulse) to the clock pulse counter 42, and also outputs a timing pulse of every second from the GPS absolute time line to the clock pulse counter 42. To receive.

Here, the clock pulse counter 42 counts the number of clock pulses from the reception of the timing pulse of every second to the frame rate pulse (the head of the telemetry frame), and transfers the counted number to the mission data formatter 41. The code indicating the absolute time corresponding to the timing pulse of every second stored in the absolute time code buffer 43 is transferred to the mission data formatter 41. Mission Data Formatter 4
1 adds these data as a part of the mission data (see FIG. 6).

The terrestrial data processing system determines the time difference between the start time of the frame (= the start time of the frame and the timing pulse of every positive second generated by the GPS receiver 2 and the absolute value of the timing pulse of every positive second included in each frame of the mission data). The code indicating the time) makes it possible to determine the absolute time at which the data was acquired with the accuracy of the clock pulse width (which can be set arbitrarily within the processing speed performance of the signal processing system).

In a conventional time system using a crystal oscillator, a drift of about 30 to 40 msec per day accumulates. However, in the internal time system according to one embodiment of the present invention, even if the same crystal oscillator as that of the conventional system is used, the GPS is not used. 0.5 μs at all times while receiving the time signal from satellite 5
It is possible to maintain the accuracy of ec or less (when the clock is 2 MHz: excluding the error included in the time signal from the GPS satellite 5).

As described above, in addition to the conventional time generating system depending on the internal oscillator, the timing pulse and the absolute time code from the GPS satellite 5 received by the GPS receiver 2 are transmitted from the satellite internal oscillator 1 by the retiming circuit 3. By supplying the clock to the satellite internal device 4 in synchronization with the clock pulse, it is possible to obtain a highly accurate time while maintaining compatibility with the conventional time system. In this case, the clock pulse from the satellite internal oscillator 1 is compared with the time signal from the GPS satellite 5, and the pulse closest to the time signal from the GPS satellite 5 and its absolute time data are transmitted to the satellite internal device 4. A bus is added.

The absolute time data bus is always GP
The interval of the time signal from the S satellite 5 is stored in the counter A35 or the counter B36 as the pulse count of the clock pulse from the satellite internal oscillator 1, and when the GPS receiver 2 loses lock, the pulse count is used by using this pulse count. The distribution of the pulse and its absolute time data to the internal device 4 is continued. Therefore, even when the time signal from the GPS satellite 5 is interrupted, continuation of the time data processing can be guaranteed.

Therefore, by adding a dedicated time line for distributing a time signal from the GPS satellite 5 synchronized with the conventional satellite internal clock, the interface modification on the satellite internal device 4 side is minimized. At the same time, an alternative signal can be supplied when the time signal from the GPS satellite 5 is interrupted.

[0065]

As described above, according to the artificial satellite internal time system of the present invention, in the artificial satellite internal time system including the clock generation circuit for generating the clock signal, the artificial satellite used in the wide area positioning system The clock information is supplied to the internal device in synchronization with the clock signal by a synchronization circuit provided independently of the clock generation circuit and the internal device of the artificial satellite, thereby maintaining compatibility with the conventional time system. There is an effect that a highly accurate time can be obtained.

According to another artificial satellite internal time system of the present invention, the time information from the artificial satellite used for the wide area positioning system is supplied to the internal equipment of the artificial satellite in synchronization with the clock signal, By supplying a time signal generated based on the time information and the clock signal at the time of interruption of information to an internal device, a highly accurate time can be obtained while maintaining compatibility with a conventional time system. There is an effect that continuation of the time data processing can be guaranteed even when the signal from is interrupted.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration example of a retiming circuit of FIG. 1;

FIG. 3 is a timing chart showing a retiming process of the retiming circuit of FIG. 1;

FIG. 4 is a flowchart showing a process of avoiding a failure when a signal from a GPS satellite is interrupted by the retiming circuit of FIG. 1;

FIG. 5 is a diagram showing an example in which the internal time system according to one embodiment of the present invention is applied to observation mission equipment.

FIG. 6 is a timing chart showing an operation of the application example of FIG. 5;

FIG. 7 is a block diagram showing an example of a conventional configuration example.

FIG. 8 is a block diagram showing another example of the conventional configuration example.

FIG. 9 is a block diagram showing another example of the conventional configuration example.

[Description of Signs] 1 Satellite internal oscillator 2 GPS receiver 3 Retiming circuit 4 Satellite internal equipment 5 GPS satellite 31 Retiming flip-flops 32, 34, 38, 43 Switch circuit 33 Time code register 35 Counter A 36 Counter B 37 Pulse counter 39 adder 40 comparator 41,42 AND circuit

Claims (3)

[Claims] 1. An artificial satellite internal time system including a clock generation circuit for generating a clock signal, comprising: a receiving unit for receiving time information from an artificial satellite used in a wide area positioning system; and the clock generation circuit and the clock generation circuit. Synchronization means provided independently of the internal equipment of the artificial satellite and supplying the time information received by the reception means to the internal equipment in synchronization with the clock signal. 2. A time signal generating means for generating a time signal based on the time information and the clock signal and supplying the time signal to the internal device, and an output from the synchronizing means to the internal device when the time information is interrupted. 2. The internal time system according to claim 1, further comprising switching means for switching between output from the time signal generating means and the internal device. 3. A counting means for counting an interval between pulse signals included in the time information based on the clock signal;
3. The internal time system according to claim 1, further comprising: a pulse signal generating unit configured to generate the pulse signal based on a count result of the counting unit when the time information is interrupted.