JPH10173234A - Semiconductor light emitting device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor light emitting device where light emitted from it is least blocked by an electrode and efficiently utilized. SOLUTION: A semiconductor light emitting device is provided with an N electrode 6 arranged so as to be located between the two intersecting sides of an N-type first semiconductor layer 3 and a P electrode 8 arranged so as to be located between the two intersecting sides of an P-type second semiconductor layer 5 formed above the semiconductor layer 3, wherein the N electrode 6 and the P electrode are formed on the same upper side (light emitting plane), the light emitting device is substantially square on a plan view, and moreover the N electrode 6 is square and the P electrode 8 is circular on a plan view. By this setup, a semiconductor light emitting device of this constitution is possessed of a wider light emitting area than a conventional one where both an N electrode and a P electrode are circular.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor light emitting device. More specifically, the present invention relates to a configuration of an electrode of a semiconductor light emitting device.

[0002]

2. Description of the Related Art Al _X In _Y Ga _{1 -X Y} N (X = 0, Y =
0, X = Y = 0), the group III nitride semiconductor is a direct transition type, and thus has high luminous efficiency and emits blue light, which is one of the three primary colors of light. For example, it has recently attracted particular attention as a material for forming a light emitting diode.

[0003] The above-mentioned group III nitride semiconductor constituting a light emitting device is generally formed on an insulating sapphire substrate. Therefore, the electrode cannot be taken out from the substrate side,
A pair of electrodes will be formed on the surface on which the semiconductor layer is formed. The light-emitting device thus configured is mounted on a reflection plate such as a lead frame with the substrate facing down, from the viewpoint of reducing the chip size. Then, wire bonding is performed on the pair of electrodes arranged on the upper surface, that is, on the n-electrode and the p-electrode. Further, according to the electrode configuration disclosed in the invention proposed in JP-A-6-338632, the n-electrode is circular as viewed from a plane, and the p-electrode is square as viewed from a plane.

[0004]

However, recently, there has been a demand for higher integration of semiconductor light emitting devices, that is, a smaller chip size. On the other hand, in order to reliably perform wire bonding, the electrodes are required to have a certain size (for example, a circular electrode has a diameter of 100 μm or more, and a square electrode has a side of 100 μm or more). Therefore, when the chip size of the light emitting element is reduced, the reduction of the light emitting surface (the portion excluding the electrode formation portion from the chip upper surface) due to the arrangement of the electrodes becomes large.

Further, the shapes of the n-electrode and the p-electrode are made different,
At the time of bonding, it is necessary to acquire an image of the work surface in advance and to process the image to recognize the type and position of each electrode.

Accordingly, an object of the present invention is to provide a semiconductor light emitting device in which the influence of the electrode on the light emitting surface can be reduced as small as possible and the light emitting surface of the light emitting device can be arranged efficiently.

[0007]

Means for Solving the Problems The present invention attains the above object, and has a structure in which an n-electrode is arranged so as to be sandwiched between two mutually intersecting sides in an n-type first semiconductor layer. A p-type electrode is disposed so as to be sandwiched between two sides that intersect in a p-type second semiconductor layer formed on the first semiconductor layer, and the n-type electrode and the p-type electrode are formed on the same surface side. In a semiconductor light emitting device having a substantially square shape in a plan view, the n-electrode is substantially square in a plan view, and the p-electrode is substantially circular in a plan view.

According to still another aspect of the present invention, the n
The vertex of the electrode facing the p-electrode is chamfered.

[0009]

According to the first aspect of the present invention, by making the n-electrode a square and the p-electrode a circle,
The light emitting surface can be arranged more efficiently than when the n-electrode is circular and the p-electrode is square as in the conventional example.

According to the second aspect of the present invention, since the apex facing the p-electrode is chamfered in the rectangular n-electrode, the light-emitting surface increases.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below based on embodiments with reference to the drawings. FIG. 1 is a plan view of a light emitting diode 10 according to an embodiment of the present invention, and FIG. 2 is a sectional view taken along line II-II in FIG. This light emitting diode 10 has a configuration in which a buffer layer 2, an n-type first semiconductor layer 3, a light emitting layer 4 having a superlattice structure, and a p-type second semiconductor layer 5 are sequentially stacked on a sapphire substrate 1. . Semiconductor layer 3
To 5 are Al _X In _Y Ga _{1 -X Y} N (X = 0, Y = 0,
X = Y = 0).

The specific specifications of each semiconductor layer are as follows. Buffer layer 2: AlN (50 nm) n layer 3: Si-doped GaN, (2200 nm) Light emitting layer 4: quantum well layer; In _0.16 Ga _0.84 N (3.5 nm) barrier layer; GaN (3.5 nm) quantum well layer and Number of barrier layer repetitions; 5 p layer 5: Mg-doped GaN (75 nm)

In the above, the n-type semiconductor layer 3 can have a two-layer structure including a low electron concentration n layer on the light emitting layer side and a high electron concentration n ⁺ layer on the buffer layer side. The light emitting layer 4 is not limited to the superlattice structure shown in FIG. 2, but may be a single hetero type, a double hetero type, or the like. A wide band gap Al _X In _Y Ga ₁ -XYN doped with an acceptor such as magnesium between the light emitting layer 4 and the p-type second semiconductor layer 5 (X = 0, Y = 0, X = Y = 0 (including 0) layer. This is to prevent the electrons injected into the light emitting layer 4 from diffusing into the p-type semiconductor layer 5. The p-type semiconductor layer 5 has a low hole concentration p on the light emitting layer side.
It can have a two-layer structure including a layer and a high hole concentration p ⁺ layer on the electrode side.

The semiconductor layers 2 to 5 on the substrate 1 are formed by metalorganic compound vapor phase epitaxy (hereinafter, referred to as "MOVPE"). In this growth method, ammonia gas and II
A group I element alkyl compound gas, for example, trimethylgallium (TMG), trimethylaluminum (TMA) or trimethylindium (TMI) is supplied to a substrate heated to an appropriate temperature and subjected to a thermal decomposition reaction to thereby produce a desired crystal. Is grown on the substrate. Since a method for forming these semiconductor layers using the MOVPE method is well known, the description of the specific conditions is omitted. For details, see JP-A-8-9747.
See No. 1 publication.

The semiconductor layer structure obtained as described above is subjected to reactive ion etching to form a surface on which an n-electrode is to be formed and a cutting allowance 15 for dicing. Effective part of the light emitting diode of this embodiment (part excluding cut margin 15)
Is a square having a side of 300 μm when viewed from a plane. The cutting margin 15 has a width of 20 μm.

After that, Al (aluminum) is vapor-deposited to form the n-electrode 6 into a substantially square having a side of 120 μm. The thickness of the n-electrode 6 is 1.5 μm. Note that V (vanadium), Nb (niobium), Zr (zirconia), Cr (chromium), or the like may be deposited as a base layer before depositing Al. A first clearance 11 having a width of 10 μm is provided between the n-electrode 6 and the etching wall surface. Further, the n-electrode 6 is arranged such that its vertex (the upper left vertex in the figure) substantially coincides with the vertex of the effective portion of the element. This is to make the area of the light emitting surface reduced by the n-electrode 6 as small as possible. The n-electrode 6 is the cutting portion 1
It may be slightly protruding to 5. The shape of the n-electrode 6 is not limited to the square shape in plan view shown in the embodiment.
A rectangle, a parallelogram, a rhombus, or the like can be employed.

Next, a translucent electrode 7 is deposited on the p-type second semiconductor layer 5 to a thickness of 10 nm. The translucent electrode 7
A second clearance 12 having a width of 10 μm is provided between the substrate and the etching wall surface.

Then, a substantially circular p-electrode 8 having a diameter of 120 μm as viewed from above is deposited on the translucent electrode 7.
The thickness of the p-electrode 8 is 1.5 μm. The p-electrode 8 is provided so that its circumferential portion is inscribed in two continuous sides when the element is viewed from a plane. These two sides are preferably different from the two sides sandwiching the n-electrode 6 when the element is viewed from a plane. This is to make the gap between them as large as possible to facilitate the bonding operation.

It is preferable that the p-electrode 8 and the translucent electrode 7 are formed of the same metal material. In this embodiment, A
These were formed by u (gold), but Pt (platinum), Pd (palladium), Ni (nickel), Co
(Cobalt) and alloys containing these can be used.

As described above, the material for forming the n-electrode and the p-electrode is deposited on the semiconductor layer and heat-treated to form each electrode. After that, the semiconductor wafer is cut for each element to obtain a desired light emitting diode. The light emitting diode of this embodiment has a peak wavelength at 520 nm.

The light emitting diode 10 of the embodiment obtained as described above (ie, an effective area of 300 μm square, 120 μm square)
Square n-electrode 6 and 120 μmφ circular p-electrode 8)
According to this, the area of the light emitting surface, that is, the area of the translucent electrode (hatched portion in the figure) is about 59,100 μm ² .

On the other hand, as shown in FIG.
In the case of the comparative example in which the n-electrode 60 is circular and the p-electrode 80 is square (the other configuration is the same as the light-emitting diode 10 in FIG. 1), the light-emitting surface area is about 58,400 μm ² .
In the element 100 shown in FIG. 3, the width of each of the first clearance 110 and the second clearance 120 is 10 μm.

From the above results, it can be seen that the light emitting diode 10 of the example increases the light emitting surface by about 1% as compared with that of the comparative example.

FIG. 4 shows a light emitting diode 2 of the second embodiment.
0 is indicated. The same members as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be partially omitted. According to the light emitting diode 20, the apex of the n-electrode 26 facing the p-electrode 8 is chamfered (or rounded). In this embodiment, the length of the chamfer is
m. That is, the length of the hypotenuse 27 in the figure is (15 ² +
15 ² ) ^1/2 = about 21 μm. Note that this chamfering must be performed so that no error occurs in recognition of the n-electrode in the image processing during the bonding operation. Therefore, the length of the chamfer is preferably 30% or less of the length of one side of the n-electrode.

According to the light emitting diode 20, the area of the light emitting surface is about 59,500 μm ² . Therefore, as compared with the comparative example shown in FIG. 3, the light emitting area is increased by about 2%. Incidentally, when the p-electrode 80 shown in FIG. 3 is similarly chamfered, the area of the light emitting surface is 100
It increases only by μm ² (about 0.2%).

FIGS. 5 and 6 show a light emitting diode 120 according to another embodiment. The same members as those in the previous embodiment are denoted by the same reference numerals, and description thereof will be omitted. In a light emitting diode of the type shown in this embodiment, as shown in FIG. 6, a cut-off 115 includes an n-type first semiconductor layer 3, a light-emitting layer 4, and a p-type second semiconductor layer 5 of the diode. The wall 150 is formed by these layers.

That is, a recess is formed in the semiconductor layers 3 to 5 by reactive ion etching, and an n-electrode 126 is formed inside the recess. In other words, the n-electrode 126 is arranged at an interval from two continuous sides in the n-type first semiconductor layer 3 and sandwiched therebetween.

The first clearance 121 between the n-electrode 126 and the etching wall has substantially the same width (10 μm) over the entire circumference of the n-electrode 126.

In this embodiment, as the n-electrode 126, the one having a chamfered side of the apex facing the p-electrode 128 when viewed from a plane is 115 μm. The length of the chamfer is 15 μm from each vertex. As the p-electrode 128, a circular one having a diameter of 115 μm when viewed from a plane was used.

When the length of the longest side of the translucent electrode 127 is 300 μm as shown in FIG. 5, the area of the translucent electrode 127, that is, the area of the light emitting surface is about 59,00.
0 μm ² .

On the other hand, as a comparative example, as shown in FIG.
The shape of each of the electrode 260 and the p-electrode 280 is circular (115 μmφ) and square with a chamfer (115 μm
□), the light-transmitting electrode 2 of the light emitting diode 200
The area of 70 is about 58,700 μm ² . FIG.
, Reference numeral 215 denotes a cutting margin, and reference numerals 221 and 222
Denotes first and second clearances, and reference numeral 250 denotes a wall.

Accordingly, the light emitting diode 120 shown in FIG.
In this case, the area of the light emitting surface is increased by about 0.5% as compared with the light emitting diode 200 of the comparative example shown in FIG.

In each of the above embodiments, a light-transmitting electrode is not required if the light-emitting element is made of, for example, a GaAs-based semiconductor or a semiconductor other than the group III nitride.

The present invention is not limited to the description of the above-described embodiments and examples, but includes various modifications which can be made by those skilled in the art without departing from the scope of the claims.

The following matters are disclosed. (1) An n-electrode is arranged on a line connecting opposite vertices in the n-type first semiconductor layer and at a position deviated from the center, and a p-type electrode formed on the first semiconductor layer is formed. In the second semiconductor layer, the p-electrode is disposed on a line connecting the opposite vertices and at a position deviated from the center, and the n-electrode and the p-electrode are formed on the same surface side in plan view. In a substantially square semiconductor light emitting device, the n
A semiconductor light-emitting device, wherein the electrode is substantially square in plan view, and the p-electrode is substantially circular in plan view.

(2) An n-electrode is arranged so as to be sandwiched between two continuous sides in the n-type first semiconductor layer,
A p-type electrode is arranged so as to be sandwiched between two continuous sides in a p-type second semiconductor layer formed on the semiconductor layer of
The n-electrode and the p-electrode are formed on the same surface side and are substantially square in a plan view. The n-electrode is substantially square in a plan view. A semiconductor light emitting device having a substantially circular shape when viewed.

(3) The semiconductor light emitting device according to (2), wherein the n-electrodes are arranged at an interval from the two continuous sides.

(4) The semiconductor light emitting device according to any one of (1) to (3), wherein a vertex of the n electrode facing the p electrode is chamfered.

[Brief description of the drawings]

FIG. 1 is a plan view of a light emitting diode according to an embodiment of the present invention.

FIG. 2 is a sectional view of the light emitting diode (indicated by the line II-II in FIG. 1).

FIG. 3 is a plan view of a light emitting diode of a comparative example.

FIG. 4 is a plan view of a light emitting diode according to another embodiment of the present invention.

FIG. 5 is a plan view of a light emitting diode according to another embodiment of the present invention.

FIG. 6 is a sectional view of the light emitting diode (shown by a VI-VI line in FIG. 5).

FIG. 7 is a plan view of a light emitting diode of a comparative example.

[Explanation of symbols]

 Reference Signs List 1 substrate 3 n-type semiconductor layer 4 light-emitting layer 5 p-type semiconductor layer 6, 26, 60, 126, 260 n-electrode 8, 28, 80, 128, 280 p-electrode 7, 70, 127, 270 translucent electrode 10, 20, 100, 120, 200 light emitting diodes

Claims (2)

[Claims] An n-electrode is arranged so as to be sandwiched between two sides that intersect in an n-type first semiconductor layer, and in a p-type second semiconductor layer formed on the first semiconductor layer. A semiconductor light emitting device having a substantially quadrangular shape in plan view, wherein a p-electrode is disposed so as to be sandwiched between two intersecting sides, and the n-electrode and the p-electrode are formed on the same surface side. A semiconductor light-emitting device, wherein the semiconductor light-emitting device is substantially square when viewed from above, and the p-electrode is substantially circular when viewed from above. 2. The semiconductor light emitting device according to claim 1, wherein a vertex of the n electrode facing the p electrode is chamfered.